TWI455245B - 製造半導體裝置之方法 - Google Patents

製造半導體裝置之方法 Download PDF

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Publication number
TWI455245B
TWI455245B TW097111074A TW97111074A TWI455245B TW I455245 B TWI455245 B TW I455245B TW 097111074 A TW097111074 A TW 097111074A TW 97111074 A TW97111074 A TW 97111074A TW I455245 B TWI455245 B TW I455245B
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TW
Taiwan
Prior art keywords
layer
substrate
semiconductor substrate
single crystal
semiconductor
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Application number
TW097111074A
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English (en)
Chinese (zh)
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TW200908209A (en
Inventor
山崎舜平
大沼英人
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半導體能源研究所股份有限公司
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Publication of TW200908209A publication Critical patent/TW200908209A/zh
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Publication of TWI455245B publication Critical patent/TWI455245B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
TW097111074A 2007-05-11 2008-03-27 製造半導體裝置之方法 TWI455245B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007127270 2007-05-11

Publications (2)

Publication Number Publication Date
TW200908209A TW200908209A (en) 2009-02-16
TWI455245B true TWI455245B (zh) 2014-10-01

Family

ID=39969907

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097111074A TWI455245B (zh) 2007-05-11 2008-03-27 製造半導體裝置之方法

Country Status (5)

Country Link
US (3) US7601601B2 (https=)
JP (1) JP5348939B2 (https=)
KR (1) KR101443580B1 (https=)
CN (1) CN101303967B (https=)
TW (1) TWI455245B (https=)

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JP5507063B2 (ja) 2007-07-09 2014-05-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
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JP5618521B2 (ja) * 2008-11-28 2014-11-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI607670B (zh) 2009-01-08 2017-12-01 半導體能源研究所股份有限公司 發光裝置及電子裝置
JP2010161671A (ja) * 2009-01-09 2010-07-22 Murata Mfg Co Ltd 圧電デバイスの製造方法
JP5607399B2 (ja) * 2009-03-24 2014-10-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8043938B2 (en) * 2009-05-14 2011-10-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and SOI substrate
GB0914251D0 (en) 2009-08-14 2009-09-30 Nat Univ Ireland Cork A hybrid substrate
JP5866088B2 (ja) * 2009-11-24 2016-02-17 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5926887B2 (ja) * 2010-02-03 2016-05-25 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5355618B2 (ja) * 2011-03-10 2013-11-27 三星ディスプレイ株式會社 可撓性表示装置及びこの製造方法
JP6040609B2 (ja) * 2012-07-20 2016-12-07 東京エレクトロン株式会社 成膜装置及び成膜方法
KR102007834B1 (ko) * 2013-06-27 2019-08-07 엘지디스플레이 주식회사 가요성 표시장치의 제조방법
US10510560B2 (en) * 2015-09-04 2019-12-17 Nanyang Technological University Method of encapsulating a substrate
CN108417523B (zh) * 2018-04-16 2020-08-04 歌尔股份有限公司 Led衬底的剥离方法
CN108493106B (zh) * 2018-05-15 2020-10-02 浙江蓝晶芯微电子有限公司 一种半导体晶圆刻蚀方法
US11050012B2 (en) * 2019-04-01 2021-06-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method to protect electrodes from oxidation in a MEMS device
US11728199B2 (en) * 2019-12-23 2023-08-15 Asmpt Nexx, Inc. Substrate support features and method of application
CN111106029B (zh) * 2019-12-31 2023-02-10 深圳市锐骏半导体股份有限公司 一种晶圆快速热处理机台的监控方法
CN111366618B (zh) * 2020-04-01 2022-07-29 上海华虹宏力半导体制造有限公司 一种温湿度传感器及其制造方法
KR20230154933A (ko) * 2021-03-09 2023-11-09 도쿄엘렉트론가부시키가이샤 반도체 칩의 제조 방법 및 기판 처리 장치
TWI912570B (zh) * 2021-12-16 2026-01-21 新加坡商發明與合作實驗室有限公司 高性能運算和高儲存容量的同構/異構積體電路系統
US20240258118A1 (en) 2023-01-27 2024-08-01 Destination 2D Inc. Large-area wafer-scale cmos-compatible 2d-material intercalation doping tools, processes, and methods, including doping of synthesized graphene

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Also Published As

Publication number Publication date
KR20080100120A (ko) 2008-11-14
US20090309183A1 (en) 2009-12-17
CN101303967B (zh) 2012-05-30
US20110114948A1 (en) 2011-05-19
KR101443580B1 (ko) 2014-10-30
JP2008311635A (ja) 2008-12-25
US7902041B2 (en) 2011-03-08
TW200908209A (en) 2009-02-16
US7601601B2 (en) 2009-10-13
US8629433B2 (en) 2014-01-14
US20080280417A1 (en) 2008-11-13
CN101303967A (zh) 2008-11-12
JP5348939B2 (ja) 2013-11-20

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