TWI452956B - 撓性電路 - Google Patents

撓性電路 Download PDF

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TWI452956B
TWI452956B TW097118741A TW97118741A TWI452956B TW I452956 B TWI452956 B TW I452956B TW 097118741 A TW097118741 A TW 097118741A TW 97118741 A TW97118741 A TW 97118741A TW I452956 B TWI452956 B TW I452956B
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electrically insulating
insulating layer
conductive layer
layer
opening
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TW200922430A (en
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Ellen Oesterle Aeling
Michael Alan Meis
Byron Mathew Jackson
John Richard David
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3M Innovative Properties Co
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
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    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
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    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4635—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards
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    • H05K1/02—Details
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
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    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
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    • H05K2203/063—Lamination of preperforated insulating layer
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
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    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Description

撓性電路
本發明係關於電路，例如撓性電路。
使用電路及光操縱裝置之照明裝置在此項技術大量應用中已為吾人所熟知。這類裝置包括一光源，及向該光源與某一光操縱裝置(例如以一所需方式引導該光源所產生光線之反射器或漫射器)供電之電路。這類裝置特別可用於試圖提供具有最小空間利用之照明，尤其在薄型光導管或光操縱裝置情況下。但是，主要用於提供照明之已知光裝置及器具通常採用裝納諸如白熾光燈泡器具或類似照明裝置等之照明裝置的龐大外殼。特別是，例如像標誌、字型燈及顯示器等應用，該等已知照明裝置佔用一相對大量之空間。
使用一電路基板之照明裝置可為以銅電路及元件安裝孔形成圖案之玻璃纖維基板。該等剛性電路板，即已知的FR4電路板，經設計成剛硬的。因而，其不適合安裝至不平坦的表面上。撓性電路存在，且其通常由薄膜(諸如那些以商業名稱KAPTON所銷售之聚醯亞胺薄膜)上之圖案化銅製成。該等電路提供撓性優勢，但承受較高生產成本之苦。另外，該等電路通常由一步驟及重複圖案製程製成。該製程提供許多困難於對準層上之部件及於層之間作連接。因而，該製程既昂貴且維修費用很高。
在一實施例中，本申請案係關於一種製造一多層電路之方法。該方法包括提供一包含開孔貫穿於其中之第一電絕緣層，及接合該第一電絕緣層與一第一導電層。該第一導電層係對準該電絕緣層中之開孔以接合於該第一電絕緣層，且該多層電路在一持續不變的速度下製造。
在另一實施例中，該方法包括提供一第二電絕緣層及接合該第二電絕緣層與相對於該第一電絕緣層之該第一導電層。
 方法
本申請案係關於一多層撓性電路。該電路可輸送一電流。該方法包括提供一電絕緣層。該電絕緣層接合於一導電層。該等層可藉由永久性黏接劑接合或可彼此移離。該連接可由許多方法完成。在一些實施例中，該連接由一機械製程完成。亦即，兩個分離層之間形成接合，且該導電層並不化學沉積到該電絕緣層上。例如，一層壓製程或使用一黏合劑將該電絕緣層與該導電層連接在一起。圖1闡明該方法之一實施例。圖1中，製程10包括一電絕緣層12。該絕緣層12接著被接合於一導電層14。
本申請案之方法在一持續不變之速度下執行。為了本申請案之目的，一持續不變之速度係定義為：一部分該電路在製造中的任意階段期間均以一恆定速度移動。例如，在該方法中之每一步驟，該電絕緣層與該導電層的移動速度相同於合成之多層電路的移動速度，該合成之多層電路包含那些電絕緣層與導電層部分。
在一些實施例中，該電絕緣層在連接其與該導電層之前被穿孔。該穿孔形成開孔於該電絕緣層中。這些開孔可以一有序圖案或一隨機圖案排列於該電絕緣層上。接著該多層電路上之後續層係對準該導電層上之開孔。為了本申請案之目的，一項目在其相對於另一項目具有正確對準或定位時係與另一項目對齊。
一電絕緣層係不導電的。該電絕緣層一般係一撓性基板。在某些實施例中，該電絕緣層亦是隔熱的。在其它實施例中，該電絕緣層係導熱的。在一些實施例中，該撓性基板係一高分子膜，例如一光增強膜。
該導電層一般係一自持層，且可由任意導電材料形成。一般地，該導電層係由可製成一薄片之材料形成。
該導電層可為連續性或不連續性。在導電層為不連續性之實施例中，電路在該導電層中斷處中斷。該導電層可為按一圖案之一完整薄片。合適圖案之例子包括格子圖案、串線圖案、串聯/並聯圖案、一系列的並聯圖案、一並聯陣列線，或其組合。
本發明所用之黏合劑可為任意適合於連接該電絕緣層至該導電層之黏合劑。在一些實施例中，該黏合劑係一壓敏性黏合劑。在一些實施例中，該黏合劑係一經熱處理之黏合劑，例如一熱熔黏合劑。
在許多實施例中，該多層電路包括一第二電絕緣層及一第二導電層。圖1顯示該第二電絕緣層16及該第二導電層18。另外，該方法可包括一覆蓋該多層電路之底膜19。該 底膜可為一附加電絕緣層或一獨立高分子膜，或兩者之組合。
圖2闡明根據本申請案之製程所製之多層電路的一實施例。由本申請案之製程所製之多層電路之特定實施例可於(例如)同在審理中之美國專利申請案第＿＿＿＿號中找到，其主張美國申請案第60/826,245號(代理人檔案號碼60609US011)之優先權，該案以引用方式併入本文中。一第一導電層42可由一金屬箔組成，例如銅箔或其他適合可製成薄片或薄層的導體。佈置於該第一導電層42之上的係一第一電絕緣或不導電層44。在一些實施例中，另一電絕緣或不導電層可被佈置於該第一導電層42之下，將該導電層42夾於該二不導電層之間。該第一電絕緣層44包括一或多個貫穿該層之開孔46。該第一電絕緣層44可由任意已知電絕緣體或可製成薄片或薄層的介電體組成，或一光反射層，如上所述。另外，層44可包含一黏合劑於一面或兩面，用於黏合層44於相鄰層，例如第一導電層42。
在圖2所示實施例中，裝置40進一步包括一第二導電層48，其被佈置於第一電絕緣層44上表面上。附加的多個層可在本申請案之範圍內被加入。第二導電層48包括一或多個貫穿該層之開孔50且可由一金屬箔，例如一銅箔或其他適合可製成薄片或薄層的導體組成。開孔50及46被配置為相互對齊或對準。最後，裝置40包括膜層52。膜層52可由一反光材料組成或具有某種其它光操縱性質，就如上述的光反射膜。層52包含一或多對開孔54，每對開孔54包括第 一開孔56及第二開孔58。第一開孔56分別與該第一導電層44及該第二導電層48中的孔46及50對齊或對準。圖2以縱虛線顯示該對準。因而，一照明源具有至少兩端(例如一具有陽極端及陰極端之LED)，其被佈置於層52上表面上，該照明源可透過開孔56、50及46與第一導電層42發生電接觸。該光照明源另一端可透過開孔58與該第二導電層48電連通。在一些實施例中，層52包含一單個大開孔，取代每對開孔54之第一開孔56及第二開孔58。
裝置40也包括一或多個光源或照明源60，其可係一或多個具有兩個觸點(即，一陽極與一陰極)的發光二極體(LED)，但並不限於此。可使用的LED之例子包括各種顏色的LED，例如白色、紅色、橙色、琥珀色、黃色、綠色、藍色、紫色，或任意其它此項技術中已知之LED顏色。該等LED亦可為取決於正向偏壓還是反向偏壓而發射多種顏色之類型，或係發射紅外線或紫外光之類型。此外，該等LED可包含多種類型的封裝LED或裸露LED晶粒，以及單片電路板類型裝置或一使用電路引線或導線之配置。
應注意第二導電層48的上表面或是光學薄膜層52的下表面可包含一黏合劑以使層48與52黏合在一起。另外，組合後裝置40之該等層被層壓在一起以形成一整體結構。
圖3闡明圖2裝置通過截面線3－3之展開橫截面，該截面線延伸過裝置40之整個垂直橫截面距離。如圖所示，一照明源60之一部分62被置於對準之開孔56、50及46正上方以 允許該部分62與該第一導電層42之間電連通。該照明裝置60之另一部分64被置於開孔58正上方，以提供電連通於該部分64及第二導電層48之間。因此，一電源，例如一電壓源66，可橫跨該第一及第二導電層42及48而被連接(如圖所示)以供電來驅動該照明源60。
如上所指明，在一些實施例中，該光源係一小型發光二極體(LED)。在這點上，「LED」係指可發射無論是可見光、紫外光或紅外光的光的二極體。其包括以「LED」名稱銷售之非相干包裝或封裝的半導體裝置，無論是常規或者超級輻射種類。如果該LED發射諸如紫外光之不可見光，且在一些發射可見光的情況中，其經封裝成包含一磷光體(或其可照明一遠置磷光體)以轉換短波長光為較長波長可見光，在一些情況中產生一發射白光之裝置。一「LED晶粒」係一最基本形式的LED，即，由半導體加工程序製造之呈單獨組件或晶片的形式。該組件或晶片可包含適用於施加電力以使該裝置通電的電接觸。該組件或晶片的單獨層及其它功能元件通常係形成於晶圓尺度上，且完工的晶圓隨後可被切割成單片部件以產生大量LED晶粒。本文提供了更多關於封裝LED，包括向前發射及側發射型LED的討論。
如果需要，其它諸如線性冷陰極螢光燈(CCFL)或熱陰極螢光燈(HCFL)之光源可用於(替代或除了分離的LED源之外)作為已揭示之背光的照明源。另外，可使用以下混合系統：諸如像是包括冷白及暖白之CCFL/LED；諸如那些 發射不同光譜之CCFL/HCFL。光發射器之組合可廣泛地變化，並包括多個LED與CCFL，且多數為諸如像是多個CCFL、不同顏色的多個CCFL，及多個LED與CCFL者。
在一些實施例中，光源包括能產生具有不同峰值波長或顏色之光的光源(例如，一系列紅色、綠色，及藍色LED)。
在一些實施例中，一透明薄膜或其它光控薄膜係接合至光源之電子組件上方的該多層電路。因此該透明薄膜保護該光源免受外部損害。在其它實施例中，一半透明薄膜係接合於光源之電子組件上方之該多層電路。因此該半透明薄膜保護該光源免受外部損害且使光線漫射，該光線經放射以提高其均一性。
本申請案所揭示之方法可以一連續製程進行。亦即，該多層電路之長度只受限於用於該等層之饋送膜長度。該方法也可為一卷對卷連續製程而設定。這一方法可在超過每分鐘300英呎的速度下進行。
在另外的實施例中，該多層電路從其卷形式被切斷以形成更小的電路。
在不背離本發明之精神與範圍下，本發明之各種修改及變動對那些熟習此項技術者係顯而易知的。
10‧‧‧製程
12‧‧‧電絕緣層
14‧‧‧導電層
16‧‧‧第二電絕緣層
18‧‧‧第二導電層
19‧‧‧底膜
40‧‧‧裝置
42‧‧‧第一導電層
44‧‧‧第一電絕緣層
46‧‧‧開孔
48‧‧‧第二導電層
50‧‧‧開孔
52‧‧‧光學薄膜層
54‧‧‧開孔
56‧‧‧第一開孔
58‧‧‧第二開孔
60‧‧‧照明源
62‧‧‧照明源之一部分
64‧‧‧照明源之一部分
66‧‧‧電壓電源
圖1係根據本申請案之一實施例的製程圖。
圖2係一已公開照明裝置之另一實例的透視展開圖。
圖3闡明圖2之裝置通過截面線3－3之展開橫截面。
40‧‧‧裝置
42‧‧‧第一導電層
44‧‧‧第一電絕緣層
46‧‧‧開孔
48‧‧‧第二導電層
50‧‧‧開孔
52‧‧‧光學薄膜層
54‧‧‧開孔
56‧‧‧第一開孔
58‧‧‧第二開孔
60‧‧‧照明源

Claims (20)

  1. 一種製造多層電路的方法，其包括：提供一第一導電層；提供一第一電絕緣層，其具有複數個開孔；提供一第二導電層，其具有複數個經構形以與該第一電絕緣層之開孔相對準之開孔；提供一第二電絕緣層，其具有複數個開孔，該第二電絕緣層之該等開孔具有一第一組開孔，該第一組開孔經構形以與該第一電絕緣層之開孔及該第二導電層之開孔對準，該第二電絕緣層之該等開孔另具有一組額外開孔，該組額外開孔經構形以不與該第一電絕緣層之開孔及該第二導電層之開孔對準；將該第一電絕緣層之一第一側與該第一導電層相結合；將該第一電絕緣層之一第二側結合至該第二導電層之一第一側，且該第一電絕緣層之開孔與該第二導電層之開孔相對準；將該第二導電層之該第二側結合至該第二電絕緣層，且該第二導電層之開孔與該第二電絕緣層之第一組開孔相對準；及其中該第二導電層之開孔在與該第一或第二電絕緣層相結合之前即已存在。
  2. 如請求項1之方法，其中該導電層係經由一機械製程被接合於該第一電絕緣層。
  3. 如請求項1之方法，其中該等層之結合包含在相鄰表面之間布置一黏著層。
  4. 如請求項1之方法，其進一步包括將該多層電路切割成若干較小電路。
  5. 如請求項1之方法，其中該第一電絕緣層係一撓性基板。
  6. 如請求項1之方法，其中該第一電絕緣層係一高分子膜。
  7. 如請求項3之方法，其中該黏合劑係一壓敏性黏合劑。
  8. 如請求項3之方法，其中該黏合劑係熱活化的。
  9. 如請求項1之方法，其中該結合步驟包含層壓動作。
  10. 如請求項1之方法，其進一步包括將至少一光源放置於該多層電路上，且其中該光源係經由該第一電絕緣層、該第二導電層及該第二電絕緣層之開孔電耦合至該第一導電層，且其中該光源係額外地經由該第二電絕緣層中之額外開孔電耦合至該第二導電層。
  11. 如請求項10之方法，其包括多個光源於該多層電路上。
  12. 如請求項11之方法，其中該多個光源按一圖案佈置。
  13. 如請求項12之方法，其中該圖案係一規則陣列。
  14. 如請求項10之方法，其中該光源係一發光二極體。
  15. 如請求項1之方法，其包括附接一電子元件至該第一導電層。
  16. 如請求項1之方法，其中該電路以每分鐘大於300英呎的速度進行。
  17. 如請求項1之方法，其中該方法包含形成一連續電路，且該方法係一卷對卷連續製程。
  18. 如請求項10之方法，其包括附接一透明層或一半透明層在該光源正上方。
  19. 如請求項1之方法，其中該結合步驟係作為一卷對卷製程的一部份而執行。
  20. 如請求項1之方法，其中該結合步驟係在一持續不變速度下執行。
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JP2010529652A (ja) 2010-08-26
EP2156716A1 (en) 2010-02-24
KR20100028581A (ko) 2010-03-12
WO2008150622A1 (en) 2008-12-11
TW200922430A (en) 2009-05-16
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CN101683009A (zh) 2010-03-24
EP2156716A4 (en) 2011-07-20
US20080295327A1 (en) 2008-12-04

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