TWI446491B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI446491B
TWI446491B TW098104518A TW98104518A TWI446491B TW I446491 B TWI446491 B TW I446491B TW 098104518 A TW098104518 A TW 098104518A TW 98104518 A TW98104518 A TW 98104518A TW I446491 B TWI446491 B TW I446491B
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wafer
die
semiconductor wafer
semiconductor
substrate
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TW200947628A (en
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Catherine Bee Liang Ng
Chin Hock Toh
Anthony Yi Sheng Sun
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United Test & Assembly Ct Lt
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Description

半導體封裝及其製造方法
本發明係關於一種包含兩個或兩個以上相互垂直堆疊之晶粒之半導體裝置及該半導體裝置之製造方法。
本申請案主張2008年2月12日申請之美國臨時申請案第61/027,843號之優先權，且該臨時申請案係以全文引用之方式併入本文中。
多個倒裝晶片於堆疊晶粒封裝中之垂直堆疊需要晶圓經加工而具有貫通矽互連件(through silicon interconnect)以致能面對背(face-to-back，F2B)倒裝晶片接合。在形成互連件之過程期間晶圓通常經薄化或經背側面研磨，且因此堆疊薄化晶圓之已知過程需要在處理及設備加工期間臨時接合至晶圓之支撐載體以防止翹曲。更特定言之，支撐載體在晶圓級貫通矽互連件製造過程及晶圓級裝配過程中可改良薄化晶圓之剛性。然而，將支撐載體接合至晶圓之過程涉及額外過程及材料之開發、額外設備投資、增加之封裝費用及針對將支撐載體接合至晶圓及支撐載體自晶圓之去接合的額外過程步驟。形成堆疊晶粒封裝之例示性已知過程將參考圖1(a)至1(d)說明。
圖1(a)展示形成臨時接合至第一支撐載體之薄化晶圓之已知過程。該過程以前表面1a經蝕刻以在其中形成通道2之晶圓1開始。通道2自晶圓1之前表面1a延伸且部分進入晶圓1中。晶圓1之前表面1a及通道2經鍍覆有一介電層、一障壁金屬層及一晶種層(一起以數字3表示)。接著用諸如銅(Cu)之金屬材料4填充經鍍覆之通道2以形成貫通矽互連件5。此後，在晶圓1之前表面1a上形成金屬化層及鈍化層(一起以數字6表示)。為了準備晶圓1用於薄化或背側面研磨，利用接合材料7a將第一支撐載體7接合至晶圓1之前表面1a。晶圓1之薄化發生在與前表面1a相對之後表面1b上。背側面研磨晶圓1直至貫通矽互連件5之後端部分5a曝露。在薄化晶圓1之後表面1b上形成金屬化層及鈍化層(一起以數字8表示)，接著形成下部凸塊金屬化(under bump metallization，UBM)墊9。在下部凸塊金屬化墊9上形成焊料凸塊10。
圖1(b)(i)及圖1(b)(ii)展示將倒裝晶片11堆疊於圖1(a)之具有UBM墊9之薄化晶圓上的已知過程。為準備薄化晶圓之前表面1a用於堆疊，利用接合材料12a將第二支撐載體12臨時接合於晶圓之後表面1b，接著自前表面1a移除(去接合)第一支撐載體7。將倒裝晶片11堆疊在晶圓1之前表面1a上方以使倒裝晶片11之焊料凸塊13與晶圓1之貫通矽互連件5對準。接著用樹脂14下部填充倒裝晶片11，且移除第二支撐載體12。接著在晶圓1之後表面1b上提供焊料凸塊15。將其上堆疊倒裝晶片11之晶圓1單一化為安裝於基板17上之個別單元16。在單一化為個別封裝之前，總成經用成型材料18覆模成型且經安裝焊料球19。
圖1(c)(i)及圖1(c)(ii)展示將倒裝晶片11堆疊於圖1(a)之具有UBM墊9及焊料凸塊10之薄化晶圓1上的替代已知過程。自薄化晶圓1移除第一支撐載體7。將晶圓1單一化為安裝於基板17上之個別晶粒。將倒裝晶片11堆疊於晶粒之前表面上以使倒裝晶片11之焊料凸塊13與晶粒之貫通矽互連件5對準。接著用樹脂14下部填充倒裝晶片11，且將整個總成用成型材料18覆模成型。在基板17之下側面上形成焊料球19，接著單一化為個別封裝。
圖1(d)展示由圖1(a)及圖1(b)或圖1(a)及圖1(c)描述之過程產生之半導體封裝。
形成堆疊晶粒封裝之已知過程涉及使用一或多個可產生上述突出缺點之支撐載體。因此，對提供可至少減少使用支撐載體或避免使用支撐載體之過程存在需要。
本發明提供一種包含兩個或兩個以上相互垂直堆疊之晶粒之半導體裝置及該半導體裝置之製造方法。
不同於如上所述之已知過程，晶圓不需要徹底加工以繼續進行晶粒堆疊過程。即，晶圓在其他晶片可堆疊其上之前不需要經歷貫通矽互連件形成與晶圓薄化過程。實情為，晶片之堆疊可在應已完成貫通矽互連件製造過程而未完成晶圓薄化過程之半加工晶圓上實現。當晶片堆疊於未薄化晶圓上時且當堆疊結構經成型時，未薄化晶圓提供對總成之支撐。
成型後，發生晶圓之薄化。薄化期間成型材料提供對總成之支撐，且在諸如背側面金屬化/鈍化、下部凸塊金屬化墊形成、晶圓凸塊化、單一化等後續過程中繼續支撐總成。因此，本發明之過程可減少或消除對使用臨時接合支撐載體的依賴，該等臨時接合支撐載體在如上所述之已知過程中對薄晶圓處理及設備加工而言為重要的。
根據本發明之一態樣，提供一種形成一堆疊晶粒封裝之方法，該方法包含：使一或多個半導體晶片附著於一晶圓之前側面；將該等半導體晶片用成型材料覆模成型；及使該晶圓之背側面薄化；其中該覆模成型在該薄化之前執行。
該方法可使得：成型材料在薄化期間給晶圓提供支撐；薄化期間晶圓不耦接至一可自晶圓去耦接之支撐載體；或成型材料包含環氧樹脂或聚合物基囊封材料。
根據本發明之另一態樣，提供一種根據上述方法形成之堆疊晶粒封裝。
根據本發明之另一態樣，提供一種形成一堆疊晶粒封裝之方法，該方法包含：使一或多個半導體晶片附著於一晶圓之前側面；將該等半導體晶片用成型材料覆模成型；及單一化該晶圓為一或多個單一化單元，每一單元包含該等半導體晶片中之至少一者；其中該覆模成型係在單一化該晶圓之前執行。
該方法可使得：成型材料在單一化期間給晶圓提供支撐；單一化期間晶圓不耦接至一可自晶圓去耦接之支撐載體；或成型材料包含環氧樹脂或聚合物基囊封材料。
根據本發明之另一態樣，提供一種根據上述方法形成之堆疊晶粒封裝。
根據本發明之另一態樣，提供一種形成一堆疊晶粒封裝之方法，該方法包含：研磨一晶圓之背表面以曝露貫通矽互連件；其中將該晶圓之前側面用成型材料覆模成型，該成型材料囊封一或多個半導體晶片且在研磨期間給晶圓提供支撐。
根據本發明之另一態樣，提供一種形成一堆疊晶粒封裝之方法，其包含：蝕刻一晶圓以在該晶圓中產生一或多個通道，該等通道自晶圓之前表面朝向晶圓之背表面延伸，該等通道在晶圓內終止；用一介電層鍍覆晶圓；用一障壁金屬層鍍覆該介電層；用一晶種層鍍覆該障壁金屬層；用金屬材料填充該等通道；拋光晶圓之前側面；在晶圓之前表面上執行金屬化及鈍化；將一或多個半導體晶片耦接至晶圓之前表面以使半導體晶片之導電部分與通道對準；用下部填充材料下部填充半導體晶片與晶圓之前表面之間的間隙；用成型材料覆蓋半導體晶片及晶圓之前表面；研磨晶圓之背表面以自晶圓之背表面曝露通道；在晶圓之背表面上執行金屬化及鈍化；在晶圓之背表面之金屬化部分上形成下部凸塊金屬化墊；將導電凸塊耦接至下部凸塊金屬化墊；將晶圓單一化為單一化單元，每一單一化單元包含至少一個半導體晶片及晶圓之一部分；晶片至基板附著，將單一化單元耦接至一基板之前表面；用下部填充材料執行單一化單元與該基板之前表面之間的至少一個間隙的下部填充，及將單一化單元及基板之前表面用成型材料覆模成型；將電連接件安裝於基板之背表面；將該基板單一化為半導體封裝，每一半導體封裝包含至少一個單一化單元及基板之一部分。
該方法可進一步包含在該半導體晶片與該晶圓之間堆疊一或多個中間晶圓。
根據本發明之另一態樣，提供一種半導體封裝，其包含：一基板；一第一晶粒，其具有一前側面，一背側面及複數個貫通矽互連件，該第一晶粒堆疊於該基板上；及一第二晶粒，其具有一前側面，一背側面及形成於該第二晶粒之背側面之第一複數個導電凸塊，該第二晶粒堆疊於該第一晶粒上且經下部填充以使得該第一複數個導電凸塊與該等貫通矽互連件連通；其中一第一成型材料囊封該第二晶粒及該第一晶粒之前側面；且一第二成型材料囊封該第一晶粒、該第二晶粒及複數個外部電連接件。
在該半導體封裝中，貫通矽互連件之每一者可進一步包含：一位於該第一晶粒之背側面之末端部分及一位於該第一晶粒之前側面之頂部部分；一沿該貫通矽互連件之內壁形成之介電層；一形成於該介電層上方之障壁金屬層；一形成於該障壁金屬層上方之晶種層；及一填充該貫通矽互連件之內壁內之空隙之金屬材料。
該半導體封裝可進一步包含：形成於該第一晶粒之前側面上以致不重疊的一金屬層及一鈍化層；形成於該第一晶粒之背側面上以致不重疊的一金屬層及一鈍化層；形成於該第一晶粒之背側面上之金屬層上之複數個UBM墊；及形成於該等UBM墊上之第二複數個導電凸塊。
本發明之上述及其他特徵藉由參考隨附圖式詳細描述其例示性實施例將變得更顯而易見。
現在，將參考展示本發明之例示性實施例之附隨圖式更全面地描述本發明。
具有兩個晶粒之堆疊封裝
參考圖2(a)至2(o)之過程流程圖描述一種製造半導體裝置之過程。
該過程包含步驟1至15，以下段落將詳細描述該等步驟。
"晶圓蝕刻"步驟1，圖2(a)：蝕刻晶圓100以在晶圓100中產生一或多個通道110。晶圓可為其中未嵌埋作用電路之非作用矽晶圓，或其中嵌埋作用電路之作用矽晶圓。當晶圓為作用晶圓時，其將在所得堆疊晶粒封裝中產生功能晶粒。當晶圓為非作用晶圓時，其將充當將堆疊在上方之晶片之較細間距連接件分布於下方基板之較大間距連接件之仲介層。蝕刻可藉由在晶圓100之前側面100a上圖案化一遮罩(未圖示)來達成。遮罩曝露晶圓100之前側面100a之將形成通道110的區域且覆蓋其餘區域。接著執行例如深反應離子蝕刻(deep reactive-ion etching，DRIE)之蝕刻以在晶圓100中形成通道110。蝕刻完成後，移除遮罩。其他蝕刻技術包括(但不限於)雷射鑽孔。通道110自晶圓100之前表面100a朝向後表面100b延伸以使其末端部分110a部分駐留於晶圓100中。
"介電質、障壁及晶種沈積"步驟2，圖2(b)：用一介電層鍍覆步驟1之蝕刻晶圓100，接著在該介電層上鍍覆一障壁金屬層，且接著在該障壁金屬層上鍍覆一晶種層。介電層通常為二氧化矽。障壁金屬層可為鈦、氮化鈦或氮化矽鉭(tantalum silicon nitride)。晶種層可為銅或任何其他金屬。為便於說明，介電層、障壁金屬層及晶種層在圖式中一起以數字120表示。
"通道填充"步驟3，圖2(c)：進一步用金屬材料130鍍覆步驟2之晶圓100以用金屬材料130填充通道110，且因此形成貫通矽互連件140。因此，通道110之末端部分110a現在將稱為貫通矽互連件140之末端部分140a。金屬材料可(例如)為銅、鎢或多晶矽。
"前側面拋光"步驟4，圖2(d)：步驟3之晶圓100可經歷諸如化學機械拋光之拋光過程以移除晶圓100之形成通道110之前側面100a上的任何殘餘金屬材料130(例如，銅)。
"前側面金屬化/鈍化"步驟5，圖2(e)：在步驟4之晶圓100上執行前側面金屬化及鈍化。如本文中所使用，"前側面"係指晶圓100之形成通道110之表面且"背側面"係指晶圓100之相對表面。金屬化過程涉及在晶圓100之頂面或前側面100a及貫通矽互連件140上圖案化金屬跡線及接合墊(未圖示)。用於圖案化金屬跡線及接合墊之金屬層可為銅、鋁或其他金屬。鈍化過程用諸如氮化矽、二氧化矽、聚醯亞胺、苯并環丁烯(BCB)或光敏環氧樹脂(商品名稱："WPR-1020"、"WPR-1050"或"WPR-1201"，JSR Micro,Inc.之產品)之鈍化層塗佈晶圓前側面上未被金屬化層覆蓋之區域。為便於說明，前側面金屬化層及鈍化層在圖式中一起以數字150表示。
"晶片至晶圓附著"步驟6，圖2(f)：將一或多個半導體晶片160(每一個皆經提供有諸如焊料凸塊之導電凸塊170之圖案)定位於晶圓100之前表面100a上方以使半導體晶片160之導電凸塊170與晶圓100之貫通矽互連件140對準且接觸。該一或多個半導體晶片160可藉由切割凸塊化晶圓(未圖示)獲得。接著使半導體晶片160之導電凸塊170回焊以使得晶片160附著於晶圓100。
"下部填充"步驟7，圖2(g)：用諸如環氧樹脂或其他材料(諸如聚合物基囊封材料)之下部填充材料180下部填充晶片160、導電凸塊170及晶圓100之前側面100a之間的間隙。
"晶圓級成型"步驟8，圖2(h)：用諸如環氧樹脂或聚合物基囊封材料之成型材料190覆蓋晶圓100及晶片160。
"晶圓薄化"步驟9，圖2(i)：研磨及拋光步驟(8)之成型晶圓100之背側面100b以曝露貫通矽互連件140之末端部分140a。
"背側面金屬化/鈍化"步驟10，圖2(j)：在步驟9之薄化晶圓100上執行背側面金屬化及鈍化。金屬化過程在晶圓之背側面100b及貫通矽互連件140之末端部分140a上方圖案化金屬跡線及接合墊。用於圖案化金屬跡線之金屬層可為銅、鋁或其他金屬。鈍化過程用諸如氮化矽、二氧化矽、聚醯亞胺、苯并環丁烯(BCB)或光敏環氧樹脂(商品名稱："WPR-1020"、"WPR-1050"或"WPR-1201"，JSR Micro,Inc.之產品)之鈍化層塗佈晶圓背側面上未被金屬化層覆蓋之區域。為便於說明，背側面金屬化層及鈍化層在圖式中一起以數字200表示。
"下部凸塊金屬化"步驟11，圖2(k)：在步驟10之晶圓100之金屬化部分的選定區域形成下部凸塊金屬化(UBM)墊210。選定區域可為後續步驟12中安裝導電凸塊之位置。UBM墊210可由Al/Ni/Au、Al/Ni-V/Cu、Cu/Ni/Au、Cu/Ni/Pd、Cu/Cr/Al、Ti-W/Cu/Ni(EP)/Cu(EP)、Cr/Cu/Cu(EP)/Ni(EP)、Ti/Ni(EP)或Ti/Ai/Ti/NiV製成。
"晶圓凸塊化"步驟12，圖2(1)：晶圓100之背側面100b上之UBM墊210經提供有諸如焊料互連件之導電凸塊220。其他非焊料互連件包括(但不限於)銅柱、金釘等。
"單一化"步驟13，圖2(m)：將步驟12之凸塊化晶圓及晶片結構單一化為個別單元230，每一單元包含一個晶片及一個單一化晶圓。或者，單一化可使得個別單元包含一個以上晶片及單一化晶圓。
"晶片至基板附著及下部填充或覆模成型"步驟14，圖2(n)(i)及圖2(n)(ii)：藉由使晶圓100之背側面100b上之焊料互連件220回焊使單一化單元230附著於基板240。用諸如環氧樹脂或聚合物基囊封材料之成型材料250下部填充[圖2(n)(ii)]安裝單元230或將安裝單元230覆模成型[圖2(n)(i)]。基板240可為有機/層壓基板。
"焊料球安裝及單一化"步驟15，圖2(o)(i)及圖2(o)(ii)：基板240之下側面經提供有諸如焊料球之外部電連接件260。接著將整個總成單一化形成個別半導體封裝，該等個別半導體封裝展示於圖3(a)或3(b)中。
圖3(a)展示由步驟1至15產生之半導體封裝300。半導體封裝300包含附著於基板240之步驟13之單一化單元230。該單元230在步驟14中係用成型材料250覆模成型。
圖3(b)展示由步驟1至15產生之替代半導體封裝400。替代半導體封裝400包含附著於基板240之步驟13之單一化單元230。該單元230在步驟14中係用成型材料250下部填充。
不同於由如圖1(c)中所示之已知過程產生之封裝結構，由本發明實施例之過程產生之如圖3(a)及3(b)中所示的封裝300、400具有於封裝300、400內之成型封裝(單一化單元230)。其為"晶圓級成型"步驟8[圖2(h)]的結果，其在後續步驟9至13(例如"晶圓薄化"步驟9及"單一化"步驟13)期間有利保護且支撐晶圓100及其上堆疊之倒裝晶片160。又，在步驟9之前，未薄化晶圓提供用於貫通矽互連件形成、晶片附著於晶圓及成型之支撐結構(亦即，步驟1至8)。
具有三個或三個以上晶粒之堆疊封裝
雖然上述第一實施例之描述描述製造兩個堆疊晶粒之封裝之過程，但應瞭解，該過程可延伸至三個、四個或四個以上堆疊晶粒之封裝。
對於三個或三個以上晶粒之堆疊封裝，可將具有貫通矽互連件之中間晶粒插入於頂部倒裝晶片與底部晶圓之間。下文參考圖4(a)至4(j)描述形成具有貫通矽互連件之中間晶粒之例示性過程。
"晶圓蝕刻"步驟1，圖4(a)：蝕刻晶圓300以在晶圓300中產生一或多個通道310。蝕刻可藉由在晶圓300之前側面300a上圖案化一遮罩(未圖示)來達成。遮罩曝露晶圓300之前側面300a之將形成通道310的區域且覆蓋其餘區域。接著執行例如深反應離子蝕刻(DRIE)之蝕刻以在晶圓300中形成通道310。蝕刻完成後，移除遮罩。其他蝕刻技術包括(但不限於)雷射鑽孔。通道310自晶圓300之前表面300a朝向後表面300b延伸以使其末端部分310a部分駐留於晶圓300中。
"介電質、障壁及晶種沈積"步驟2，圖4(b)：用一介電層鍍覆步驟1之蝕刻晶圓300，接著在該介電層上鍍覆一障壁金屬層，且接著在該障壁金屬層上鍍覆一晶種層。介電層通常為二氧化矽。障壁金屬層可為鈦、氮化鈦或氮化矽鉭。晶種層可為銅或任何其他金屬。為便於說明，介電層、障壁金屬層及晶種層在圖式中一起以數字320表示。
"通道填充"步驟3，圖4(c)：進一步用金屬材料330鍍覆步驟2之晶圓300以用金屬材料330填充通道310，且因此形成貫通矽互連件340。因此，通道310之末端部分310a現在將稱為貫通矽互連件之末端部分340a。金屬材料可(例如)為銅、鎢或多晶矽。
"前側面拋光"步驟4，圖4(d)：步驟3之晶圓300可經歷諸如化學機械拋光之拋光過程以移除形成通道310之晶圓300之前側面300a上的任何殘餘金屬材料330(例如，銅)。
"前側面金屬化/鈍化"步驟5，圖4(e)：在步驟4之晶圓300上執行前側面金屬化及鈍化。如本文中所使用，"前側面"係指晶圓300之形成通道310之表面且"背側面"係指晶圓300之相對表面。金屬化過程涉及在晶圓300之前側面300a及貫通矽互連件340之頂部圖案化金屬跡線及接合墊(未圖示)。用於圖案化金屬跡線及接合墊之金屬層可為銅、鋁或其他金屬。鈍化過程用諸如氮化矽、二氧化矽、聚醯亞胺、苯并環丁烯(BCB)或光敏環氧樹脂(商品名稱："WPR-1020"、"WPR-1050"或"WPR-1201"，JSR Micro,Inc.之產品)之鈍化層塗佈晶圓前側面上未被金屬化層覆蓋之區域。為便於說明，前側面金屬化層及鈍化層在圖式中一起以數字350表示。
"晶圓薄化"步驟6，圖4(f)：研磨及拋光步驟(6)之晶圓300之背側面300b以曝露貫通矽互連件340之末端部分340a。
"背側面金屬化/鈍化"步驟7，圖4(g)：在步驟6之薄化晶圓300上執行背側面金屬化及鈍化。金屬化過程在晶圓之背側面300b及貫通矽互連件340之末端部分340a上方圖案化金屬跡線及接合墊。用於圖案化金屬跡線之金屬層可為銅、鋁或其他金屬。鈍化過程用諸如氮化矽、二氧化矽、聚醯亞胺、苯并環丁烯(BCB)或光敏環氧樹脂(商品名稱："WPR-1020"、"WPR-1050"或"WPR-1201"，JSR Micro,Inc.之產品)之鈍化層塗佈晶圓背側面上未被金屬化層覆蓋之區域。為便於說明，背側面金屬化層及鈍化層在圖式中以數字400表示。
"下部凸塊金屬化"步驟8，圖4(h)：在步驟7之晶圓300之金屬化部分的選定區域形成下部凸塊金屬化(UBM)墊410。選定區域可形成後續晶圓凸塊化步驟9中導電凸塊之位置。UBM墊410可由Al/Ni/Au、Al/Ni-V/Cu、Cu/Ni/Au、Cu/Ni/Pd、Cu/Cr/Al、Ti-W/Cu/Ni(EP)/Cu(EP)、Cr/Cu/Cu(EP)/Ni(EP)、Ti/Ni(EP)或Ti/Ai/Ti/NiV製成。
"晶圓凸塊化"步驟9，圖4(i)：晶圓300之背側面300b上之UBM墊410經提供有諸如焊料互連件之導電凸塊420。其他非焊料互連件包括(但不限於)銅柱、金釘等。
"單一化"步驟10，圖4(j)：將步驟9之凸塊化晶圓及晶片結構單一化為個別單元或晶粒430。
可能必需使用附著於前表面300a之臨時接合支撐載體以在步驟6至9期間在結構上支撐薄化中間晶圓。
為形成具有三個或三個以上堆疊晶粒之半導體封裝，執行如圖2(a)至2(e)中所示之相同過程步驟1至5。圖5(a)至5(j)分別展示下文將描述之後續步驟6至15。
"晶片至晶圓附著"步驟6，圖5(a)：可將所得中間晶粒430堆疊於第一晶圓300上以使導電凸塊420與第一晶圓300之貫通矽互連件340對準。第一晶圓300可為作用晶圓或非作用晶圓。必要時，可以相同方式將其他中間晶粒堆疊於中間晶粒430頂部。為便於說明及描述，描述及圖式將展示形成三個晶粒堆疊之封裝之步驟。半導體晶片360(每一者具有諸如焊料凸塊之導電凸塊370之圖案)定位於中間晶粒430上方以使半導體晶片360之導電凸塊370與中間晶粒430之貫通矽互連件340對準且接觸。半導體晶片360可藉由切割凸塊化晶圓(未圖示)獲得。接著使半導體晶片360之導電凸塊370回焊以使得晶片360附著於中間晶粒430。
"下部填充"步驟7，圖5(b)：可用諸如環氧樹脂或其他材料(諸如聚合物基囊封材料)之下部填充材料380下部填充晶片360與中間晶粒430之間及中間晶粒430與第一晶圓之間的間隙。
"晶圓級成型"步驟8，圖5(c)：用諸如環氧樹脂或聚合物基囊封材料之成型材料390覆蓋第一晶圓300、中間晶粒430及晶片360。
"晶圓薄化"步驟9，圖5(d)：研磨及拋光步驟8之成型晶圓300之背側面300b以曝露貫通矽互連件340之末端部分340a。
"背側面金屬化/鈍化"步驟10，圖5(e)：在步驟9之薄化晶圓300上執行背側面金屬化及鈍化。金屬化過程在晶圓之背側面300b及貫通矽互連件340之末端部分340a上方圖案化金屬跡線及接合墊。用於圖案化金屬跡線之金屬層可為銅、鋁或其他金屬。鈍化過程用諸如氮化矽、二氧化矽、聚醯亞胺、苯并環丁烯(BCB)或光敏環氧樹脂(商品名稱："WPR-1020"、"WPR-1050"或"WPR-1201"，JSR Micro,Inc.之產品)之鈍化層塗佈晶圓背側面上未被金屬化層覆蓋之區域。為便於說明，背側面金屬化層及鈍化層在圖式中一起以數字400表示。
"下部凸塊金屬化"步驟11，圖5(f)：在步驟10之晶圓300之金屬化部分上形成下部凸塊金屬化(UBM)墊410。UBM墊410可由Al/Ni/Au、Al/Ni-V/Cu、Cu/Ni/Au、Cu/Ni/Pd、Cu/Cr/Al、Ti-W/Cu/Ni(EP)/Cu(EP)、Cr/Cu/Cu(EP)/Ni(EP)、Ti/Ni(EP)或Ti/Ai/Ti/NiV製成。
"晶圓凸塊化"步驟12，圖5(g)：晶圓300之背側面300b上之UBM墊410經提供有諸如焊料互連件之導電凸塊420。其他非焊料互連件包括(但不限於)銅柱、金釘等。
"單一化"步驟13，圖5(h)：將步驟12之凸塊化晶圓及晶片結構單一化為個別單元440。
"晶片至基板附著及下部填充或覆模成型"步驟14，圖5(i)：藉由使晶圓300之背側面300b上之焊料互連件420回焊使單一化單元440附著於基板450。將安裝單元440用諸如環氧樹脂或聚合物基囊封材料之成型材料覆模成型。基板450可為有機/層壓基板。雖然圖式中未圖示，但應瞭解，諸如在圖2(n)(ii)之情況下，亦可用成型材料下部填充安裝單元440。
"焊料球安裝及單一化"步驟15，圖5(j)：基板450之下側面經提供有諸如焊料球之外部電連接件460。接著將整個總成單一化形成個別半導體封裝，該等個別半導體封裝展示於圖6中。
應瞭解，可將中間晶粒以晶圓格式堆疊於第一晶圓上，且不需要單一化為個別晶粒來堆疊於第一晶圓上。
半導體封裝
提供一種包含一或多個以垂直方式堆疊於基板上之晶粒之半導體封裝。圖3(a)及3(b)展示半導體封裝之例示性結構。雖然圖3(a)及3(b)先前已描述為源自"具有兩個晶粒之堆疊封裝"實施例之過程，但應瞭解，本發明亦將涵蓋具有源自除所述過程以外之過程之類似結構的封裝。
參考圖3(a)，半導體封裝包含一第一晶粒100及一第二晶粒160。第一晶粒100具有一前側面100a及一背側面100b。第一晶粒100可為具有嵌埋電路之作用晶粒及無任何嵌埋電路之非作用晶粒。第一晶粒100進一步包括複數個貫通矽互連件140，每一貫通矽互連件140具有第一晶粒100之背側面100b上之末端部分140a及第一晶粒100之前側面100a上之頂部部分140b。貫通矽互連件140各自具有一沿其內壁形成之介電層，接著一形成於該介電層上方之障壁金屬層及接著一形成於該障壁金屬層上方之晶種層。介電層通常為二氧化矽。障壁金屬層可為Ti、TiN或氮化矽鉭。晶種層可為銅或任何其他金屬。為便於說明，介電層、障壁金屬層及晶種層在圖式中一起以數字120表示。金屬材料130填充內壁內之空隙以形成貫通矽互連件140。金屬材料可(例如)為銅、鎢或多晶矽。
第一晶粒100之前側面100a具有一圖案化於其上以產生導電跡線及接合墊之之金屬化層。金屬層可為銅、鋁或其他金屬。在前側面100a上未被金屬化層佔據之區域上形成一鈍化層。該鈍化層可為氮化矽、二氧化矽、聚醯亞胺、苯并環丁烯(BCB)或光敏環氧樹脂(商品名稱："WPR-1020"、"WPR-1050"或"WPR-1201"，JSR Micro,Inc.之產品)。為便於說明，前側面金屬化層及鈍化層在圖式中一起以數字150表示。
第一晶粒100之背側面100b亦具有一圖案化其上以產生導電跡線及接合墊之金屬化層及一佔據未沈積金屬化層之其餘區域之鈍化層。為便於說明，背側面金屬化層及鈍化層在圖式中一起以數字200表示。背側面100b進一步包括形成於金屬化部分之選定區域上之複數個UBM墊210。在UBM墊210上形成諸如焊料互連件之導電凸塊220。其他非焊料互連件包括(但不限於)銅柱、金釘等。UBM墊210可為Al/Ni/Au、Al/Ni-V/Cu、Cu/Ni/Au、Cu/Ni/Pd、Cu/Cr/Al、Ti-W/Cu/Ni(EP)/Cu(EP)、Cr/Cu/Cu(EP)/Ni(EP)、Ti/Ni(EP)或Ti/Ai/Ti/NiV。
第二晶粒160包括一前側面160a及一背側面160b，且進一步包括形成於背側面160b上之複數個導電凸塊170。以一使導電凸塊170與貫通矽互連件140對準且接觸之方式將第二晶粒160堆疊於第一晶粒100上。下部填充材料180填充第二晶粒160、導電凸塊170及第一晶粒100之間的空隙。下部填充材料180可為環氧樹脂或諸如聚合物基囊封材料之其他材料。成型材料190亦覆蓋或囊封第二晶粒160及第一晶粒100之前側面100a。成型材料可為環氧樹脂或聚合物基囊封材料。
堆疊於第一晶粒上之成型第二晶粒形成內部封裝500。內部封裝500安裝於基板240上。基板240可為層壓基板或有機基板。
半導體封裝進一步包括一完全囊封基板240上之內部封裝500之成型材料250及形成於其下側面上之諸如焊料球之複數個外部電連接件260。
或者，參考圖3(b)，成型材料250可僅下部填充內部封裝500與基板240之間的空隙。
應瞭解，本發明之半導體封裝亦將延伸至(例如)如圖6中所示之三個或三個以上晶粒堆疊之封裝。形成於第一晶粒300與第二晶粒360之間的中間晶粒亦將具有形成於其中之貫通矽互連件340。因此，對於三個晶粒堆疊之封裝，將存在一個位於第一晶粒300與第二晶粒360之間的中間晶粒430，且該中間晶粒以使其貫通矽互連件340及導電凸塊420與第一晶粒300之貫通矽互連件340及第二晶粒360之導電凸塊370對準之方式堆疊。
一或多個上述例示性實施例提供一或多個以下優點：如由上述描述將清楚地瞭解，兩個晶粒堆疊之封裝裝配過程中之晶圓或三個或三個以上晶粒堆疊之封裝裝配過程中之至少第一晶圓不需要臨時接合支撐載體。
至少對兩個晶粒堆疊之封裝裝配過程而言，若不需要支撐載體，則不需要實施使臨時支撐載體接合至晶圓所需之新過程及材料(例如，黏著劑)的開發。
因此，至少對兩個晶粒堆疊之封裝裝配過程而言，資金投資不需要投放用於支援臨時接合支撐載體技術之新設備。
因對兩個晶粒堆疊之封裝而言可完全省去支撐載體及對三個或三個以上晶粒堆疊之封裝而言部分省去支撐載體的潛在封裝費用優點。
因為過程步驟不需要使載體基板至晶圓或第一晶圓額外接合及由此產生之後續去接合，所以可改良面對背倒裝晶片晶粒堆疊裝配流程循環時間。
因為晶圓或第一晶圓中之貫通矽互連件之製造在不研磨狀態下執行及完成，所以過程允許晶圓具有用較高凸塊I/O以較小間距焊料凸塊化或用預形成球熔滴過程以較大焊料球間距及球尺寸焊料凸塊化的靈活性。
因為晶圓及其上堆疊之倒裝晶片在晶圓薄化步驟9及單一化步驟13之前成型[步驟8，參見圖2(h)]，所以成型有助於在薄化及單一化期間支撐晶圓。
雖然已參考本發明之例示性實施例特別展示及描述本發明，但一般熟習此項技術者應瞭解，在不背離以下申請專利範圍所界定之本發明之精神及範疇的情況下，可進行形式及細節之各種改變。
1．．．晶圓
1a．．．晶圓之前表面
1b．．．晶圓之後表面
2．．．通道
3．．．節點層、障壁金屬層及晶種層
4．．．金屬材料
5．．．貫通矽互連件
5a．．．貫通矽互連件之後端部分
6．．．金屬化及鈍化層
7．．．第一支撐載體
7a．．．接合材料
8．．．金屬化及鈍化層
9．．．下部凸塊金屬化墊
10．．．焊料凸塊
11．．．倒裝晶片
12．．．第二支撐載體
12a．．．接合材料
13．．．焊料凸塊
14．．．樹脂
15．．．焊料凸塊
16．．．個別單元
17．．．基板
18．．．成型材料
19．．．焊料球
100．．．晶圓/薄化晶圓/第一晶粒
100a．．．晶圓之頂面/第一晶粒之前側面/晶圓之前側面/晶圓之前表面
100b．．．第一晶粒之背側面/晶圓之後表面/晶圓之背側面
110．．．通道
110a．．．通道之末端部分
120．．．介電層、障壁金屬層及晶種層
130．．．金屬材料
140．．．貫通矽互連件
140a．．．貫通矽互連件之末端部分
140b．．．貫通矽互連件之頂部部分
150．．．前側面金屬化層及鈍化層
160．．．半導體晶片/第二晶粒
160a．．．第二晶粒之前側面
160b．．．第二晶粒之背側面
170．．．導電凸塊
180．．．下部填充材料
190．．．成型材料
200．．．背側面金屬化層及鈍化層
210．．．下部凸塊金屬化墊
220．．．導電凸塊
230．．．個別單元/安裝單元/單一化單元
240．．．基板
250．．．成型材料
260．．．外部電連接件
300．．．半導體封裝/晶圓/薄化晶圓/第一晶粒/第一晶圓
300a．．．晶圓之前側面
300b．．．晶圓之背側面/晶圓之後表面
310．．．通道
320．．．介電層、障壁金屬層及晶種層
330．．．金屬材料
340．．．貫通矽互連件
340a．．．貫通矽互連件之末端部分
350．．．前側面金屬化層及鈍化層
360．．．半導體晶片/第二晶粒
370．．．導電凸塊
380．．．下部填充材料
390．．．成型材料
400．．．替代半導體封裝/背側面金屬化層及鈍化層
410．．．下部凸塊金屬化墊
420．．．導電凸塊
430．．．個別單元/晶粒/中間晶粒
440．．．個別單元
450．．．基板/安裝單元
460．．．外部電連接件
500．．．內部封裝
圖1(a)說明形成接合至第一支撐載體之薄化晶圓之已知過程。
圖1(b)(i)及1(b)(ii)說明將倒裝晶片堆疊於圖1(a)之具有UBM墊之薄化晶圓上的已知過程。
圖1(c)(i)及圖1(c)(ii)說明將倒裝晶片堆疊於圖1(a)之具有UBM墊及焊料凸塊之薄化晶圓上的替代已知過程。
圖1(d)說明由圖1(a)及圖1(b)或圖1(a)及圖1(c)描述之過程產生之已知半導體封裝。
圖2(a)-2(o)(ii)展示根據本發明之一例示性實施例之製造半導體裝置的過程流程圖。
圖3(a)展示根據本發明之一例示性實施例之半導體裝置。
圖3(b)展示根據本發明之一替代性例示性實施例之半導體裝置。
圖4(a)-4(j)展示製造中間晶粒之過程流程圖。
圖5(a)-5(j)展示根據本發明之另一例示性實施例之製造半導體裝置的過程流程圖。
圖6展示根據本發明之另一例示性實施例之半導體裝置。
100．．．晶圓/薄化晶圓/第一晶粒
100a．．．第一晶粒之前側面/晶圓之前側面/晶圓之前表面/晶圓之頂面
100b．．．第一晶粒之背側面/晶圓之後表面/晶圓之背側面
120．．．介電層、障壁金屬層及晶種層
130．．．金屬材料
140．．．貫通矽互連件
140a．．．貫通矽互連件之末端部分
140b．．．貫通矽互連件之頂部部分
150．．．前側面金屬化層及鈍化層
160．．．半導體晶片/第二晶粒
160a．．．第二晶粒之前側面
160b．．．第二晶粒之背側面
170．．．導電凸塊
180．．．下部填充材料
190．．．成型材料
200．．．背側面金屬化層及鈍化層
210．．．下部凸塊金屬化墊
240．．．基板
250．．．成型材料
260．．．外部電連接件
300．．．半導體封裝/晶圓/薄化晶圓/第一晶粒/第一晶圓
500．．．內部封裝

Claims (24)

  1. 一種形成一堆疊晶粒封裝之方法，該方法包含：使一或多個半導體晶片附著於一半導體晶圓之一前側面；將該半導體晶片用一成型材料覆模成型；及使該半導體晶圓之背側面薄化而不曝露該成型材料，其中該覆模成型係在該薄化之前執行。
  2. 如請求項1之方法，其中該成型材料在該薄化期間提供對該半導體晶圓之支撐。
  3. 如請求項1之方法，其中該薄化期間，該半導體晶圓不耦接至一可自該半導體晶圓去耦接之支撐載體。
  4. 如請求項1之方法，其中該成型材料包含一環氧樹脂或一聚合物基囊封材料。
  5. 一種堆疊晶粒封裝，其係根據請求項1之方法而形成。
  6. 一種形成一堆疊晶粒封裝之方法，該方法包含：使一或多個半導體晶片附著於一晶圓之一前側面；將該半導體晶片用一成型材料覆模成型；使該半導體晶圓之背側面薄化而不曝露該成型材料；及將該半導體晶圓單一化為一或多個單一化單元，每一單元包含該等半導體晶片中之至少一者，其中該覆模成型係在該單一化該半導體晶圓之前執行。
  7. 如請求項6之方法，其中該成型材料在該單一化期間提供對該半導體晶圓之支撐。
  8. 如請求項6之方法，其中該單一化期間，該半導體晶圓 不耦接至一可自該半導體晶圓去耦接之支撐載體。
  9. 如請求項6之方法，其中該成型材料包含一環氧樹脂或一聚合物基囊封材料。
  10. 一種堆疊晶粒封裝，其係根據請求項6之方法而形成。
  11. 一種形成一堆疊晶粒封裝之方法，該方法包含：研磨一半導體晶圓之一背表面以曝露貫通矽互連件；其中該半導體晶圓之一前側面係經一成型材料覆模成型，該成型材料囊封一或多個半導體晶片且在該研磨期間不曝露該成型材料而提供對該晶圓之支撐。
  12. 如請求項11之方法，其包含：對該半導體晶圓之該背表面執行金屬化及鈍化；在該半導體晶圓之該背表面之金屬化部分上形成下部凸塊金屬化墊；將導電凸塊耦接至該等下部凸塊金屬化墊；及將該半導體晶圓單一化為單一化單元，每一單一化單元包含至少一個半導體晶片及該半導體晶圓之一部分。
  13. 如請求項12之方法，其包含：將該等經單一化之單元附著至一基板；及以一成型材料將該等經單一化之單元覆膜成型。
  14. 如請求項12之方法，其包含：將該等經單一化之單元附著至一基板；及以一下部填充材料填充在該等經單一化之單元與該基板之一前表面之間之間隙。
  15. 如請求項11之方法，其包含： 在該等半導體晶片與該半導體晶圓之該前側面之間堆疊一或多個中間晶粒。
  16. 如請求項15之方法，其包含：對該半導體晶圓之該背表面執行金屬化及鈍化；在該半導體晶圓之該背表面之金屬化部分上形成下部凸塊金屬化墊；將導電凸塊耦接至該等下部凸塊金屬化墊；及將該半導體晶圓單一化為單一化單元，每一單一化單元包含至少一個半導體晶片、至少一中間晶粒及該半導體晶圓之一部份。
  17. 如請求項16之方法，其包含：將該等經單一化之單元附著至一基板；及以一成型材料將該等經單一化之單元覆膜成型。
  18. 如請求項16之方法，其包含：將該等經單一化之單元附著至一基板；及以一下部填充材料填充在該等經單一化之單元與該基板之一前表面之間之間隙。
  19. 一種形成一堆疊晶粒封裝之方法，該方法包含：蝕刻一晶圓以在該晶圓中產生一或多個通道，該等通道自該晶圓之一前表面朝向該晶圓之一背表面延伸，該等通道在該晶圓內終止；用一介電層鍍覆該晶圓；用一障壁金屬層鍍覆該介電層；用一晶種層鍍覆該障壁金屬層； 用一金屬材料填充該等通道；拋光該晶圓之前側面；對該晶圓之該前表面執行金屬化及鈍化；將一或多個半導體晶片耦接至該晶圓之該前表面以使該等半導體晶片之導電部分與該等通道對準；用一下部填充材料下部填充該等半導體晶片與該晶圓之該前表面之間的間隙；用一成型材料覆蓋該等半導體晶片及該晶圓之該前表面；研磨該晶圓之該背表面以自該晶圓之該背表面曝露該等通道；對該晶圓之該背表面執行金屬化及鈍化；在該晶圓之該背表面之金屬化部分上形成下部凸塊金屬化墊；將導電凸塊耦接至該等下部凸塊金屬化墊；將該晶圓單一化為單一化單元，每一單一化單元包含至少一個半導體晶片及該晶圓之一部分；晶片至基板附著；將該等單一化單元耦接至一基板之一前表面；用一下部填充材料執行該等單一化單元與該基板之該前表面之間的至少一個間隙的下部填充，及將該等單一化單元及該基板之該前表面用一成型材料覆模成型；將電連接件安裝於該基板之該背表面；將該基板單一化為半導體封裝，每一半導體封裝包含 至少一個單一化單元及該基板之一部分。
  20. 如請求項19之方法，其進一步包含在該等半導體晶片與該晶圓之間堆疊一或多個中間晶圓。
  21. 一種半導體封裝，其包含：一基板；一第一晶粒，其具有一前側面、一背側面及複數個貫通矽互連件，該第一晶粒係堆疊於該基板上；及一第二晶粒，其具有一前側面、一背側面及形成於該第二晶粒之該背側面之第一複數個導電凸塊，該第二晶粒係堆疊於該第一晶粒上且經下部填充以使該第一複數個導電凸塊與該等貫通矽互連件電氣地連通，其中一第一成型材料囊封該第二晶粒及該第一晶粒之該前側面；及一第二成型材料囊封該第一晶粒、該第二晶粒及複數個外部電連接件。
  22. 如請求項21之半導體封裝，其中該等貫通矽互連件中之每一個進一步包含：一在該第一晶粒之該背側面之末端部分及一在該第一晶粒之該前側面之頂部部分；一沿該貫通矽互連件之內壁形成之介電層；一形成於該介電層上方之障壁金屬層；一形成於該障壁金屬層上方之晶種層；及一填充該貫通矽互連件之該等內壁內之空隙的金屬材料。
  23. 如請求項22之半導體封裝，其進一步包含： 形成於該第一晶粒之該前側面以致不重疊的一金屬層及一鈍化層；形成於該第一晶粒之該背側面以致不重疊的一金屬層及一鈍化層；形成於該第一晶粒之該背側面上之該金屬層上的複數個UBM墊；及形成於該等UBM墊上之第二複數個導電凸塊。
  24. 如請求項21之半導體封裝，其進一步包含：一在該第一晶粒及該第二晶粒之間之間隙，其中該間隙係藉由一下部填充材料所填充，使得該第一複數個導電凸塊被該下部填充材料所包圍。
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