TWI434357B - 製造一種凹入式通道存取電晶體元件之方法 - Google Patents

製造一種凹入式通道存取電晶體元件之方法 Download PDF

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TWI434357B
TWI434357B TW100146819A TW100146819A TWI434357B TW I434357 B TWI434357 B TW I434357B TW 100146819 A TW100146819 A TW 100146819A TW 100146819 A TW100146819 A TW 100146819A TW I434357 B TWI434357 B TW I434357B
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gate
recessed
channel access
access transistor
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Wei Ming Liao
Ming Cheng Chang
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Nanya Technology Corp
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Description

製造一種凹入式通道存取電晶體元件之方法
本發明大體上關於一種半導體元件及其製造方法。更特定言之，本發明係與一種製作凹入式通道存取電晶體(recessed channel access transistor,RCAT)元件之方法有關，其所製作出來的通道存取電晶體的閘極誘導汲極漏電流(gate induced drain leakage,GIDL)較小。
隨著半導體元件尺寸的減縮，閘通道長度亦隨之縮短，其結果可能會引發短通道效應。習知解決短通道效應的方法包含減少閘氧化層之厚度或增加摻雜子的濃度。然而，這類方法可能會造成元件可靠度的劣化並降低資料傳輸的速度。
近幾年，業界中已發展出凹入式通道存取電晶體元件(或簡稱為RCAT元件)，其可藉由在物理層面上增加閘通道長度而不增加閘極的橫向面積之方式來抑制短通道效應。相較於那些閘極形成在基底平面上的平面閘極式電晶體而言，RCAT電晶體元件具有一形成在側壁上的閘氧化層以及一蝕入基底中的凹槽底面，該凹槽中會填入導電物質。因而可以提高式閘極的整合度。
然而在一般的RCAT元件中，當汲極電壓(Vd)施加在一與NMOS電晶體電性連接的電容上時，其可能會發生閘極誘導汲極漏電(GIDL)的問題。多晶矽閘極的銳角與該多晶矽閘極銳角附近相對較薄的閘氧化層設計會造成DRAM記憶胞側的電場過度集中。此電場集中之現象會導致漏電。閘極誘導汲極漏電對DRAM裝置的更新特性有不好的影響。因此，吾人希望能消除或減緩RCAT元件中閘極誘導汲極漏電的現象，以改善DRAM裝置的更新特性。
據此，本發明的目的之一即在於提供一種製作凹入式通道存取電晶體(RCAT)元件的改良方法，使所製作出來的通道存取電晶體的閘極誘導汲極漏電流(GIDL)較小。
根據本發明一實施例，其提供了一種製造凹入式通道存取電晶體元件之方法。首先，提供一半導體基底，其上具有一凹槽蝕入其主表面中。一閘極介電層隨後形成在該凹槽的內表面。一凹入式閘極之後形成在該凹槽之中與上。該凹入式閘極包含一凹入式閘部嵌入該凹槽中與該主表面下，及一位在該主表面上方的上閘部。該凹入式閘極的一裸露側壁會受到等向性蝕刻，因而形成一寬度小於該凹入式閘部的經修整頸部。該經修整頸部的一裸露側壁之後會被氧化。
無疑地，本發明的這類目的與其他目的在閱者讀過下文以多種圖示與繪圖來描述的較佳實施例細節說明後將變得更為顯見。
在下文的細節描述中，元件符號會標示在隨附的圖示中成為其中的一部份，並且以可實行該實施例之特例描述方式來表示。這類實施例會說明足夠的細節，使得該領域之技藝人士可具以實施。閱者須瞭解到在本發明中亦可利用其他的實施例或是在不悖離所述實施例的前提下做出結構性、邏輯性、及電性上的改變。因此，下文之細節描述將不欲被視為是一種限定，反之，其中所含有的實施例將由隨附的申請專利範圍來加以界定。
對於電晶體與積體電路之製造而言，如在一平面製程的場合中，「主表面」一詞係指那些內部或近處製有複數個電晶體的半導體層的表面。如文中所使用的，「垂直」一詞意指與該主表面實質上呈直角。一般而言，該主表面係沿著所製作出之場效電晶體上的單晶矽層之一<100>平面延伸。
第1～6圖為本發明的截面示意圖，其表示出根據本發明實施例用以製作出具有較小GIDL(閘極誘導汲極漏電流)之凹入式通道存取電晶體(RCAT)元件的方法範例。如第1圖所示，其提供了一半導體基底10(如矽基底)或一含有矽質層的基底。該半導體基底10具有一主表面10a與至少一凹槽12蝕入該半導體基底10的主表面10a中。該凹槽可具有輪廓平順的側壁12a及位在主表面10a附近的上壁角12c。
在凹槽12形成後，閘極介電層14(如氧化矽或高K值氧化物)會形成在包含凹槽12側壁12a及底部12b的內表面上。該閘極介電層14亦會覆蓋在主表面10a上。接著，一導電閘極材料層20會沈積在該凹槽12中並填滿該凹槽12。根據此實施例，該導電閘極材料層20包含一第一層結構16與一第二層結構18。舉例言之，該第一層結構16可包含多晶矽而該第二層結構18則可包含金屬、金屬合金或金屬矽化物等。然而，須瞭解在不悖離本發明精神之前提下，該導電閘極材料層20可為單層結構或多層結構。之後，一圖形化光阻遮罩30會形成在該導電閘極材料層20上。
如第2圖所示，該圖形化光阻遮罩30形成後會進行一非等向性乾蝕刻製程來蝕刻那些未為該圖形化光阻遮罩30所覆蓋的導電閘極材料層20。更特定言之，根據本發明實施例，第二層結構18未為該圖形化光阻遮罩30所覆蓋的部位會完全被蝕去。上述的非等向性乾蝕刻製程會在第一層結構16裸露時停止。發明中亦可選擇性地在該第一層結構16裸露時進行一過蝕刻(over etch)製程。
如第3圖所示，該圖形化光阻遮罩30會被拔除。其後，一介電蓋體34會形成在圖形化的第二層結構18a上。根據此實施例，介電蓋體34可包含氮化矽，然本發明中亦可採用其他材質。在該介電蓋體34形成在圖形化的第二層結構18a上後會進行一非等向性乾蝕刻製程來蝕刻那些未為該介電蓋體34所遮蓋的第一層結構16，因而形成一圖形化第一層結構16a。就此點而言，該圖形化第一層結構16、該圖形化第二層結構18、及該介電蓋體34共同建構出一凹入式閘極40。根據本發明實施例，上述的非等向性乾蝕刻製程會在該閘極介電層14裸露時停止。意即，該第一層結構16未為該介電蓋體34遮蓋的裸露部位會完全被蝕去，然其亦非必要條件。在另一實施例中，如第7圖所示，為可靠度之考量，閘極介電層14上會刻意保留一第一層結構16之薄層116。
凹入式閘極40包含一嵌入凹槽12中與主表面10a下的凹入式閘部40a以及位在該主表面10a上的上閘部40b。就此點而言，該上閘部40b的寬度W1略寬於該凹入式閘部40a的寬度W2，較寬的上閘部40b會產生尖銳的多晶矽壁角，如圖中標以元件符號145的虛圈所示。如先前所提到者，多晶矽閘部的銳角與相對較薄的閘氧化層會造成電場集中在胞側壁角。此電場集中的現象會導致漏電。本發明方法即應運此問題而生。
如第4圖所示，該凹入式閘極40形成後會進行一等向性蝕刻製程(如採用氨水[NH4 OH]或氫氧化四甲銨[Tetra-methylammonium Hydroxide,TMAH]的濕蝕刻製程)來側向蝕刻該凹入式閘極40圖形化第一層結構16a所裸露之側壁部位，因而在該圖形化第一層結構16a中形成一凹槽16b及一寬度W3小於該凹入式閘部40a寬度W2的經修整頸部216。就此點而言，該凹入式閘極40具有蕈狀的截面形。由於該圖形化第一層結構16a是以等向性蝕刻製程來蝕刻，故該經修整頸部216可具有弧形的側壁輪廓。舉例言之，根據此實施例，該凹入式閘極40圖形化第一層結構16a的受蝕部位在每一側約為5-8 nm厚，而寬度W3則可能介於10-35 nm(以20-30 nm為佳)。上述的等向性蝕刻製程除去了多晶矽閘極處的銳角特徵。
接著，如第5圖所示，進行一熱氧化製程來氧化該經修整頸部216的裸露面，因而形成一矽氧化層42。介電蓋體34、該矽氧化層42、及閘極介電層14共同包覆了該圖形化第一層結構16a與第二層結構18a。在該矽氧化層42形成後會進行一離子佈植製程50來將摻質植入半導體基底10的主表面10a中，因而在該凹入式閘極40的兩側形成一源極/汲極摻雜區52。本發明之凹入式閘極40與凹入式通道存取電晶體100元件於焉完成。
如第6圖所示，本發明可選擇性地在上述凹入式閘極40的兩側壁上形成一氮化矽間隙壁60。該氮化矽間隙壁60形成後會進行一清洗製程來除去殘留的閘極介電層14或來自該半導體基底10主表面10a的原生氧化層等氧化物。其後，一磊晶矽層70會在上述源極/汲極摻雜區52上該半導體基底10所裸露的主表面10a上成長(或沈積於其上)。
本領域之技藝人士將可輕易瞭解到在維持本發明教示之前提下，本發明之元件與方法可加以修改或變形成多種態樣。
10．．．基底
10a．．．主表面
12．．．凹槽
12a．．．側壁
12b．．．底部
12c．．．上壁角
14．．．閘極介電層
16．．．第一層結構
16a．．．圖形化第一層結構
16b．．．凹槽
18．．．第二層結構
18a‧‧‧圖形化第二層結構
20‧‧‧閘極材料層
30‧‧‧圖形化光組遮罩
34‧‧‧介電蓋體
40‧‧‧凹入式閘極
40a‧‧‧凹入式閘部
40b‧‧‧上閘部
42‧‧‧矽氧化層
50‧‧‧離子佈植製程
52‧‧‧源極/汲極摻雜區
60‧‧‧間隙壁
70‧‧‧磊晶矽層
100‧‧‧凹入式通道存取電晶體
116‧‧‧薄層
145‧‧‧元件符號
216‧‧‧經修整頸部
本說明書含有附圖併於文中構成了本說明書之一部分，俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在這些圖示中：
第1～6圖為截面示意圖，其表示出根據本發明實施例用以製作具有較低GIDL(閘極誘導汲極漏電流)的凹入式通道存取電晶體元件之方法；及
第7圖描繪了本發明另一實施例。
10‧‧‧基底
12‧‧‧凹槽
14‧‧‧閘極介電層
16a‧‧‧圖形化第一層結構
18‧‧‧第二層結構
40‧‧‧凹入式閘極
42‧‧‧矽氧化層
50‧‧‧離子佈植製程
52‧‧‧源極/汲極摻雜區
100‧‧‧凹入式通道存取電晶體

Claims (7)

  1. 一種製作凹入式通道存取電晶體元件之方法，包含有：提供一半導體基材，其主表面上具有一凹槽；於該凹槽內形成一閘極介電層；於該凹槽內形成一凹入式閘極，其中該凹入式閘極包含一凹入式閘部，嵌入在該凹槽內且位於該主表面下，以及一上閘部，位於該主表面上，其中該上閘部包含一圖案化上層以及覆蓋住該圖形化上層的一側壁與一上表面的一介電蓋體；等向性蝕刻該凹入式閘極的一裸露側壁，俾形成一經修整之頸部，其寬度小於該凹入式閘極的寬度；以及氧化該經修整之頸部的裸露側壁。
  2. 如申請專利範圍第1項所述之一種製作凹入式通道存取電晶體元件之方法，其中氧化該經修整之頸部的裸露側壁後，另包含：進行一離子佈植製程，將摻質植入該半導體基材之該主表面，俾於該凹入式閘極的兩側形成一源極/汲極摻雜區。
  3. 如申請專利範圍第2項所述之一種製作凹入式通道存取電晶體元件之方法，其中在進行該離子佈植製程後，另包含： 於該凹入式閘極之一側壁上形成一間隙壁。
  4. 如申請專利範圍第3項所述之一種製作凹入式通道存取電晶體元件之方法，其中於該凹入式閘極之側壁上形成該間隙壁後，另包含：進行一清洗製程，將氧化物從該半導體基材之該主表面去除；以及從該半導體基材之該主表面成長出一磊晶矽層。
  5. 如申請專利範圍第3項所述之一種製作凹入式通道存取電晶體元件之方法，其中該間隙壁係為一氮化矽間隙壁。
  6. 如申請專利範圍第1項所述之一種製作凹入式通道存取電晶體元件之方法，其中該經修整之頸部的寬度介於10nm至35nm。
  7. 如申請專利範圍第1項所述之一種製作凹入式通道存取電晶體元件之方法，其中前述等向性蝕刻該凹入式閘極的裸露側壁係利用氨水(NH4 OH)或氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)溶液。
TW100146819A 2011-08-18 2011-12-16 製造一種凹入式通道存取電晶體元件之方法 TWI434357B (zh)

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