CN102956502B - 制造一种凹入式沟道存取晶体管器件的方法 - Google Patents

制造一种凹入式沟道存取晶体管器件的方法 Download PDF

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CN102956502B
CN102956502B CN201210061996.8A CN201210061996A CN102956502B CN 102956502 B CN102956502 B CN 102956502B CN 201210061996 A CN201210061996 A CN 201210061996A CN 102956502 B CN102956502 B CN 102956502B
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廖伟明
张明成
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Nanya Technology Corp
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H10B12/05—Making the transistor
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Abstract

本发明公开了一种制作凹入式沟道存取晶体管器件的方法。首先，提供一半导体衬底，其上具有一凹槽蚀入其主表面中。之后形成一栅极介电层在所述凹槽的内表面。再于之后形成一凹入式栅极在所述凹槽之中与之上。所述凹入式栅极包含一嵌入所述凹槽中与所述主表面下的凹入式栅部以一位在所述主表面上方的上栅部。所述凹入式栅极的一裸露侧壁会受到等向性蚀刻，因而形成一宽度小于所述凹入式栅部的经修整颈部。之后所述经修整颈部的一裸露侧壁会被氧化。

Description

制造一种凹入式沟道存取晶体管器件的方法
技术领域
本发明关于一种半导体器件及其制造方法，特别是关于一种制作凹入式沟道存取晶体管(recessed channel access transistor，RCAT)器件的方法，其所制作出来的沟道存取晶体管的栅极致漏极漏电流(gate induced drain leakage，GIDL)较小。
背景技术
随着半导体器件尺寸的减缩，栅沟道长度亦随之缩短，其结果可能会引发短沟道效应。公知解决短沟道效应的方法包含减少栅氧化层的厚度或增加掺杂子的浓度。然而，这类方法可能会造成器件可靠度的劣化并降低数据传输的速度。
近几年，业界中已发展出凹入式沟道存取晶体管器件(或简称为RCAT器件)，其可透过在物理层面上增加栅沟道长度而不增加栅极的横向面积的方式来抑制短沟道效应。相较于那些栅极形成在衬底平面上的平面栅极式晶体管而言，RCAT晶体管器件具有一形成在侧壁上的栅氧化层以及一蚀入基底中的凹槽底面，所述凹槽中会填入导电物质。因而可以提高式栅极的整合度。
然而在一般的RCAT器件中，当漏极电压(Vd)施加在一与NMOS晶体管电性连接的电容上时，其可能会发生栅极致漏极漏电(GIDL)的问题。多晶硅栅极的锐角与所述多晶硅栅极锐角附近相对较薄的栅氧化层设计会造成DRAM存储单元侧的电场过度集中。此电场集中的现象会导致漏电。栅极致漏极漏电对DRAM装置的更新特性有不好的影响。因此，吾人希望能消除或减缓RCAT器件中栅极诱导漏极漏电的现象，以改善DRAM装置的更新特性。
发明内容
据此，本发明的目的之一即在于提供一种制作凹入式沟道存取晶体管(RCAT)器件的改良方法，使所制作出来的沟道存取晶体管的栅极致漏极漏电流(GIDL)较小。
根据本发明一实施例，其提供了一种制造凹入式沟道存取晶体管器件的方法。首先，提供一半导体衬底，其上具有一凹槽蚀入其主表面中。一栅极介电层随后形成在所述凹槽的内表面。一凹入式栅极之后形成在所述凹槽之中与之上。所述凹入式栅极包含一凹入式栅部嵌入所述凹槽中与所述主表面下，及一位在所述主表面上方的上栅部。所述凹入式栅极的一裸露侧壁会受到等向性蚀刻，因而形成一宽度小于所述凹入式栅部的经修整颈部。所述经修整颈部的一裸露侧壁之后会被氧化。
无疑地，本发明的这类目的与其它目的在阅者读过下文以多种图示与绘图来描述的优选实施例细节说明后将变得更为显见。
附图说明
图1～6为横断面示意图，其表示出根据本发明实施例用以制作具有较低GIDL(栅极致漏极漏电流)的凹入式沟道存取晶体管器件的方法；及
图7描绘了本发明另一实施例。
其中，附图标记说明如下：
10   衬底                 34   介电盖体
10a  主表面               40   凹入式栅极
12   凹槽                 40a  凹入式栅部
12a  侧壁                 40b  上栅部
12b  底部42硅氧化层
12c  上壁角               50   离子注入工艺
14   栅极介电层           52   源极/栅极掺杂区
16   第一层结构           60   间隙壁
16a  图形化第一层结构     70   磊晶硅层
16b  凹槽                 100   凹入式沟道存取晶体管
18   第二层结构             116   薄层
18a  图形化第二层结构       145   组件符号
20   栅极材料层             216   经修整颈部
30   图形化光阻掩膜         34    介电盖体
具体实施方式
在下文的细节描述中，组件符号会标示在随附的图示中成为其中的一部份，并且以可实行所述实施例的特例描述方式来表示。这类实施例会说明足够的细节，使得本领域的技艺人士可具以实施。阅者须了解到在本发明中亦可利用其它的实施例或是在不悖离所述实施例的前提下做出结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所含有的实施例将由随附的权利要求项来加以界定。
对于晶体管与集成电路的制造而言，如在一平面工艺的场合中，「主表面」一词是指那些内部或近处制有多个晶体管的半导体层的表面。如文中所使用的，「垂直」一词是指与主表面实质上呈直角。一般而言，所述主表面会沿着所制作出的场效应晶体管上的单晶硅层的一<100>平面延伸。
图1～6为本发明的横断面示意图，其表示出根据本发明实施例用以制作出具有较小GIDL(栅极致漏极漏电流)的凹入式沟道存取晶体管(RCAT)器件的方法范例。如图1所示，其提供了一半导体衬底10(如硅衬底)或一含有硅质层的衬底。所述半导体衬底10具有一主表面10a与至少一凹槽12蚀入半导体衬底10的主表面10a中。所述凹槽可具有轮廓平顺的侧壁12a及位在主表面10a附近的上壁角12c。
在凹槽12形成后，栅极介电层14(如氧化硅或高K值氧化物)会形成在包含凹槽12侧壁12a及底部12b的内表面上。所述栅极介电层14亦会覆盖在主表面10a上。接着，一导电栅极材料层20会沈积在凹槽12中并填满凹槽12。根据此实施例，导电栅极材料层20包含一第一层结构16与一第二层结构18。举例言之，第一层结构16可包含多晶硅而第二层结构18则可包含金属、金属合金或金属硅化物等。然而，须了解在不悖离本发明精神的前提下，所述导电栅极材料层20可为单层结构或多层结构。之后，一图形化光阻掩膜30会形成在导电栅极材料层20上。
如图2所示，所述图形化光阻掩膜30形成后会进行一非等向性干蚀刻工艺来蚀刻那些未为所述图形化光阻掩膜30所覆盖的导电栅极材料层20。更特定言之，根据本发明实施例，第二层结构18未为所述图形化光阻掩膜30所覆盖的部位会完全被蚀去。上述的非等向性干蚀刻工艺会在第一层结构16裸露时停止。发明中亦可选择性地在第一层结构16裸露时进行一过蚀刻(overetch)工艺。
如图3所示，所述图形化光阻掩膜30会被拔除。其后，一介电盖体34会形成在图形化的第二层结构18a上。根据此实施例，介电盖体34可包含氮化硅，然本发明中亦可采用其它材质。在介电盖体34形成在图形化的第二层结构18a上后会进行一非等向性干蚀刻工艺来蚀刻那些未为介电盖体34所遮盖的第一层结构16，因而形成一图形化第一层结构16a。就此点而言，所述图形化第一层结构16、所述图形化第二层结构18、及所述介电盖体34共同建构出一凹入式栅极40。根据本发明实施例，上述的非等向性干蚀刻工艺会在所述栅极介电层14裸露时停止。即，第一层结构16未为介电盖体34遮盖的裸露部位会完全被蚀去，然其亦非必要条件。在另一实施例中，如图7所示，为了可靠度之故，栅极介电层14上会刻意保留一第一层结构16的薄层116结构。
凹入式栅极40包含一嵌入凹槽12中与主表面10a下的凹入式栅部40a以及位在所述主表面10a上的上栅部40b。就此点而言，所述上栅部40b的宽度W1略宽于所述凹入式栅部40a的宽度W2，较宽的上栅部40b会产生尖锐的多晶硅壁角，如图中标以组件符号145的虚圈所示。如先前所提到者，多晶硅栅部的锐角与相对较薄的栅氧化层会造成电场集中在存储单元侧壁角。此电场集中的现象会导致漏电。本发明方法即应运此问题而生。
如图4所示，凹入式栅极40形成后会进行一等向性蚀刻工艺(如采用氨水[NH4OH]或氢氧化四甲铵[Tetra-methylammonium Hydroxide，TMAH]的湿蚀刻工艺)来侧向蚀刻所述凹入式栅极40图形化第一层结构16a所裸露的侧壁部位，因而在所述图形化第一层结构16a中形成一凹槽16b及一宽度W3小于所述凹入式栅部40a宽度W2的经修整颈部216。就此点而言，凹入式栅极40具有蕈状的横断面形状。由于图形化第一层结构16a是以等向性蚀刻工艺来蚀刻，故所述经修整颈部216可具有弧形的侧壁轮廓。举例言之，根据此实施例，所述凹入式栅极40图形化第一层结构16a的受蚀部位在每一侧约为5-8nm厚，而宽度W3则可能介于10-35nm(以20-30nm为佳)。上述的等向性蚀刻工艺除去了多晶硅栅极处的锐角特征。
接着，如图5所示，进行一热氧化工艺来氧化所述经修整颈部216的裸露面，因而形成一硅氧化层42。介电盖体34、硅氧化层42、与栅极介电层14共同包覆了所述图形化第一层结构16a与第二层结构18a。在硅氧化层42形成后会进行一离子注入工艺50来将掺质注入半导体衬底10的主表面10a中，因而在所述凹入式栅极40的两侧形成一源极/漏极掺杂区52。本发明的凹入式栅极40与凹入式沟道存取晶体管100器件于此完成。
如图6所示，本发明可选择性地在上述凹入式栅极40的两侧壁上形成一氮化硅间隙壁60。所述氮化硅间隙壁60形成后会进行一清洗工艺来除去残留的栅极介电层14或来自半导体衬底10主表面10a的原生氧化层等氧化物。其后，一磊晶硅层70会在上述源极/漏极掺杂区52上半导体衬底10所裸露的主表面10a上成长(或沈积于其上)。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (7)

1.一种制作凹入式沟道存取晶体管器件的方法，其特征在于，包含：
提供一半导体基材，其主表面上具有一凹槽；
于所述凹槽内形成一栅极介电层；
于凹槽内形成一凹入式栅极，其中所述凹入式栅极包含一凹入式栅部，嵌入在所述凹槽内且位于所述主表面下，以及一上栅部，位于所述主表面上，其中所述上栅部包含一图案化上层以及覆盖住所述图案化上层的一侧壁与一上表面的一介电盖体；
等向性蚀刻所述凹入式栅极的裸露侧壁，俾形成一经修整的颈部，其宽度小于所述凹入式栅极的宽度；以及
氧化所述经修整的颈部的裸露侧壁。
2.如权利要求1所述的制作凹入式沟道存取晶体管器件的方法，其特征在于，氧化所述经修整的颈部的裸露侧壁后，另包含：
进行一离子注入工艺，将掺质注入所述半导体衬底的所述主表面，俾于所述凹入式栅极的两侧形成一源极/漏极掺杂区。
3.如权利要求2所述的制作凹入式沟道存取晶体管器件的方法，其特征在于，在进行所述离子注入工艺后，另包含：
于所述凹入式栅极的一侧壁上形成一间隙壁。
4.如权利要求3所述的制作凹入式沟道存取晶体管器件的方法，其特征在于，于所述凹入式栅极的侧壁上形成所述间隙壁后，另包含：
进行一清洗工艺，将氧化物从所述半导体衬底的所述主表面去除；以及
从所述半导体衬底的所述主表面成长出一磊晶硅层。
5.如权利要求3所述的制作凹入式沟道存取晶体管器件的方法，其特征在于， 所述间隙壁为一氮化硅间隙壁。
6.如权利要求1所述的制作凹入式沟道存取晶体管器件的方法，其特征在于，所述经修整的颈部的宽度介于10nm至35nm。
7.如权利要求1所述的制作凹入式沟道存取晶体管器件的方法，其特征在于，等向性蚀刻所述凹入式栅极的裸露侧壁的步骤是利用氨水(NH4OH)或氢氧化四甲基铵(tetramethylammonium hydroxide,TMAH)溶液。
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