TWI417964B - 具有浸沒接點之電晶體及其形成之方法 - Google Patents
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
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Description
本發明大體係關於半導體裝置,且更明確地說係關於具有浸沒接點之電晶體。
傳統上,用於將電流電極連接至一電晶體之接點形成於源極區及汲極區之各別表面上。然而,形成於源極區及汲極區之表面上的接點在三維裝置(諸如FinFET電晶體或三閘極電晶體)中引起關於電流之問題。詳言之,如圖1所示,展示一習知FinFET電晶體10。習知FinFET電晶體10可形成於一基板層(諸如氧化層12)上。習知FinFET電晶體10可包括一源極/汲極結構14、一鰭狀物16、一形成於鰭狀物16上之鰭帽18及一形成於一閘極介電20上的閘極22。在一矽化物層27形成於源極/汲極結構14上之後,一源極/汲極接點24可形成於源極/汲極結構14上。如圖1所示,電流沿著鰭狀物之(例如,鰭狀物16)側壁流動,如由定向箭頭26展示。該電流接著流向源極/汲極接點24,如由定向箭頭28指示。因為源極/汲極接點僅形成於源極/汲極結構14之表面上,故沿著該鰭狀物之底部流動之電流導致較高的電阻,此係因為其在到達源極/汲極接點24之前必須行進較長路徑。此為該習知FinFET電晶體造成一較高的有效源極/汲極電阻。儘管圖1展示電流自鰭狀物16之底部流向源極/汲極接點24,但電流亦自鰭狀物16之另一側上的源極/汲極接點流向鰭狀物16之底部。此對在習知FinFET電晶體中流動之電流造成額外電阻。
此外,傳統上,習知MOSFET裝置上之閘極在作用區外的閘電極材料之頂部接觸。然而,由於閘極厚度減少,故閘極電阻成為一問題。詳言之,在許多情況下,閘電極為若干材料之一層壓。通常,底層為低電阻導體,且閘極之剩餘部分係由摻雜多晶矽或金屬矽化物製成。總之,形成該閘極之剩餘部分的材料具有較高電阻率。該閘極接點因此與具有一低電阻率之底層分隔,而是與該層之具有高電阻率之剩餘部分接觸。
因此,需要一具有較低源極/汲極電阻及較低閘極電阻之電晶體。
在一項態樣中,一方法包括形成一半導體結構及形成一第一接點。形成該第一接點之步驟包括移除半導體裝置電極結構之一第一部分以形成一開口及在該開口中形成接點材料,其中該第一接點電耦接至該半導體裝置電極結構。如本文所使用之術語"半導體裝置電極結構"可包括一由半導體材料或金屬材料或其任何組合之部分製成的裝置電極結構。此外,該半導體裝置電極結構可包括一閘極結構,其中該第一接點可電耦接至該閘極結構。如本文所使用之術語"閘極結構"可包括一由半導體材料或金屬材料或其任何組合之部分製成的閘極結構。
在另一態樣中,一半導體裝置包含一電極結構及一第一接點,其中該第一接點延伸至該電極結構中且電耦接至該電極結構。
在另一態樣中,一方法包括形成一半導體結構,該半導體結構包括一第一電流電極區、一第二電流電極區及一通道區,該通道區係定位於該第一電流電極區與該第二電流電極區之間,其中該通道區係定位於該半導體結構之一鰭狀物結構中,其中該通道區中之載流子傳輸大體係在該第一電流電極區與該第二電流電極區之間的一水平方向上。該方法進一步包括形成一第一接點,其中形成該第一接點包括:(1)移除該半導體結構之一第一部分以形成一開口,其中該開口在該第一電流電極區中;及(2)在該開口中形成接點材料。如本文所使用之術語"半導體結構"可包括一由半導體材料或金屬材料或其任何組合之部分製成的結構。
圖2為根據本發明之一項實施例之電晶體50之一局部透視圖。如圖2所示,作為電晶體50之部分,源極/汲極接點24可形成為一埋入式源極/汲極接點30。由於源極/汲極接點之埋入式性質,故在鰭狀物16之底部中流動之電流可在一大體平行於甚至在該閘極外部的氧化層20的路徑中行進,如定向箭頭31所指示。此將導致在鰭狀物16之底部中流動之電流遭遇較低電阻,此接著將減少電晶體50之有效的源極至汲極電阻。另外,流經埋入式源極/汲極接點24之電流遭遇較低的電阻,因為接點材料之電阻率比高度摻雜矽的電阻率低。儘管圖2按照源極/汲極接點討論電流,但根據本發明之其他實施例之其他電晶體可具有可受益於改良電流的其他類型之接點。儘管圖2展示一大體為矩形之埋入式源極/汲極接點,但其可具有另一形狀。源極/汲極接點30可(例如)在頂部逐漸減少約為120奈米之寬度,且在底部逐漸減少約為90奈米之寬度。另外及/或其他,在不偏離本發明之範疇的情況下,電晶體50可含有額外層或組件。
圖3為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖。作為形成電晶體50之一部分,一源極結構33及一汲極結構35以及一鰭狀物36可形成於氧化物42上。儘管圖3展示氧化物42,但電晶體50可形成於任何類型之基板上,包括(例如)絕緣體上矽或塊狀晶圓。一閘極38可形成為電晶體50之一部分。舉例而言,根據閘極材料之厚度,閘極38可為1000埃。閘極材料可為多晶矽、碳化鉭、氮化鈦、三氮化鉭或任何其他適合的閘極材料。閘極材料亦可為一包含兩層之層壓,其中一第一層可由碳化鉭、氮化鉭或氮化鈦形成,且一第二層可由多晶矽或矽化物(諸如鎳矽化物、矽化鈦或鈷矽化物)形成。舉例而言,該第一層可為約250埃高,且該第二層可為約600埃及大於600埃高。儘管圖3未展示一閘極介電,但閘極介電亦可作為該步驟之一部分而形成。介電側壁間隔40可鄰近閘極38予以形成。介電側壁間隔40可為氧化矽或氮化矽間隔。如圖3所示,電晶體50可具有一源極區32、一汲極區34及一通道區37。電流可自源極區32經由通道區37流至汲極區34。載流子傳輸(例如,關於p通道裝置之電洞及關於n通道裝置之電子)可大體在源極區32與汲極區34之間的一水平方向上。通常,可將源極區32及汲極區34稱作電流電極區。
圖4為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖。作為該步驟之一部分,TEOS層52可形成於電晶體50之頂部。接點開口54及56可接著形成於TEOS層52中。接點開口可藉由移除形成電晶體50之半導體結構之一部分而形成。可藉由蝕除形成電晶體50之半導體結構之一部分而形成接點開口54及56。儘管圖4展示接點開口54及56一直延伸至氧化層42,但接點開口54及56無需延伸那麼遠。另外及/或其他,接點開口54及56可未被形成源極/汲極區之半導體材料予以完全封閉或圍繞。圖5展示圖2之電晶體在該製造步驟期間的一局部俯視圖。儘管接點開口54及56經描述為作為該步驟之部分形成,但接點開口54及56可在形成鰭狀物36時形成。
圖6為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖。在形成接點開口54及56之後,可形成一襯墊58,如圖6所示。舉例而言,可使用鎳、鈷或任何其他適合的材料來形成襯墊58。儘管襯墊58經展示為一層,但襯墊58可由多個層形成。接著,如圖7所示,一矽化物層60可形成於接點開口54及56之側壁上。矽化物層60可為鎳矽化物層或鈷矽化物層。接著,如圖8所示,可形成一障壁層62。舉例而言,可使用鈦及氮化鈦來形成障壁層62。接著,可沈積一接點材料64,其亦可形成於接點開口54及56中。接點材料64可為鎢、銅或任何其他適合的接點材料。接著,如圖9所示,例如可使用化學機械研磨法來使接點材料64平坦化。因此,埋入式源極/汲極接點66及68可形成於電晶體50中。
圖10為根據本發明之一項實施例之多鰭狀物電晶體之一局部俯視圖。儘管已關於單一鰭狀物結構描述以上過程步驟,但亦可形成一具有埋入式源極/汲極接點之多鰭狀物電晶體。因此,如圖10所示,一電晶體70可包括一包含鰭狀物78、80、82、84之多鰭狀物結構74,可使用半導體處理技術來形成。多鰭狀物結構74可包括一源極結構72及一汲極結構76。亦可形成一閘極88。可使用以上描述的處理步驟形成埋入式源極/汲極接點90、92、94、96、98及100。舉例而言,每一鰭狀物可為20奈米寬且可隔開140奈米之距離。此外,儘管圖10展示埋入式源極/汲極接點90、92、94、96、98及100與鰭狀物78、80、82及84偏移,但其可對準該等鰭狀物而形成,例如圖5所示。
圖11為一具有埋入式閘極接點之平面電晶體之一局部俯視圖。平面電晶體可具有一形成於一矽渠溝式絕緣體104上之作用區102。作用區102可包括(例如)源極/汲極及通道區。一閘極106可形成於作用區102之頂部上。可形成閘極接點108及110以連接閘極材料。現參看圖12,如圖所示,接點108及110可為埋入式。換言之,可在為該等閘極接點蝕刻開口一直通到矽渠溝式絕緣體104之後,沈積形成接點108及110之接點材料。儘管圖12展示閘極接點材料一直延伸至矽渠溝式絕緣體104,但閘極接點材料無需一直延伸至矽渠溝式絕緣體104。此外,在於閘極接點開口中沈積接點材料之前,可沈積鎳或鎳鉑從而降低肖特基接觸障壁。再者,閘極接點開口之側壁可在每一側壁上具有接點材料層。另外,儘管未圖示,但閘極106可為若干層之一層壓。另外及/或其他,閘極接點開口108及110可未被閘極材料予以完全封閉或圍繞。
圖13展示具有埋入式閘極接點之圖2之電晶體之一局部透視圖。詳言之,如圖所示,一閘極接點112可埋入於閘極22中。舉例而言,閘極接點112可一直埋入至氧化物12,儘管其無需一直埋入。此外,在於閘極接點開口中沈積接點材料之前,可沈積鎳或鎳鉑從而降低肖特基接觸障壁。再者,閘極接點開口之側壁可在每一側壁上具有接點材料層。另外,儘管未圖示,但閘極112可為若干層之一層壓。
在上述的說明書中,已根據特定實施例而描述本發明。然而,一般熟習此項技術者瞭解在不偏離以下申請專利範圍所闡述的本發明之範疇的情況下可進行各種修改及改變。因此,應說明性地而非限制性地看待本說明書及圖式,且所有該等修改意欲包括在本發明之範疇內。
上文已關於特定實施例來描述利益、其他優點及問題的解決方法。然而,不將利益、優點、問題的解決方法及可導致任何利益、優點或解決方法出現或變得較顯著的任何元件理解為任何或所有申請專利範圍之關鍵的、必需的或基本的特徵或元件。如本文所使用之術語"包含"或其任何其他變體意欲涵蓋非排他性內含物,使得包含一列表之元件之過程、方法、物件或設備不僅包括彼等元件而且可包括未明確列出或為該過程、方法、物件或設備所固有的其他元件。
10...FinFET電晶體
12...氧化層
14...源極汲極結構
16...鰭狀物
18...鰭帽
20...氧化層
22...閘極
24...汲極接點
26...箭頭
27...矽化物層
28...箭頭
30...汲極接點
31...定向箭頭
32...源極區
33...源極結構
34...汲極區
35...汲極結構
36...鰭狀物
37...通道區
38...閘極
40...介電側壁間隔
42...氧化物
50...電晶體
52...TEOS層
54...接點開口
56...接點開口
58...襯墊
60...矽化物層
62...障壁層
64...接點材料
66...汲極接點
68...汲極接點
70...電晶體
72...源極結構
74...多鰭狀物結構
76...汲極結構
78...鰭狀物
80...鰭狀物
82...鰭狀物
84...鰭狀物
88...閘極
90...汲極接點
92...汲極接點
94...汲極接點
96...汲極接點
98...汲極接點
100...汲極接點
102...區域
104...矽渠溝式絕緣體
106...閘極
108...閘極接點
110...閘極接點
112...閘極接點
圖1為一習知電晶體之一局部透視圖;圖2為根據本發明之一項實施例的電晶體之一局部透視圖;圖3為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖;圖4為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖;圖5為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部俯視圖;圖6為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖;圖7為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖;圖8為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖;圖9為根據本發明之一項實施例之圖2之電晶體在一製造步驟期間的一局部橫截面圖;圖10為根據本發明之一項實施例之多鰭狀物電晶體之一局部俯視圖;圖11為根據本發明之一項實施例之平面電晶體之一局部俯視圖;圖12為根據本發明之一項實施例之平面電晶體之一局部橫截面圖;及圖13為根據本發明之一項實施例之電晶體之一局部透視圖。
熟習此項技術者瞭解圖式中之元件係為了簡單及明晰的目的而被說明且未必按比例描繪。舉例而言,圖式中之一些元件的尺寸可相對於其他元件而放大從而幫助提高對本發明之實施例的理解。
12...氧化層
14...源極/汲極結構
16...鰭狀物
18...鰭帽
20...氧化層
22...閘極
24...汲極接點
26...箭頭
27...矽化物層
30...汲極接點
31...定向箭頭
50...電晶體
Claims (10)
- 一種用於形成一半導體裝置之方法,其包含:形成一半導體裝置電極結構在一基板上;及形成一第一接點,其中形成該第一接點包括:移除該半導體裝置電極結構之一第一部分以在該半導體裝置電極結構上形成一第一開口,其中該第一開口由該半導體裝置電極結構之一側壁界定,且該第一開口自該半導體裝置結構頂部延伸至該基板;及在該第一開口中形成接點材料;其中該第一接點電耦接至該半導體裝置電極結構。
- 如請求項1之方法,其中該半導體裝置電極結構包括一第一電流電極區,且該第一接點電耦接至該第一電流電極區。
- 如請求項2之方法,其中該第一電流電極區具有一半導體結構,該半導體結構進一步包括:一第二電流電極區;一通道區,其定位於在該第一電流電極區與該第二電流電極區之間的該半導體結構中,該通道區定位於該半導體結構之一鰭狀物結構中,其中該通道區中之一載流子傳輸大體係在該第一電流電極區與該第二電流電極區之間的一水平方向上。
- 如請求項3之方法,其中該鰭狀物結構水平地延伸於該半導體結構之一第一結構與該半導體結構之一第二結構之間,其中該第一電流電極區之至少一部分係定位於該 第一結構中,且該第二電流電極區之至少一部分係定位於該第二結構中,且其中經移除之該第一部分具有該第一結構。
- 如請求項3之方法,其進一步包含:形成一第二接點,其中形成該第二接點包括:移除該第二電流電極區之一第二部分以在該半導體裝置電極結構上形成一第二開口;及在第二開口中形成接點材料;其中該第二接點電耦接至該第二電流電極區。
- 如請求項1之方法,其中該半導體裝置電極結構包括一閘極結構,且其中該第一接點電耦接至該閘極結構。
- 如請求項1之方法,其中在該第一開口中形成接點材料進一步包括:在該第一開口中形成一障壁層材料;及在形成該障壁層材料之後,在該第一開口中形成一第二材料。
- 如請求項1之方法,其中移除一第一部分進一步包括:在該半導體裝置電極結構上形成一層介電材料;在該層介電材料中蝕刻一第二開口;及經由該第二開口蝕刻該半導體裝置電極結構之該第一部分以移除該第一部分。
- 如請求項1之方法,該方法進一步包含:在於該開口中形成接點材料之前,在該側壁上形成一矽化物。
- 一種用於形成一半導體裝置之方法,其包含:形成一半導體結構於一基板上,該半導體結構包括一第一電流電極區、一第二電流電極區、一閘極及一通道區,該通道區係定位於該第一電流電極區與該第二電流電極區之間,其中該通道區係定位於該半導體結構之一鰭狀物結構中,其中在該通道區中之一載流子傳輸大體係在該第一電流電極區與該第二電流電極區之間的一水平方向上;及形成一第一接點,其中形成該第一接點包括:移除該半導體結構之一第一部分以形成一第一開口,其中該第一開口係在該第一電流電極區中,且該第一開口由該第一電流電極區之一側壁界定,且該第一開口自該第一電流電極區頂部延伸至該基板,且該第一開口延伸至至少與該閘極一樣深的深度;及在該開口中形成接點材料。
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JP2009520367A (ja) | 2009-05-21 |
US20070161170A1 (en) | 2007-07-12 |
US20110210395A1 (en) | 2011-09-01 |
US20130009222A1 (en) | 2013-01-10 |
EP1964167A2 (en) | 2008-09-03 |
US7968394B2 (en) | 2011-06-28 |
WO2007120283A2 (en) | 2007-10-25 |
US8633515B2 (en) | 2014-01-21 |
WO2007120283A3 (en) | 2008-10-23 |
TW200733249A (en) | 2007-09-01 |
US8314448B2 (en) | 2012-11-20 |
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