TWI406288B - 記憶體的測試裝置以及測試方法 - Google Patents

記憶體的測試裝置以及測試方法 Download PDF

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Publication number
TWI406288B
TWI406288B TW098115376A TW98115376A TWI406288B TW I406288 B TWI406288 B TW I406288B TW 098115376 A TW098115376 A TW 098115376A TW 98115376 A TW98115376 A TW 98115376A TW I406288 B TWI406288 B TW I406288B
Authority
TW
Taiwan
Prior art keywords
subroutine
signal
confirmed
update
dram
Prior art date
Application number
TW098115376A
Other languages
English (en)
Chinese (zh)
Other versions
TW200951972A (en
Inventor
Takashi Nakamura
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of TW200951972A publication Critical patent/TW200951972A/zh
Application granted granted Critical
Publication of TWI406288B publication Critical patent/TWI406288B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
TW098115376A 2008-05-09 2009-05-08 記憶體的測試裝置以及測試方法 TWI406288B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008123353A JP5113617B2 (ja) 2008-05-09 2008-05-09 メモリの試験装置および試験方法

Publications (2)

Publication Number Publication Date
TW200951972A TW200951972A (en) 2009-12-16
TWI406288B true TWI406288B (zh) 2013-08-21

Family

ID=41264560

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098115376A TWI406288B (zh) 2008-05-09 2009-05-08 記憶體的測試裝置以及測試方法

Country Status (5)

Country Link
US (1) US8345496B2 (ja)
JP (1) JP5113617B2 (ja)
KR (1) KR101202531B1 (ja)
TW (1) TWI406288B (ja)
WO (1) WO2009136503A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10261852B2 (en) 2013-05-31 2019-04-16 Hewlett Packard Enterprise Development Lp Memory error determination
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06236683A (ja) * 1993-02-09 1994-08-23 Oki Electric Ind Co Ltd メモリリフレッシュ制御回路
JPH08327703A (ja) * 1994-09-01 1996-12-13 Teledyne Inc ベクトル・モジュール・テーブルを用いる自動テスト装置のためのメモリ・アーキテクチャ
JPH117763A (ja) * 1997-06-13 1999-01-12 Nec Ic Microcomput Syst Ltd Ｄｒａｍリフレッシュ制御方法及びその回路
US6138259A (en) * 1996-10-18 2000-10-24 Advantest Corporation Semiconductor memory testing apparatus
US20040233745A1 (en) * 2001-05-22 2004-11-25 Carsten Ohlhoff Dynamic memory and method for testing a dynamic memory
US7114025B2 (en) * 2002-10-31 2006-09-26 Fujitsu Limited Semiconductor memory having test function for refresh operation
US20060285413A1 (en) * 2002-09-20 2006-12-21 Fujitsu Limited Semiconductor memory
US20070030746A1 (en) * 2005-08-04 2007-02-08 Best Scott C Memory device testing to support address-differentiated refresh rates
US20070033338A1 (en) * 2005-08-04 2007-02-08 Tsern Ely K Memory with address-differentiated refresh rate to accommodate low-retention storage rows

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6464050A (en) * 1987-09-04 1989-03-09 Nec Corp Refresh control circuit for memory test device
JPH06259962A (ja) * 1991-11-20 1994-09-16 Oki Micro Design Miyazaki:Kk 半導体メモリ装置
JP2011248964A (ja) * 2010-05-28 2011-12-08 Elpida Memory Inc 半導体装置及びその制御方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06236683A (ja) * 1993-02-09 1994-08-23 Oki Electric Ind Co Ltd メモリリフレッシュ制御回路
JPH08327703A (ja) * 1994-09-01 1996-12-13 Teledyne Inc ベクトル・モジュール・テーブルを用いる自動テスト装置のためのメモリ・アーキテクチャ
US6138259A (en) * 1996-10-18 2000-10-24 Advantest Corporation Semiconductor memory testing apparatus
JPH117763A (ja) * 1997-06-13 1999-01-12 Nec Ic Microcomput Syst Ltd Ｄｒａｍリフレッシュ制御方法及びその回路
US20040233745A1 (en) * 2001-05-22 2004-11-25 Carsten Ohlhoff Dynamic memory and method for testing a dynamic memory
TWI276108B (en) * 2001-05-22 2007-03-11 Infineon Technologies Ag Dynamic memory and method for testing a dynamic memory
US20060285413A1 (en) * 2002-09-20 2006-12-21 Fujitsu Limited Semiconductor memory
US7114025B2 (en) * 2002-10-31 2006-09-26 Fujitsu Limited Semiconductor memory having test function for refresh operation
US20070030746A1 (en) * 2005-08-04 2007-02-08 Best Scott C Memory device testing to support address-differentiated refresh rates
US20070033338A1 (en) * 2005-08-04 2007-02-08 Tsern Ely K Memory with address-differentiated refresh rate to accommodate low-retention storage rows

Also Published As

Publication number Publication date
KR101202531B1 (ko) 2012-11-16
US8345496B2 (en) 2013-01-01
WO2009136503A1 (ja) 2009-11-12
JP2009272013A (ja) 2009-11-19
US20110116333A1 (en) 2011-05-19
KR20110016920A (ko) 2011-02-18
JP5113617B2 (ja) 2013-01-09
TW200951972A (en) 2009-12-16

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MM4A Annulment or lapse of patent due to non-payment of fees