JPS6464050A - Refresh control circuit for memory test device - Google Patents

Refresh control circuit for memory test device

Info

Publication number
JPS6464050A
JPS6464050A JP62220260A JP22026087A JPS6464050A JP S6464050 A JPS6464050 A JP S6464050A JP 62220260 A JP62220260 A JP 62220260A JP 22026087 A JP22026087 A JP 22026087A JP S6464050 A JPS6464050 A JP S6464050A
Authority
JP
Japan
Prior art keywords
memory
test
signal
test executing
executing state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62220260A
Other languages
Japanese (ja)
Inventor
Fumihiko Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62220260A priority Critical patent/JPS6464050A/en
Publication of JPS6464050A publication Critical patent/JPS6464050A/en
Pending legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To hold the internal state of a memory to be tested with no change even with plural times of intermittent tests, by performing the refresh actions of said memory for an interrupted period of tests. CONSTITUTION:A timing signal selection circuit 101 delivers a test timing signal 101a to a memory 20 to be tested in a memory test executing state and then a refresh timing signal to the memory 20 as a timing signal 101c in a non-test executing state respectively based on a state signal 103 showing a test executing or non-test executing state. An address signal selection circuit 102 receives the signal 103 and sends a test address signal 102a to the memory 20 in a test executing state and then a refresh address signal 102b as an address signal 102c in a non-test executing state respectively. The memory 20 receives both signals 101c and 102c and caries out the actions decided by these signals.
JP62220260A 1987-09-04 1987-09-04 Refresh control circuit for memory test device Pending JPS6464050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62220260A JPS6464050A (en) 1987-09-04 1987-09-04 Refresh control circuit for memory test device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62220260A JPS6464050A (en) 1987-09-04 1987-09-04 Refresh control circuit for memory test device

Publications (1)

Publication Number Publication Date
JPS6464050A true JPS6464050A (en) 1989-03-09

Family

ID=16748396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62220260A Pending JPS6464050A (en) 1987-09-04 1987-09-04 Refresh control circuit for memory test device

Country Status (1)

Country Link
JP (1) JPS6464050A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04288648A (en) * 1990-07-03 1992-10-13 Digital Equip Corp <Dec> Mode changeover of memory device by diagnostic scan
JP2009272013A (en) * 2008-05-09 2009-11-19 Advantest Corp Device and method for testing memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04288648A (en) * 1990-07-03 1992-10-13 Digital Equip Corp <Dec> Mode changeover of memory device by diagnostic scan
JP2009272013A (en) * 2008-05-09 2009-11-19 Advantest Corp Device and method for testing memory
US8345496B2 (en) 2008-05-09 2013-01-01 Advantest Corporation Memory test apparatus and testing method

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