TWI385763B - 四方扁平無引腳半導體封裝及其製作方法 - Google Patents

四方扁平無引腳半導體封裝及其製作方法 Download PDF

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Publication number
TWI385763B
TWI385763B TW098115827A TW98115827A TWI385763B TW I385763 B TWI385763 B TW I385763B TW 098115827 A TW098115827 A TW 098115827A TW 98115827 A TW98115827 A TW 98115827A TW I385763 B TWI385763 B TW I385763B
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Taiwan
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column
terminal pins
semiconductor package
quad flat
die
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TW098115827A
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English (en)
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TW200950013A (en
Inventor
Tung Hsien Hsieh
Nan Cheng Chen
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Mediatek Inc
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Publication of TWI385763B publication Critical patent/TWI385763B/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

四方扁平無引腳半導體封裝及其製作方法
本發明係有關於一種晶片封裝，且特別有關於一種具有擴充的端子引腳的高接腳數(high-pin-count)四方扁平無引腳(quad flat non-lead,以下簡稱QFN)半導體封裝及其相關方法。
隨著電子產品的小型化，手持產品之市場不斷擴張。主要受手機及數位助理市場之驅動，所述裝置之製造商正面臨著產品體積壓縮以及更多類個人電腦功能之需求的挑戰。而額外增加之功能僅能藉由高性能之邏輯積體電路結合增加之記憶體容量來達成。此種挑戰，為更小之印製電路板，其為表面黏著元件製造商設計產品，以佔用可能之最小面積帶來了壓力。
現今手持產品市場中，許多廣泛使用之元件開始從有引腳形式向無引腳形式過渡。手持產品製造商之主要驅動力係為由這些元件之較小黏著面積而節省的印製電路板空間。此外，同提高的電子性能一樣，絕大多數元件於重量及高度上仍可減少。由於主要的晶片尺寸封裝(chip scale package)已轉向無引腳設計，因此節省出的額外空間可用於配置附加的裝置功能所需之元件。由於無引腳設計可使用許多現有的導線架(leadframe)製程，因此產品線之轉換成本可降至最低。
類似於有引腳元件，無引腳設計使用焊線接合作為積體電路(以下簡稱IC)與導線架之間的主要連接方式。然而，由於獨特的安放位置幾何形狀以及外觀尺寸密度，傳統的焊線接合製程可能無法以高產出率進行生產。對於這些設計而言，需要額外的焊線接合性能以及改進的製程以達成可接受之產品產出率。
專利號為6,238,955之美國專利揭露了一種低腳數晶片封裝，其包含用於接收半導體晶片之晶粒墊以及電性耦接至半導體晶片之多個連接墊，其中晶粒墊及連接墊皆具有凹式外形。封裝主體形成於半導體晶片之上，晶粒墊及連接墊之一部分由封裝主體底部延伸出封裝主體。
專利號為6,261,864之美國專利揭露了一種晶片封裝。半導體晶片、晶粒墊以及連接墊被封裝於封裝主體中，晶粒墊及連接墊之較低表面露於封裝主體之外。晶粒墊及連接墊係由蝕刻形成，因此其具有凹式外形，且其厚度比由電鍍形成之傳統晶粒墊及連接墊厚得多。
專利號為6,306,685之美國專利揭露了一種凸點晶片載體(bump chip carrier)成形方法。乾塑膠被用於具有適合厚度之銅底板的頂面與底面。電路圖樣形成於每一乾塑膠之上，金屬被鍍於每一電路圖樣之上以形成連接墊及散熱通道，而晶粒黏著於銅底板之上。晶粒所黏著之銅底板之表面被塑模以形成模層。
專利號為6,342,730之美國專利揭露了一種封裝架構，其包含接受半導體晶片之晶粒墊以及電性耦接至晶粒墊之多個連接墊。半導體晶片、晶粒墊以及連接墊被封裝於封裝主體中，晶粒墊及連接墊之較低表面露於封裝主體之外。所述晶粒墊及連接墊皆具有大體為凹式之外形。
專利號為6,495,909之美國專利揭露了一種晶片封裝。半導體晶片、晶粒墊以及連接墊被封裝於封裝主體中，晶粒墊及連接墊之較低表面露於封裝主體之外。晶粒墊及連接墊係具有T形之外形，從而能夠延遲水分擴散入封裝之時間。
專利號為6,621,140之美國專利揭露了一種半導體封裝，其具有整體形成於導線架之電感性部分。所述電感性部分可透過焊線接合直接連接於導線架之引腳，或間接連接於半導體晶粒之引腳或接合墊，以形成電感。
為減少表面黏著元件所占用印製電路板之面積並提高產品之產出率，特提供以下技術方案：本發明實施例提供一種四方扁平無引腳半導體封裝，包含晶粒黏接墊、半導體晶粒、至少一列內部端子引腳、多個第一焊線、至少一列擴充的外部端子引腳、至少一列中間端子、多個第二焊線以及多個第三焊線。所述晶粒黏接墊具有一凹區；所述半導體晶粒安裝於晶粒黏接墊之凹區；所述至少一列內部端子引腳位於靠近晶粒黏接墊之位置；所述多個第一焊線用於將所述至少一列內部端子引腳分別焊接至半導體晶粒；所述至少一列擴充的外部端子引腳位於沿著四方扁平無引腳半導體封裝外圍之位置；所述至少一列中間端子位於所述至少一列內部端子引腳與所述至少一列擴充的外部端子引腳之間；所述多個第二焊線用於將所述至少一列中間端子分別焊接至半導體晶粒；以及所述多個第三焊線用於將所述至少一列中間端子分別焊接至所述至少一列擴充的外部端子引腳。
本發明實施例另提供一種四方扁平無引腳半導體封裝，包含晶粒黏接墊、半導體晶粒、至少一列內部端子引腳、多個第一焊線、至少一列擴充的外部端子引腳、至少一列中間端子、多個第二焊線以及走線。所述晶粒黏接墊具有一凹區；所述半導體晶粒安裝於晶粒黏接墊之凹區；所述至少一列內部端子引腳位於靠近晶粒黏接墊之位置：所述多個第一焊線用於將所述至少一列內部端子引腳分別焊接至半導體晶粒；所述至少一列擴充的外部端子引腳位於沿著四方扁平無引腳半導體封裝外圍之位置；所述至少一列中間端子位於所述至少一列內部端子引腳與所述至少一列擴充的外部端子引腳之間；所述多個第二焊線用於將所述至少一列中間端子分別焊接至半導體晶粒；以及所述走線用於將所述至少一列中間端子其中之一中間端子連接至所述至少一列擴充的外部端子引腳其中之一擴充的外部端子引腳。
本發明實施例另提供一種製作四方扁平無引腳半導體封裝的方法，包含半蝕刻載體之第一面，以形成引腳陣列之頂部以及晶粒黏接墊之晶粒黏接面，其中引腳陣列包含至少一列內部端子引腳、至少一列擴充的外部端子引腳以及至少一列中間端子，所述至少一列內部端子引腳位於靠近晶粒黏接墊之位置，所述至少一列擴充的外部端子引腳位於沿著四方扁平無引腳半導體封裝外圍之位置，所述至少一列中間端子位於所述至少一列內部端子引腳與所述至少一列擴充的外部端子引腳之間；將半導體晶粒安裝於晶粒黏接面；透過多個第一導體焊線將半導體晶粒電性連接至所述至少一列內部端子引腳之對應的多個端子引腳以及所述至少一列中間端子之對應的多個端子；透過多個第二導體焊線將所述至少一列中間端子之多個端子電性連接至所述至少一列擴充的外部端子引腳之對應的多個端子引腳；利用模套封裝半導體晶粒、多個第一導體焊線以及多個第二導體焊線；以及半蝕刻所述載體之與第一面相對之第二面，以形成引腳陣列之底部以及該晶粒黏接墊。
以上所述的四方扁平無引腳半導體封裝及其製作方法，能夠以較低之成本封裝表面黏著元件，使其產出率提高並使其占用印製電路板之面積減少。
於說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，硬體製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。於通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。另外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
請一並參考第1圖及第2圖。第1圖係依本發明實施例之具有中間端子之QFN半導體封裝之剖面示意圖。第2圖係依本發明所述實施例之具有中間端子之QFN半導體封裝之佈線的上視圖。如第1圖及第2圖所示，QFN半導體封裝1包含具有凹區10a之晶粒黏接墊(die attach pad)10。半導體晶粒20黏著於晶粒黏接墊10之凹區10a中。晶粒黏接墊10具有底面10b，其露於模套(mold cap)30之外。晶粒黏接墊10可包含電源或接地環11。至少一列內部端子引腳12位於靠近晶粒黏接墊10之位置。至少一列擴充的外部端子引腳14位於沿著QFN半導體封裝1外圍之位置。至少一列中間端子13位於內部端子引腳12與擴充的外部端子引腳14之間。依本發明之另一實施例，晶粒黏接墊10可省略。
半導體晶粒20具有頂面20a，其上有多個接合墊21(包含21a、21b及21c)。半導體晶粒20上之接合墊21a透過金焊線22焊接至電源或接地球環11。半導體晶粒20上之接合墊21b透過金焊線24焊接至內部端子引腳12。半導體晶粒20上之接合墊21c透過金焊線26焊接至中間端子13。
依本實施例，外部端子引腳14與半導體晶粒之距離超過最大焊線長度，所述最大焊線長度係由焊接工具或焊線機為半導體晶粒之特定的最小焊墊開窗尺寸而提供。如熟習該項技術者所知悉，焊線機所提供之最大焊線長度取決於晶粒上接合墊之最小焊墊開窗尺寸。
舉例而言，對於具有最小焊墊開窗尺寸為43微米(micrometer)之接合墊21而言，典型之焊線機僅可提供140密耳(mil)之最大焊線長度，即3556微米。依本發明之實施例，金焊線26具有焊線接合工具或焊線機可為特定的最小焊墊開窗尺寸而提供之最大焊線長度。為電性連接接合墊21c與外部端子引腳14，中間端子13透過金焊線28焊線接合至外部端子引腳14。
應可理解，上述單一列之中間端子13的排佈或佈線僅用於例示目的，其不能視為本發明之範圍的限制。於另一實施例中，中間端子13可被排佈成兩列或更多列，或可被排佈成相互交錯的兩列。依本實施例，每一中間端子13所占用之接合面面積較每一外部端子引腳14所占用之接合面面積小，而外部端子引腳14具有與內部端子引腳12大體相同之接合面面積。
第2圖較佳地繪示了較小之中間端子13。舉例而言，每一內部端子引腳12與外部端子引腳14之尺寸可為270微米×270微米，而每一中間端子13之尺寸可為150微米×150微米。應可理解，每一中間端子13之接合面面積皆必須符合金焊線26與28之焊球(squash ball)的需求，上述焊球未於圖中明確繪示。
第3圖係依本發明另一實施例之外部端子引腳與中間端子連接之放大上視圖。如第3圖所示，第一列外部端子引腳14’透過走線15電性連接至中間端子13’，較遠之第二列外部端子引腳14”則透過金焊線28電性連接至中間端子13”。
第4-11圖係依本發明實施例之用於例示製作第1圖所示之具有中間端子之QFN半導體封裝之方法的剖面示意圖，其中相同之標號代表相同之區域、層或元件。如第4圖所示，提供銅載體40。圖案化光阻膜42a及42b分別形成於銅載體40之兩個相對面第一面40a及第二面40b之上，以於銅載體40上定義引腳陣列圖樣52及晶粒黏接墊圖樣54。
如第5圖所示，執行電鍍製程，以利用可接合金屬層62(例如鎳、金或其組合)填充銅載體40之兩個相對面上之引腳陣列圖樣52及晶粒黏接墊圖樣54。如第6圖所示，將圖案化光阻膜42a及42b剝離以露出銅載體40之表面的一部分。
如第7圖所示，接著執行銅蝕刻製程，以從第一面40a開始半蝕刻銅載體40之露出的部分。於第一面40a上形成凹區10a。於銅蝕刻製程中，可接合金屬層62可作為硬遮罩。依本實施例，第4至7圖所描述之步驟皆可於導線架製作廠完成。
如第8圖所示，半導體晶粒20黏著於凹區10a中，舉例而言，可利用表面黏著技術(Surface Mount technology,SMT)或其他適合的方法達成。半導體晶粒20具有頂面20a，頂面20a具有多個接合墊(未明確繪示)。
如第9圖所示，執行焊線接合製程，以分別透過金焊線22、24、26及28電性連接半導體晶粒20之頂面20a上的接合墊與對應之端子引腳。如前所述，焊線機於焊線接合製程中提供之最大焊線長度取決於半導體晶粒20上接合墊之最小焊墊開窗尺寸。舉例而言，對於具有最小焊墊開窗尺寸為43微米之接合墊而言，典型之焊線機僅可提供140密耳(3556微米)之最大焊線長度。依本實施例，金焊線26具有焊線接合工具或焊線機可為特定的最小焊墊開窗尺寸而提供之最大焊線長度。
如第10圖所示，執行塑模(molding)製程。金焊線22、24、26及28、半導體晶粒20以及銅載體40之第一面40a被封裝於膜套30中，膜套30是例如環氧樹脂(epoxy resin)。
如第11圖所示，於塑模製程之後，執行銅蝕刻製程以從第二面40b開始半蝕刻銅載體40上未被可接合金屬層62覆蓋之部分，從而形成晶粒黏接墊10、電源或接地環11、內部端子引腳12、中間端子13以及外部端子引腳14。依本實施例，電源或接地環11可與晶粒黏接墊10一並形成，且為環狀。電源或接地環11可為連續的或非連續的。晶粒黏接墊10、內部端子引腳12以及外部端子引腳14分別具有大體共面之暴露的底面10b、12b以及14b。暴露的底面10b、12b以及14b最終分別接合至印製電路板。中間端子13具有凹式底面13b，且凹式底面13b並不與暴露的底面10b、12b以及14b中任一者共面。依本實施例，第8至11圖所描述之步驟皆可於組裝廠或封裝廠完成。
第12圖係依本發明另一實施例之具有內部端子之QFN半導體封裝之剖面示意圖。如第12圖所示，圖中QFN半導體封裝1a與第1圖中QFN半導體封裝1之區別在於，第12圖之中間端子13的凹式底面13b被保護層70所覆蓋，例如膠黏劑(glue)或其他適合的絕緣材料，以防止與印製電路板之間發生短路。
以上所述僅為本發明之較佳實施例，舉凡熟悉本案之人士援依本發明之精神所做之等效變化與修飾，皆應涵蓋於後附之申請專利範圍內。
1、1a．．．QFN半導體封裝
10．．．晶粒黏接墊
10a．．．凹區
10b、12b、14b．．．暴露的底面
11．．．電源或接地環
12．．．內部端子引腳
13、13’、13”．．．中間端子
13b．．．凹式底面
14、14’、14”．．．外部端子引腳
20．．．半導體晶粒
15．．．走線
20a．．．頂面
21、21a、21b、21c．．．接合墊
22、24、26、28．．．金焊線
30．．．模套
40．．．銅載體
42a、42b．．．圖樣化光阻膜
52．．．引腳陣列圖樣
54．．．晶粒黏接墊圖樣
62．．．可接合金屬層
70．．．保護層
第1圖係依本發明實施例之具有中間端子之QFN半導體封裝之剖面示意圖。
第2圖係依本發明實施例之具有中間端子之QFN半導體封裝之佈線的上視圖。
第3圖係依本發明另一實施例之外部端子引腳與中間端子連接之放大上視圖。
第4-11圖係依本發明實施例之用於例示製作第1圖所示之QFN半導體封裝之方法的剖面示意圖。
第12圖係依本發明另一實施例之具有內部端子之QFN半導體封裝之剖面示意圖。
1a．．．QFN半導體封裝
10．．．晶粒黏接墊
10a．．．凹區
10b．．．暴露的底面
11．．．電源或接地環
12．．．內部端子引腳
13．．．中間端子
13b．．．凹式底面
14．．．外部端子引腳
20．．．半導體晶粒
20a．．．頂面
21．．．接合墊
22、24、26、28．．．金焊線
30．．．模套
42a、42b．．．圖樣化光阻膜
62．．．可接合金屬層
70．．．保護層

Claims (20)

  1. 一種四方扁平無引腳半導體封裝，包含：一晶粒黏接墊，具有一凹區；一半導體晶粒，安裝於該晶粒黏接墊之該凹區；至少一列內部端子引腳，位於靠近該晶粒黏接墊之位置；多個第一焊線，用於將該至少一列內部端子引腳分別焊接至該半導體晶粒；至少一列擴充的外部端子引腳，位於沿著該四方扁平無引腳半導體封裝外圍之位置；至少一列中間端子，位於該至少一列內部端子引腳與該至少一列擴充的外部端子引腳之間；多個第二焊線，用於將該至少一列中間端子分別焊接至該半導體晶粒；以及多個第三焊線，用於將該至少一列中間端子分別焊接至該至少一列擴充的外部端子引腳。
  2. 如申請專利範圍第1項所述之四方扁平無引腳半導體封裝，其中該至少一列擴充的外部端子引腳與該半導體晶粒之距離超過一最大焊線長度，該最大焊線長度對應於該半導體晶粒之一特定的最小焊墊開窗尺寸。
  3. 如申請專利範圍第2項所述之四方扁平無引腳半導體封裝，其中該特定的最小焊墊開窗尺寸為43微米，而該最大焊線長度為140密耳。
  4. 如申請專利範圍第1項所述之四方扁平無引腳半導體封裝，更包含一模套，用於封裝該半導體晶粒、該多個第一焊線、該多個第二焊線以及該多個第三焊線。
  5. 如申請專利範圍第1項所述之四方扁平無引腳半導體封裝，其中每一中間端子所占用之一接合面面積較每一擴充的外部端子引腳所占用之一接合面面積小。
  6. 如申請專利範圍第1項所述之四方扁平無引腳半導體封裝，其中每一中間端子具有一凹式底面，該凹式底面不與任一內部端子引腳之一底部接合面及任一擴充的外部端子引腳之一底部接合面共面。
  7. 如申請專利範圍第6項所述之四方扁平無引腳半導體封裝，其中該凹式底面被一保護層覆蓋。
  8. 一種四方扁平無引腳半導體封裝，包含：一晶粒黏接墊，具有一凹區；一半導體晶粒，安裝於該晶粒黏接墊之該凹區；至少一列內部端子引腳，位於靠近該晶粒黏接墊之位置：多個第一焊線，用於將該至少一列內部端子引腳分別焊接至該半導體晶粒；至少一列擴充的外部端子引腳，位於沿著該四方扁平無引腳半導體封裝外圍之位置；至少一列中間端子，位於該至少一列內部端子引腳與該至少一列擴充的外部端子引腳之間；多個第二焊線，用於將該至少一列中間端子分別焊接至該半導體晶粒；以及一走線，用於將該至少一列中間端子其中之一中間端子連接至該至少一列擴充的外部端子引腳其中之一擴充的外部端子引腳。
  9. 如申請專利範圍第8項所述之四方扁平無引腳半導體封裝，其中該至少一列擴充的外部端子引腳與該半導體晶粒之距離超過一最大焊線長度，該最大焊線長度對應於該半導體晶粒之一特定的最小焊墊開窗尺寸。
  10. 如申請專利範圍第9項所述之四方扁平無引腳半導體封裝，其中該特定的最小焊墊開窗尺寸為43微米，而該最大焊線長度為140密耳。
  11. 如申請專利範圍第8項所述之四方扁平無引腳半導體封裝，更包含一模套，用於封裝該半導體晶粒、該多個第一焊線以及該多個第二焊線。
  12. 如申請專利範圍第8項所述之四方扁平無引腳半導體封裝，其中每一中間端子所占用之一接合面面積較每一擴充的外部端子引腳所占用之一接合面面積小。
  13. 如申請專利範圍第8項所述之四方扁平無引腳半導體封裝，其中每一中間端子具有一凹式底面，該凹式底面不與任一內部端子引腳之一底部接合面及任一擴充的外部端子引腳之一底部接合面共面。
  14. 如申請專利範圍第13項所述之四方扁平無引腳半導體封裝，其中該凹式底面被一保護層覆蓋。
  15. 一種製作四方扁平無引腳半導體封裝的方法，包含：半蝕刻一載體之一第一面，以形成一引腳陣列之頂部以及一晶粒黏接墊之一晶粒黏接面，其中該引腳陣列包含至少一列內部端子引腳、至少一列擴充的外部端子引腳以及至少一列中間端子，該至少一列內部端子引腳位於靠近該晶粒黏接墊之位置，該至少一列擴充的外部端子引腳位於沿著該四方扁平無引腳半導體封裝外圍之位置，該至少一列中間端子位於該至少一列內部端子引腳與該至少一列擴充的外部端子引腳之間；將一半導體晶粒安裝於該晶粒黏接面；透過多個第一導體焊線將該半導體晶粒電性連接至該至少一列內部端子引腳之對應的多個端子引腳以及該至少一列中間端子之對應的多個端子；透過多個第二導體焊線將該至少一列中間端子之多個端子電性連接至該至少一列擴充的外部端子引腳之對應的多個端子引腳；利用一模套封裝該半導體晶粒、該多個第一導體焊線以及該多個第二導體焊線；以及半蝕刻該載體之與該第一面相對之一第二面，以形成該引腳陣列之底部以及該晶粒黏接墊。
  16. 如申請專利範圍第15項所述之製作四方扁平無引腳半導體封裝的方法，其中該至少一列擴充的外部端子引腳與該半導體晶粒之距離超過一最大焊線長度，該最大焊線長度係由一焊線機所提供且對應於該半導體晶粒之一特定的最小焊墊開窗尺寸。
  17. 如申請專利範圍第16項所述之製作四方扁平無引腳半導體封裝的方法，其中該特定的最小焊墊開窗尺寸為43微米，而該最大焊線長度為140密耳。
  18. 如申請專利範圍第15項所述之製作四方扁平無引腳半導體封裝的方法，其中每一中間端子所占用之一接合面面積較每一擴充的外部端子引腳所占用之一接合面面積小。
  19. 如申請專利範圍第15項所述之製作四方扁平無引腳半導體封裝的方法，其中每一中間端子具有一凹式底面，該凹式底面不與任一內部端子引腳之一底部接合面及任一擴充的外部端子引腳之一底部接合面共面。
  20. 如申請專利範圍第19項所述之製作四方扁平無引腳半導體封裝的方法，其中該凹式底面被一保護層覆蓋。
TW098115827A 2008-05-19 2009-05-13 四方扁平無引腳半導體封裝及其製作方法 TWI385763B (zh)

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CN102201388A (zh) 2011-09-28
US20090283882A1 (en) 2009-11-19
US8039933B2 (en) 2011-10-18
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CN102201386A (zh) 2011-09-28
US8044496B2 (en) 2011-10-25
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