TWI379400B - Integrated circuit packaging system with interposer - Google Patents

Integrated circuit packaging system with interposer Download PDF

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Publication number
TWI379400B
TWI379400B TW097102292A TW97102292A TWI379400B TW I379400 B TWI379400 B TW I379400B TW 097102292 A TW097102292 A TW 097102292A TW 97102292 A TW97102292 A TW 97102292A TW I379400 B TWI379400 B TW I379400B
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TW
Taiwan
Prior art keywords
integrated circuit
spacer
upper die
integrated
substrate
Prior art date
Application number
TW097102292A
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English (en)
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TW200834879A (en
Inventor
Philip Lyndon Cablao
Rachel Layda Abinan
Dario S Filoteo Jr
Allan P Ilagan
Original Assignee
Stats Chippac Ltd
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Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW200834879A publication Critical patent/TW200834879A/zh
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Publication of TWI379400B publication Critical patent/TWI379400B/zh

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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

1379400 九、發明說明： [相關申請案之交互參考] 本申請案包含共同申請之美國國專利申請案第 11/464,699號所相關之標的内容。該相關申請案讓渡级 STATS ChipPAC 公司。 又、口 【發明所屬之技術領域】 本發明大體上係關於積體電路封裝，而尤係關於用於 封裝系統級封裝件（System-in-Package)配置之系統。 【先前技術】 現今發現半導體，或積體電路（IC)，實際上用於每一 個製造之電性產品中。K不僅用於非常複雜之工業和商業 電子設備，而且亦用於許多家庭和消f者項目，馨如電視、 洗衣機和乾衣機、無線電、和電話。當產品變得較小' /更多的功能時’則需要包含更多的IC於較小的產品中以執 行功能。亦作用為相機、網際網路存取裝置、和音 鲁器之蜂巢式電話的縮小為如何結合入愈來愈小的電子 -而能力愈來愈強之一個例子。 σ° .之丰成本、高效能、更加縮小、和更高封裝密度 之+導體裂置的需要增加時，則發展出. (驗結構，以符合需要 ‘構具有安裝於單-積體電路封裝件内之許多個晶粒和^ 拉和其他的組件能夠以垂直方式、樺向古 式、或他們的組合方式安裝。 ”方 一個此種方法；^妝 α 為將一個晶粒疊置在另一個晶粒之上 94209 5 13/^400 面，然後將号r -¾ to 内。用於:有:二:晶粒包裝(enc1。叫在-個封裝件 諸曰… 半導體的最後封裝件遠小於由 所得到者。除了提供較小之尺寸外， 如容易處提供許多相關於製造封襄件之優點，譬 於®置之晶粒的配置中，血彳 或超音、丁始拉人 T 使用已熟知的熱壓縮 備，使晶粒連續地耦接。 g)0又 ^ ^ ^ _ 打綠接合製程期間，打線接人 裝置之頭部施加向下之壓 ° 拣接鎇夕道喷站 阳粒之打線接合墊保 接墊上’以鲜接或谭接該導線至該晶粒上之焊 而P-Γ ’相較於數個各具有單-晶粒之半導體 廉。能者’4置之晶粒能夠製造得較快速和較價 廉宜置之晶粒方法具有優點因為#挞、 因為其增加電路密度、增進 埋置之互連線之訊號品質、並絲成於㈣電路封 s雖然疊置之晶粒配置可以產生更有效的封 且令故障的組件而使得製程遭受到產率下降 件無法操作丄:所==可能造成整個封裝 f阻多的MCM結構需要附加譬如 。奋益、或電感器之積體被動裝置t
passive device，IPD)。 S 因此’需要保持積體電路封農系統，以可靠和經濟地 產糸統級封裝件（System也_Package，sip)裝置。於 對將額外的功能併入於較小封裝件中之持續的屢力，因此 對於找出這些問題之解決方法是愈來愈重要。有馨於持續 94209 6 1379400 增強之商業競爭壓力，連同成 於市場上有意義之產品差 ''者期望，和減少對 之解決方法是愈來愈重要：：，：此對於找出這些問題 率和性^古 此外’需要節省成本、改進效 u及克服競爭壓力， 問題之解決方法益加急迫。 策而要找出逆些 已長期尋求對於這些問題之解 未能夠教示或建議任何的解決之道，、仁疋先前的研發 之解決方本p且, 畔决之道’因此，對於這些問題 之解决方法已長期困擾著熟悉此項技術者。 【發明内容】 輕接=:種積體電路封裝系統，包含:形成具有 曰B ^件，將上晶粒固定於該間隔件上；安裝該間 隔件於積體電路之上；以及經由 、以 至該上晶粒。 二由該耦接槽耦接該積體電路 有=1=當之上述諸情況外，本發明之某些實施利具 ^他的U篆。熟習此項技術者由讀取下列之詳細說明並 φ > π所附圖式後，該等態樣將變得报清楚。 -【實施方式】 . 兹充分詳細說明下列之實施例以使熟悉此 夠製造和使用本發明。應了解到根據本揭示說㈣ 實施例將是很日請的，以及可做域理或機械改變而不合 悖離本發明之範圍。 θ 於下列說明中，提出了許多特定的詳細說明以提供對 j發明之完全了解。然而，很顯然的對於熟悉本技藝者而 言，可不必作如此詳細說明即能夠實施本發明。為7不致 94209 7 13/9400 吴糊了本：明焦點，-些已知的電路、系統配置、和處理 :T不予詳、田°兒明。同樣情況’顯示該系統實施例之各圖 式：：圖形的，並未按比例繪製，而尤其是一些尺寸是為 、月疋表示而於各圖式中予以非常誇大地顯示。此處揭示 明:多個實施例’具有一些共同的特徵，用來清楚和 容易例示、說明、和對其理解，彼此類似和相同的特徵通 常將以相同的參考數字說明。 鲁一」了說明之目的，此處所用之“水平的（horizon)” 一詞定義為平行於積體電路封裝絲板之平Φ或表面的平 面，而無關於其方向。“垂直的（vertical)，，一詞參考為垂 直於‘剛才所定義之水平的方向。相關於該水平面而定義譬 如在上方（above) ” 、 “在下方（below)，，、 “底部 (b〇tt〇m)”、“頂部（t0P)”、“側（side)，’（如於“侧壁，，）、 ^^*(higher)^ . ^^(lower)^ . (upper)» ^ 庄在…之上（over)” 、和“在…下面（under)”等詞彙。詞 #彙“在上面（0n)，，意指元件之間有直接接觸。詞彙“系統 (^ystem)”意指本發明之方法和裝置。此處所用之詞彙 .處理（pr〇cessmg)” 包含衝壓（stamping)、鍛造（forging)、 圖案化（patterning)、曝光、顯影（devel〇pmem)、蝕刻清 洗、和/或去除材料或雷射修飾，如形成所述結構所需要者。 茲參考第1圖，圖卡顯示於本發明之實施例中積體電 路封裝系統100之剖面圖。積體電路封裝系統1〇〇之剖面 圖描繪基板102,基板102具有組件側1〇4和連接侧1〇6。 連接墊108形成在基板1〇2之連接側。譬如錫球、金凸塊 94209 8 1379400 '⑽d bump)、錫凸塊⑽如以叫）、或錫柱腳⑽如_咖) 之系統互連接110連接至連接墊1〇8用來附接積體電路封 .，系統100至次級系統。位於組件側1 〇4上之焊接墊j j 2 .可以藉由内部連接114連接至連接墊ι〇8。 ^積體電路116(譬如覆晶積體電路）可藉由黏著劑 • 女裝於組件侧104上。具有連接凸塊12〇(譬如錫凸塊、 金凸塊、或錫柱腳）之第一積體㈣ιΐ6彳定位於第二積體 籲 22之周圍，第二積體電路122係藉由黏著劑118安 裝於組件側104上。具有輕接槽126之間隔件124電性連 接^連接凸塊120並藉由黏著劑118(譬如晶粒附接材料或 熱導電樹脂’)而安裝在第二積體電路122上。耦接槽⑶可 以是間隔件124之内部部分之開口。輕接槽m可以是各 办/狀仁疋有允許工具接近施加電性互連接之最小 第上晶粒i3〇(譬如覆晶積體電路）電性連接至間隔 件I24之表面，該表面係相對於連接至連接凸塊120之表 動裝置132(譬如電阻器、電容器、或電感器) 於第—上晶粒130之附近。第二上晶粒134(嬖如積 由黏著劑118而安裝於與積體被動裝置 好楚_同的表面。電性互連接128可經由耦接槽126而將 = 上晶粒134電性耦接至第二積體電路122。第二上 曰曰粒134亦可㈣至基板1Ό2之組件側電性互連接 亦可將該基板102之纪件側1 04連接至第一上晶粒130 或第一上晶粒134之附近之間隔件124。 94209 9 譬如環氧樹脂槿赞化入从^ 成在基板Π)2之组^ η 型蓋（m〇ld CaP)136形 "、牛側104上。模型芸1 電路116、第二積體電路122、第 封裝弟一積體 粒134、積體被第—上晶粒130、第二上晶 可具有至广2m::電性互連接128。模型蓋136 .2 mm轭圍之厚度。 茲參考第2圖，ΐφ屋g-#丄 之上#圖，^ _ 於本實施例中間隔件配件200 細之上視_會間隔件124槽126。間隔件配件 部分。焊接塾2〇2配 :接槽126位於該内部 的周 在間隔件U4和耦接槽126之邊緣 二：曰J 一上晶粒130連接鄰近積體被動裝置132。第 制立m藉由黏著齊J 118而安裳在轉接槽126之另一 侧。積體被動裝置132連接至組件墊2〇4。 發現到間隔件124可以用笛,B . # 晶粒130、積體被動 、 和苐—上晶粒⑽在前面組合，並且在組合次 ^封農件之前測試適當的操作4種能力提供增加製造 因此提供減少完成產品之成本。上述例子表示第一上 曰曰粒130和第一上晶粒j34輕接到間隔件124，但是了解 到任何數目個上晶粒可以麵接到間隔件124。以及討論了 單一單元之積體被動裝^ 132,但是可以有任何數目和思 用之積體被動裝置132。 兹參照第3圖，其中顯示了本發明之替代實施例之積 體電路封裝系統300之剖面圖。積體電路封裝系統3〇〇之 剖面圖描繪安裝在基板102之組件側1〇4上之第一積體電 路〗】6。藉由黏著劑118將譬如覆晶積體電路之第二積體 94209 10 毛路302女裝至組件側1()4。第二積體電路逝之連接凸 塊120可以電性連接至間隔件124之底表面。額外的訊號 可以藉由附加電性互連接128穿過純槽126而連接於第 ，體宅路302與間隔件124、積體被動裝置132、或第二 上曰曰粒134之頂表面之間。模型蓋136形成於基板^ 組件側104之上。 一 、第4圖，其中顯示了於本發明之另一替代實施 ’i之積體電路封裝系統侧之剖面圖。積體電路封裝系統 之剖面圖描緣具有第一積體電路402之基板1()2,第一 積體電路402藉由| τ。h _ 由黏者知丨118女裝至組件側104。第二積 體電路404藉由黏著齊H18 $裝接近該第一積體電路 。間隔件4〇6藉由黏著齊】ιΐ8而安裝於第一積體電路 I02和第二積體電路_之上。間隔件偏具有第-純 θ 408 U接槽41G·、和第三耦接槽412。 日日粒130可經由覆晶附著（flip chip attach)而連 接至間隔件406。第-上a扮— •—弘 乐一上日日粒134可以藉由黏著劑118而 於間件406 。可以使用電性互連接—將第二上
-:粒134經由第：輕接槽㈣轉接至第：積體電路綱。 弟一上晶粒13 4亦能夠婉由筮-如“ I 1ΛΟ 此列，，·工由弟二耦接槽412連接至基板 !〇2之組件側1〇4。 妓 > 第5圖’其中顯示了於本發明之替代實施例之 :有複數個_之間隔件配件5〇〇之上視圖。間隔件配 500之上視圖描.繪間隔件4〇6具有複數個耦接槽“ο位 ;該内部部分。焊接墊2〇2配置在間隔件傷之邊緣的周 94209 11 1379400 .- % .圍，以及環繞著苐-輕接槽偏、第二轉接槽4i〇 耦接槽412。 * 第一上晶粒130電性連接至第一耦接槽408盥第二耦 .接槽410之間之間隔件_。藉由黏著劑118將第二上晶 粒134女裝於第二麵接槽41〇與第三麵接槽化之間之間 -隔件406上。複數個積體被動裝置132可以電性連接至裝 设在間隔件406之周圍之組件墊204。 籲 兹參照第6圖，其中顯示了積體電路封裝系統⑽於 乂造電性輕接階段之部分_之放大剖面圖。部分6⑼之 放大剖面圖描缘具有位於第一積體電路晶粒4〇2和第二積 體電路晶粒404之間在組件侧1〇4上之焊接塾ιΐ2之基板 =2。間隔件406藉由黏著劑m而絲在第一積體電路晶 粒402和第二積體電路晶粒4〇4上。第二上晶粒"A藉由 黏著劑118而安裝於間隔件4〇6之頂部。 耦接毛細管（c〇upling capillary)6〇2安褒在焊接機器 # 604上^耦接毛細管6〇2之形狀允許其用熱或超音波方式 穿達第三耦接槽412以將電性互連接128焊接至焊揍墊 -112。電性互連接128之另一端可以谭接至在間隔件_ 上的焊接墊202、第二上晶粒134、或其組合。應了解到上 f狀態之實施焊接為一個例子而叙接毛細f⑽彳以用來 焊接電性互連接128至可接近之任何的焊接墊丨〗〕。 第三耦接槽412之尺寸可假設任何形狀，但是第三輕 接槽412之最小寬度可由公式】計算。
Wniin^ 2((Tan Θ )(H+ WH)-f TW) ⑴ 94209 12 1379400 此處wmin為第三輕接槽412之最小寬度，角 毛細管術之圓錐角，Η為從谭接塾112之表面至間= 4〇6之頂表面之距離，觀為從間隔件4()6之頂表面: 接，202上之附接點橫掃過間隔件4〇6之角落所需之= f间度，以及TW為該福接毛細管之尖端的寬度。而 言，福接毛細管602具有麵之尖端寬度和20。之 Θ，達成結合〇.6mm之高度和需要的〇.25mm導線 度以清除間隔件之角落，將允許如下式所示、’： ⑴ I = 2(伽 2〇。）(〇.6 + 〇.25) + L ⑽ _ 於前面例子中，結合高度（Η)包含組件側！ 〇 4上 劑118之厚度、第一積體電路4〇2之厚度、第一 與間隔件406之間之黏著劑118之厚度、和間隔件_ 之厚度。使用於此範例的數值係在這些組件的現行製造標 準内 兹參照第7圖，其中顯示於本發明之又另一 =體電路封裝系統之剖面圖。積體電路封裳系： 之4面圖描繪具有組件側1〇4和連接側1〇6之美 ⑽。連接塾108形成在基板1〇2之連接側上。系統^接 110U如锡球、金凸塊、錫凸塊、或錫柱腳）係連接至連接 塾⑽用來附接積體電路封裝系統100至次級系統。位於 在組件側104上之焊接墊112可以藉由内部連接114接 至連接墊108。 接 第—積體電路7〇2(譬如覆晶積體電路）可藉由黏著劑 94209 13 1379400 女裝於，.且件们04上。具有連接凸塊1 金凸塊、或錫柱腳）之第一 ^如錫凸塊、
疋位於組件側1〇4之中央。具者d 1]S 電性連接至輕接於第福接才曰126之間隔件124 電路702之連接凸塊120,祐 女裝在鹌接於組件側1〇4第_ 並 ^ g 弟一組之連接凸塊120上。耦 接槽126可以疋間隔件124 可以异夂鍤π此 内#邛刀之開口。耦接槽126 了 乂疋各㈣狀’但是有允許1具接 128之最小寬度。 电『生互連接 體電路704(譬如覆晶積體電路)可 弟-積體電路702之暴露接觸墊(未圖示)。馨 之黏著材料7〇6支禮第二積體電 第一積體電路704位於間隔件124之㈣槽126 :。搞接槽！26可以寬到足夠允許放置第二積體電^ 7〇4 ^附接電性互連接128於間隔件124之頂表面 電路702之表面之間。 積體 94209 14 1379400 ·*» ， 上晶粒134之附近之間隔件】24。 第五積體電路708可以安裝在第二積體電路7〇4之頂 •部。可以使用黏著劑U8來安裝第五積體電路708以及可 -以使用電性互連接128而將第五積體電路708耦接至間隔 件124、第-積體電路702、組件侧1〇4、或他們的組合。 譬如環氧樹脂模製化合物之模型蓋136形成在基板 102之組件側104上。模型蓋136封裝第—積體電路7〇2、 •第二積體電路704、第一上晶粒13〇、第二上晶粒134、積 •體被動裝置I32、第五積體電路708、和 模型蓋Π6可具有…心^随範圍^^1^ 茲參照第8圖，其中顯示於本發明之又另一替代實施 例之加強型球閘格陣列（enhanced ball gdd an#， 封褒件800之剖面圖。加強型球閘格陣列（ebga)封裝件 800之剖面圖描繪譬如散熱器之蓋子8〇2，蓋子8〇2具有藉 由黏著劑118來安裝之第一積體電路8〇4。第一積體電路 籲804可以是具有連接凸塊12〇之覆晶積體電路晶粒。加強 •型球閘格陣列（EBGA)基板806環繞著第-積體電路8〇4。 -EBGA基板806具有第一層訊號線跡8〇8和第一 跡，。咖A基板806形成設有具第一層訊號二= 之暴路#分之第一步階812和具第二層訊號線跡810之暴 露部分之第二步階814之凹處。 、 ，隔件124可以耦接到第一積體電路8〇4之連接凸塊 _错由連接電性互連接128穿過第一積體電路804和間 隔件124之頂表面之間之耦接槽126而提供進一步之訊號 94209 15 1379400 * 互連接。電性互連接128亦可耦接於間隔件124之頂表面、 第一層訊號線跡808、和該第二層訊號線跡之間。 • 間隔件124承載第一上晶粒130、積體被動裝置132、 ， 和弟一上晶粒134。第二上晶粒134可以電性連接至第一 積體電路804、第一層訊號線跡808、該第二層訊號線跡、 間隔件124之頂表面、或他們的組合。模型蓋136封裝第 • 一積體電路804、間隔件124、第一上晶粒13〇、積體被動 鲁裝置132、第二上晶粒134、電性互連接128、第一步階812 和第二步階814。系統互連接11〇耦接至系統墊816用來 連接至次一級系統，譬如印刷電路板（未圖示）。 從參照第9圖，其中顯示用來製造本發明之實施例之 具有間隔件124之積體電路封裝系統1〇〇之積體電路封裝 系統900之流程圖。系統9〇〇包含於方塊9〇2中形成具有 耦接槽之間隔件；於方塊9〇4中..固定上晶粒於該間隔件 上；於方塊906中安裝該間隔件於積體電路之上；以及於 籲方塊9G8中穿過該搞接槽麵接該積體電路至該上晶粒。 ' 本發明之童要態樣係有價值地支援和服務降低成本、 .簡化系統、和增加效能之歷史傾向。本發明之這些和苴他 有價值之方面結果促進了至少至次一級之技術狀態/、 因此發現到本發明之具有間隔件之積體電路封裝系 統提供重要的和迄今未知和未可獲得的解決方法、能力、 和功能方面用來提供先前不可能之低成本和高產量之系统 級封裝件解決方法。所得到之處理和配置係明確的、有效 成本的、不複雜的、高度多樣和有效的，能夠藉由調適已 94209 16 1379400 ，知之技術而出人意外地和非顯而易知地執行，並且 易適合有效和價廉地製造完全與習.知製程和技術相= 裝系統級封裝件。所得到之處理和配置係明確的、= 本的、不複雜的、高度多樣的、正確的、靈敏的、和2 的，並且能夠藉由調適已知的址件用來 ^ _價地製造、應用、和使用。 另双和廉 •雖然本發明已結合特定之最佳實施模式而作了說 應了解到對於熟習此技藝者而言，麵於上述之 後，可了解該實施例可作許多之替換、修飾 本發明將包含所有落於所包含之申請專利範圍因此」 圍内之此等的替換、修飾和改變。此 二和季已 附圖式中所顯示之所有内容係將作°曰所提出和所 來限制本發^ 將作例而並非欲用 【圖式簡單說明】 ’圖’·第1圖為本發明之實施例之積體電路封裝系統之剖面 隔件配 第2圖為本發明之實施例之具有該耦接 件之上視圖； ^ 第3圖為於本發明之替代實施 之剖面圖； ’例之積體電路封裝系統 系统=面圖圖為於本發明之另一替代實施例之積趙電路封裝 之心:::=替代實施例之具有複數個_ 94209 17 •八第6圖為積體電路封裝系統於製造電性耦接階段之 为之放大剖面圖； 。丨 第7圖為於本發明之又另—替代實施例之積體電路封 哀糸統之剖面圖； 弟8圖為於本發明之又另—替代實施例之加強型球問 ' 。陣列封裝件之剖面圖；以及 • 帛9圖為用於製造本發明之實施例之積體電路封裝系 統之積體電路封裝系統之流程圖。 【主要元件符號說明】 106 110 114 116 118 122 124 128 132 136 204 410 500 連接側 系統互連接 内部連接 402、702第一積體電路 :、3〇0、4〇0、700 ' 900積體電路封裝系統 102、806基板 1〇4組件側 108 112 120 連接塾 2Q2 焊接墊 連接凸塊 積體電路 126耦接槽 130 第一上晶粒 134 第二上晶粒 〇〇 間隔件配件 408第—耦接槽 412 第三麵接槽 黏著劑 302、404、704 第 4〇5間隔件 電性互連接 積體被動裝置 模型蓋（mold cap) 組件墊 苐一搞接槽 具有複數個純槽之間隔件配； 94209 1379400 • 600 積體電路封裝系統於製造電性耦接階段的部分 602 耦接毛細管 604 焊接機器 706 黏著材料 708 第五積體電路 800 加強型球閘格陣列封裝件 802 蓋子 804 第一積體電路 808、810 第一層訊號線跡 812 第一步階 814 第二步階 816 系統墊 902、904、906、908 方塊 19 94209

Claims (1)

1379400
申請專利範圍： 種製造積體電路封裝系統之方法，包括： 形成具有耦接槽之間隔件 固疋上晶粒於該間隔件上； 提供基板，該基板具有在組件側上之積體電路盘在 連接側上之系統互連接’包含安裝該間隔件於該積體電 路之上；以及 傾跽电 2. 3. 耦接該積體電路穿過該轉接槽至該上晶粒。 如申請專利範圍第1項所述之方法，復包括： 安裝第二積體電路於該基板上；以及 電f生連接δ亥第一積體電路至該間隔件。 如申請專利範圍第1項所述之方法，復包括 固定第二上晶粒於該間隔件上.； 耦接積體被動裝置至該間隔件；以及
電性連接m該第二上晶粒、該積體被動裝 或他們的組合至該積體電路。 4. 如申請專·圍第1項所述之方法，其中，純該積體 電路至該上晶粒包含焊接電性互連接。 5. 如申請專利範圍第j項所述之方法，復包括： 提供具有訊號線跡於步階之加強型球閘格陣列基 板； 安裝該積體電路鄰接於談步階； 安裝該間隔件於該步階之上；以及 電性連接該積體電路穿過該間隔件至該訊號線跡。 94209修正版 20 ^ moo 第97102292號專利申請案 100年12月20日修正替換頁' 卜日修正替換I 6.—種積體電路封 間隔件，該間隔件具有耦接槽； 上晶粒’該上晶粒位於該間隔件上； 基板，該基板具有在組件侧上之積體電路與在連接 側上之系統互連接，包含於該積體電路之上之該間隔 件；以及 該積體電路穿過該耦接槽耦接至該上晶粒。 7. 如申請專利範圍第6項所述之系統，復包括： 第二積體電路，該第二積體電路位於該基板上；以 及 該第二積體電路電性連接至該間隔件。 8. 如申請專利範圍第6項所述之系統，復包括： 第二上晶粒，該第二上晶粒位於該間隔件上； 積體被動裝置，該積體被動裝置耦接至該間隔件； 以及 »亥上BB粒、5亥第一上晶粒、該積體被動襄置、或其 組合電性連接至該積體電路。 9. 如申請專利範圍第6項所述之系統，其中，耦接至該上 .晶粒之該積體電路包含嬋接至該積體電路之電性互連 接。 10·如申請專利範圍第6項所述之系統，復包括： 加強型球閘格陣列基板，該加強型球閘格陣列基板 具有訊號線跡於步階中； 該積體電路安裝鄰接於該步階； 94209修正版 21 1379400 ~年吲'^修正替換頁 第97102292號專利申請案 100年12月20日修正替換頁 該間隔件安裝於該步階之上；以及 該積體電路電性連接穿過該間隔件至該訊號線跡。 22 94209修正版
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