JP4594419B2 - 半導体装置及び半導体装置の接続確認方法 - Google Patents
半導体装置及び半導体装置の接続確認方法 Download PDFInfo
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Description
ちなみに、特許文献1には、POPにおける接続良否判定方法が開示されている。
すなわち、上側ソケット110の測定ピン111と半導体装置aの第1のランド210との位置合わせ、及び下側ソケット120の測定ピン121と半導体装置aの半田ボール213との位置合わせを行う必要がある。このとき、図5に示すように、上側ソケット110の位置合わせの精度を欠くと、当該パッケージ基板2における第1のランド210の周辺領域を損傷させる虞がある。
また、各測定ピンとの電気的接続がうまく取れないなど何らかの理由により複数回の測定を行う場合、第1のランド210に複数回、測定ピン111の先端部が接触して、当該第1のランド210が損傷する虞がある。
本実施形態では、半導体チップ3をパッケージ基板2の上面に搭載したが、この限りでない。半導体チップ3をパッケージ基板2の内部に搭載しても良い。また、半導体チップ3をパッケージ基板2の下面に搭載しても良い。
本実施形態では、パッケージ基板2の第1の主面を上面とし、第2の主面を下面としたが、逆の構成でも良い。
2 パッケージ基板
3 半導体チップ
5 樹脂封止材
30 半田ボール
40 半田ボール
100 接続確認装置
110 上側ソケット、111 測定ピン
120 下側ソケット、121 測定ピン
200 チップ接続用ランド
201 ランド
202 接続配線
203 半田ボール
210 第1のランド
211 第2のランド
212 接続配線
213(a) 半田ボール(第1の接続端子)
220 第3のランド
221 分岐配線
222 半田ボール(第2の接続端子)
Q 象限
X、Y 直交する二軸
Claims (8)
- パッケージ基板と、
前記パッケージ基板に搭載された半導体チップと、
前記パッケージ基板の第1の主面に形成された第1のランドと、
前記パッケージ基板の第2の主面に形成された第2のランドと、
前記第2のランドに接続され、前記半導体チップを介して前記第2のランドとの接続が確認できない第1の接続端子と、
前記第1のランドと前記第2のランドとを接続する接続配線と、
前記パッケージ基板の第2の主面に形成された第2の接続端子と、
前記接続配線と前記第2の接続端子とを接続する分岐配線と、
を備えた半導体装置。 - 前記第1及び第2の接続端子は半田ボールであることを特徴とする請求項1に記載の半導体装置。
- 前記第2の接続端子は、前記パッケージ基板の空き領域に配置されることを特徴とする請求項1又は2に記載の半導体装置。
- 前記第2の接続端子は、前記第1の接続端子と同一象限内に配置されることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記半導体チップは、前記パッケージ基板の第1の主面に搭載されることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップは、前記パッケージ基板の内部に搭載されることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップは、前記パッケージ基板の第2の主面に搭載されることを特徴とする請求項1に記載の半導体装置。
- パッケージ基板と、
前記パッケージ基板に搭載された半導体チップと、
前記パッケージ基板の第1の主面に形成された第1のランドと、
前記パッケージ基板の第2の主面に形成された第2のランドと、
前記第2のランドに接続され、前記半導体チップを介して前記第2のランドとの接続が確認できない第1の接続端子と、
前記第1のランドと前記第2のランドとを接続する接続配線と、
前記パッケージ基板の第2の主面に形成された第2の接続端子と、
前記接続配線と前記第2の接続端子とを接続する分岐配線と、
を備えた半導体装置を構成し、
前記第1の接続端子又は前記第2の接続端子の一方に電圧又は電流を印加し、前記第1の接続端子と前記第2の接続端子との間の抵抗値を計測する半導体装置の接続確認方法。
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US12/591,424 US8421206B2 (en) | 2008-11-27 | 2009-11-19 | Semiconductor device and connection checking method for semiconductor device |
US13/716,341 US9041185B2 (en) | 2008-11-27 | 2012-12-17 | Semiconductor device and connection checking method for semiconductor device |
US14/689,736 US9502385B2 (en) | 2008-11-27 | 2015-04-17 | Semiconductor device and connection checking method for semiconductor device |
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JPH11163194A (ja) * | 1997-11-26 | 1999-06-18 | Oki Electric Ind Co Ltd | Vlsiパッケージ |
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US7390700B2 (en) * | 2006-04-07 | 2008-06-24 | Texas Instruments Incorporated | Packaged system of semiconductor chips having a semiconductor interposer |
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