TWI378519B - - Google Patents

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Publication number
TWI378519B
TWI378519B TW097131903A TW97131903A TWI378519B TW I378519 B TWI378519 B TW I378519B TW 097131903 A TW097131903 A TW 097131903A TW 97131903 A TW97131903 A TW 97131903A TW I378519 B TWI378519 B TW I378519B
Authority
TW
Taiwan
Prior art keywords
layer
wiring
insulating film
semiconductor
semiconductor device
Prior art date
Application number
TW097131903A
Other languages
English (en)
Chinese (zh)
Other versions
TW200917395A (en
Inventor
Hiroyasu Jobetto
Original Assignee
Teramikros Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teramikros Inc filed Critical Teramikros Inc
Publication of TW200917395A publication Critical patent/TW200917395A/zh
Application granted granted Critical
Publication of TWI378519B publication Critical patent/TWI378519B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
TW097131903A 2007-08-24 2008-08-21 Semiconductor device and manufacturing method thereof TW200917395A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007217876A JP4752825B2 (ja) 2007-08-24 2007-08-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200917395A TW200917395A (en) 2009-04-16
TWI378519B true TWI378519B (enExample) 2012-12-01

Family

ID=40340690

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097131903A TW200917395A (en) 2007-08-24 2008-08-21 Semiconductor device and manufacturing method thereof

Country Status (6)

Country Link
US (2) US7727862B2 (enExample)
JP (1) JP4752825B2 (enExample)
KR (1) KR101167384B1 (enExample)
CN (1) CN101785106B (enExample)
TW (1) TW200917395A (enExample)
WO (1) WO2009028578A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI465171B (zh) * 2012-12-21 2014-12-11 臻鼎科技股份有限公司 承載電路板、承載電路板的製作方法及封裝結構

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2244288A4 (en) * 2008-02-14 2011-11-02 Mitsubishi Heavy Ind Ltd SEMICONDUCTOR ELEMENT MODULE AND METHOD FOR THE PRODUCTION THEREOF
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US9570376B2 (en) 2010-06-29 2017-02-14 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US8653670B2 (en) * 2010-06-29 2014-02-18 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
DE112012006469B4 (de) 2012-06-08 2022-05-05 Intel Corporation Mikroelektronisches Gehäuse mit nicht komplanaren gekapselten mikroelektronischen Bauelementen und einer Aufbauschicht ohne Kontaktierhügel
US8853058B2 (en) * 2012-06-22 2014-10-07 Freescale Semiconductor, Inc. Method of making surface mount stacked semiconductor devices
US8836094B1 (en) * 2013-03-14 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package device including an opening in a flexible substrate and methods of forming the same
JP6695066B2 (ja) * 2014-11-27 2020-05-20 ツーハイ アクセス セミコンダクター カンパニー リミテッド フレームがコンデンサと直列に少なくとも１個のビアを備えるようなチップ用のポリマーフレーム
US10276467B2 (en) 2016-03-25 2019-04-30 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10068855B2 (en) * 2016-09-12 2018-09-04 Samsung Electro-Mechanics Co., Ltd. Semiconductor package, method of manufacturing the same, and electronic device module
WO2018096830A1 (ja) * 2016-11-28 2018-05-31 株式会社村田製作所 電子部品及びその製造方法
CN110050338B (zh) 2016-12-07 2023-02-28 株式会社村田制作所 电子部件及其制造方法
CN110036472A (zh) * 2016-12-08 2019-07-19 日立化成株式会社 半导体装置的制造方法
KR102540829B1 (ko) * 2018-10-05 2023-06-08 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
KR102568705B1 (ko) * 2018-10-05 2023-08-22 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
US10818569B2 (en) 2018-12-04 2020-10-27 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and a method of manufacturing a semiconductor device
KR102586072B1 (ko) * 2019-05-21 2023-10-05 삼성전기주식회사 반도체 패키지 및 이를 포함하는 안테나 모듈
CN113555326A (zh) * 2021-06-03 2021-10-26 珠海越亚半导体股份有限公司 可润湿侧面的封装结构与其制作方法及垂直封装模块
US12362255B2 (en) 2021-08-26 2025-07-15 Micron Technology, Inc. Apparatus including direct-contact heat paths and methods of manufacturing the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5824019B2 (ja) * 1979-06-15 1983-05-18 松下電器産業株式会社 電子回路装置の製造方法
JP3346320B2 (ja) 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
JP3813402B2 (ja) * 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
US6492252B1 (en) * 2000-10-13 2002-12-10 Bridge Semiconductor Corporation Method of connecting a bumped conductive trace to a semiconductor chip
TW511415B (en) 2001-01-19 2002-11-21 Matsushita Electric Industrial Co Ltd Component built-in module and its manufacturing method
TW550997B (en) * 2001-10-18 2003-09-01 Matsushita Electric Industrial Co Ltd Module with built-in components and the manufacturing method thereof
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
JP2004023218A (ja) * 2002-06-13 2004-01-22 Matsushita Electric Ind Co Ltd 電話装置
JP3888267B2 (ja) * 2002-08-30 2007-02-28 カシオ計算機株式会社 半導体装置およびその製造方法
CA2464078C (en) 2002-08-09 2010-01-26 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
EP1636842B1 (en) * 2003-06-03 2011-08-17 Casio Computer Co., Ltd. Stackable semiconductor device and method of manufacturing the same
JP2005191157A (ja) * 2003-12-25 2005-07-14 Casio Comput Co Ltd 半導体装置およびその製造方法
US7489032B2 (en) * 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
JP4055717B2 (ja) 2004-01-27 2008-03-05 カシオ計算機株式会社 半導体装置およびその製造方法
JP4398305B2 (ja) * 2004-06-02 2010-01-13 カシオ計算機株式会社 半導体装置およびその製造方法
US7459340B2 (en) * 2004-12-14 2008-12-02 Casio Computer Co., Ltd. Semiconductor device and manufacturing method thereof
JP4870501B2 (ja) * 2005-09-13 2012-02-08 新光電気工業株式会社 電子部品内蔵基板の製造方法
US20070080458A1 (en) * 2005-10-11 2007-04-12 Tsuyoshi Ogawa Hybrid module and method of manufacturing the same
JP5065586B2 (ja) * 2005-10-18 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI465171B (zh) * 2012-12-21 2014-12-11 臻鼎科技股份有限公司 承載電路板、承載電路板的製作方法及封裝結構

Also Published As

Publication number Publication date
US8063490B2 (en) 2011-11-22
CN101785106A (zh) 2010-07-21
US20100193938A1 (en) 2010-08-05
TW200917395A (en) 2009-04-16
KR101167384B1 (ko) 2012-07-19
JP4752825B2 (ja) 2011-08-17
WO2009028578A8 (en) 2009-11-26
JP2009054666A (ja) 2009-03-12
US7727862B2 (en) 2010-06-01
WO2009028578A2 (en) 2009-03-05
CN101785106B (zh) 2012-05-30
KR20100038232A (ko) 2010-04-13
US20090051038A1 (en) 2009-02-26
WO2009028578A3 (en) 2009-05-14

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