TWI345298B - Stacked integrated circuit package-in-package system - Google Patents

Stacked integrated circuit package-in-package system Download PDF

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Publication number
TWI345298B
TWI345298B TW096146010A TW96146010A TWI345298B TW I345298 B TWI345298 B TW I345298B TW 096146010 A TW096146010 A TW 096146010A TW 96146010 A TW96146010 A TW 96146010A TW I345298 B TWI345298 B TW I345298B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
package
opening
interconnect
internal interconnect
Prior art date
Application number
TW096146010A
Other languages
English (en)
Chinese (zh)
Other versions
TW200834873A (en
Inventor
Ki Youn Jang
Jong-Woo Ha
Jong Wook Ju
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW200834873A publication Critical patent/TW200834873A/zh
Application granted granted Critical
Publication of TWI345298B publication Critical patent/TWI345298B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
TW096146010A 2006-12-09 2007-12-04 Stacked integrated circuit package-in-package system TWI345298B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/608,827 US7772683B2 (en) 2006-12-09 2006-12-09 Stacked integrated circuit package-in-package system

Publications (2)

Publication Number Publication Date
TW200834873A TW200834873A (en) 2008-08-16
TWI345298B true TWI345298B (en) 2011-07-11

Family

ID=39497000

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096146010A TWI345298B (en) 2006-12-09 2007-12-04 Stacked integrated circuit package-in-package system

Country Status (4)

Country Link
US (1) US7772683B2 (https=)
JP (2) JP4947656B2 (https=)
KR (1) KR101454883B1 (https=)
TW (1) TWI345298B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI690042B (zh) * 2018-02-01 2020-04-01 美商谷歌有限責任公司 用於保護半導體晶粒之封裝加強件

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US7746656B2 (en) * 2005-05-16 2010-06-29 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
US7518224B2 (en) * 2005-05-16 2009-04-14 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
US7622333B2 (en) * 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US7645638B2 (en) * 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
US8432026B2 (en) * 2006-08-04 2013-04-30 Stats Chippac Ltd. Stackable multi-chip package system
US8642383B2 (en) * 2006-09-28 2014-02-04 Stats Chippac Ltd. Dual-die package structure having dies externally and simultaneously connected via bump electrodes and bond wires
US7759783B2 (en) * 2006-12-07 2010-07-20 Stats Chippac Ltd. Integrated circuit package system employing thin profile techniques
US7635913B2 (en) * 2006-12-09 2009-12-22 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US8304874B2 (en) * 2006-12-09 2012-11-06 Stats Chippac Ltd. Stackable integrated circuit package system
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US8163600B2 (en) * 2006-12-28 2012-04-24 Stats Chippac Ltd. Bridge stack integrated circuit package-on-package system
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US7683469B2 (en) * 2008-05-30 2010-03-23 Stats Chippac Ltd. Package-on-package system with heat spreader
US8310061B2 (en) * 2008-12-17 2012-11-13 Qualcomm Incorporated Stacked die parallel plate capacitor
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
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US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
KR101118711B1 (ko) 2010-12-17 2012-03-12 테세라, 인코포레이티드 중앙 콘택을 구비한 적층형 마이크로전자 조립체
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8338963B2 (en) 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US8304881B1 (en) 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
KR20150046117A (ko) * 2012-08-23 2015-04-29 피에스5 뤽스코 에스.에이.알.엘. 장치 및 그 제조 방법
WO2014167871A1 (ja) * 2013-04-10 2014-10-16 株式会社村田製作所 半導体装置
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9871007B2 (en) * 2015-09-25 2018-01-16 Intel Corporation Packaged integrated circuit device with cantilever structure
KR102556518B1 (ko) * 2018-10-18 2023-07-18 에스케이하이닉스 주식회사 상부 칩 스택을 지지하는 서포팅 블록을 포함하는 반도체 패키지
US11495505B2 (en) 2019-06-03 2022-11-08 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
US11398455B2 (en) * 2019-06-03 2022-07-26 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
KR102767617B1 (ko) * 2019-08-12 2025-02-17 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR20230164794A (ko) 2022-05-25 2023-12-05 삼성전자주식회사 반도체 패키지

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI690042B (zh) * 2018-02-01 2020-04-01 美商谷歌有限責任公司 用於保護半導體晶粒之封裝加強件

Also Published As

Publication number Publication date
US20080136006A1 (en) 2008-06-12
JP2008147669A (ja) 2008-06-26
JP2012064983A (ja) 2012-03-29
TW200834873A (en) 2008-08-16
US7772683B2 (en) 2010-08-10
KR20080053233A (ko) 2008-06-12
JP5397964B2 (ja) 2014-01-22
KR101454883B1 (ko) 2014-10-28
JP4947656B2 (ja) 2012-06-06

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