JP4947656B2 - 積重ねられた集積回路パッケージインパッケージシステムおよびその製造方法 - Google Patents

積重ねられた集積回路パッケージインパッケージシステムおよびその製造方法 Download PDF

Info

Publication number
JP4947656B2
JP4947656B2 JP2007317306A JP2007317306A JP4947656B2 JP 4947656 B2 JP4947656 B2 JP 4947656B2 JP 2007317306 A JP2007317306 A JP 2007317306A JP 2007317306 A JP2007317306 A JP 2007317306A JP 4947656 B2 JP4947656 B2 JP 4947656B2
Authority
JP
Japan
Prior art keywords
integrated circuit
package
recess
stacked
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007317306A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008147669A (ja
JP2008147669A5 (https=
Inventor
キ・ヨン・ジャン
ジョン−ウー・ハ
ジョン・ウォーク・ジュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Publication of JP2008147669A publication Critical patent/JP2008147669A/ja
Publication of JP2008147669A5 publication Critical patent/JP2008147669A5/ja
Application granted granted Critical
Publication of JP4947656B2 publication Critical patent/JP4947656B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2007317306A 2006-12-09 2007-12-07 積重ねられた集積回路パッケージインパッケージシステムおよびその製造方法 Active JP4947656B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/608,827 US7772683B2 (en) 2006-12-09 2006-12-09 Stacked integrated circuit package-in-package system
US11/608,827 2006-12-09

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011285712A Division JP5397964B2 (ja) 2006-12-09 2011-12-27 積み重ねられた集積回路パッケージインパッケージシステムおよびその製造方法

Publications (3)

Publication Number Publication Date
JP2008147669A JP2008147669A (ja) 2008-06-26
JP2008147669A5 JP2008147669A5 (https=) 2011-01-27
JP4947656B2 true JP4947656B2 (ja) 2012-06-06

Family

ID=39497000

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2007317306A Active JP4947656B2 (ja) 2006-12-09 2007-12-07 積重ねられた集積回路パッケージインパッケージシステムおよびその製造方法
JP2011285712A Active JP5397964B2 (ja) 2006-12-09 2011-12-27 積み重ねられた集積回路パッケージインパッケージシステムおよびその製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011285712A Active JP5397964B2 (ja) 2006-12-09 2011-12-27 積み重ねられた集積回路パッケージインパッケージシステムおよびその製造方法

Country Status (4)

Country Link
US (1) US7772683B2 (https=)
JP (2) JP4947656B2 (https=)
KR (1) KR101454883B1 (https=)
TW (1) TWI345298B (https=)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7746656B2 (en) * 2005-05-16 2010-06-29 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
US7518224B2 (en) * 2005-05-16 2009-04-14 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
US7622333B2 (en) * 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US7645638B2 (en) * 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
US8432026B2 (en) * 2006-08-04 2013-04-30 Stats Chippac Ltd. Stackable multi-chip package system
US8642383B2 (en) * 2006-09-28 2014-02-04 Stats Chippac Ltd. Dual-die package structure having dies externally and simultaneously connected via bump electrodes and bond wires
US7759783B2 (en) * 2006-12-07 2010-07-20 Stats Chippac Ltd. Integrated circuit package system employing thin profile techniques
US7635913B2 (en) * 2006-12-09 2009-12-22 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US8304874B2 (en) * 2006-12-09 2012-11-06 Stats Chippac Ltd. Stackable integrated circuit package system
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US8163600B2 (en) * 2006-12-28 2012-04-24 Stats Chippac Ltd. Bridge stack integrated circuit package-on-package system
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US7683469B2 (en) * 2008-05-30 2010-03-23 Stats Chippac Ltd. Package-on-package system with heat spreader
US8310061B2 (en) * 2008-12-17 2012-11-13 Qualcomm Incorporated Stacked die parallel plate capacitor
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
KR101686553B1 (ko) 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
KR101118711B1 (ko) 2010-12-17 2012-03-12 테세라, 인코포레이티드 중앙 콘택을 구비한 적층형 마이크로전자 조립체
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8338963B2 (en) 2011-04-21 2012-12-25 Tessera, Inc. Multiple die face-down stacking for two or more die
US8304881B1 (en) 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
KR20150046117A (ko) * 2012-08-23 2015-04-29 피에스5 뤽스코 에스.에이.알.엘. 장치 및 그 제조 방법
WO2014167871A1 (ja) * 2013-04-10 2014-10-16 株式会社村田製作所 半導体装置
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9871007B2 (en) * 2015-09-25 2018-01-16 Intel Corporation Packaged integrated circuit device with cantilever structure
US10083920B1 (en) * 2018-02-01 2018-09-25 Google Llc Package stiffener for protecting semiconductor die
KR102556518B1 (ko) * 2018-10-18 2023-07-18 에스케이하이닉스 주식회사 상부 칩 스택을 지지하는 서포팅 블록을 포함하는 반도체 패키지
US11495505B2 (en) 2019-06-03 2022-11-08 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
US11398455B2 (en) * 2019-06-03 2022-07-26 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
KR102767617B1 (ko) * 2019-08-12 2025-02-17 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR20230164794A (ko) 2022-05-25 2023-12-05 삼성전자주식회사 반도체 패키지

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144982A (ja) * 1991-11-19 1993-06-11 Nippon Precision Circuits Kk 集積回路装置
US5854507A (en) * 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
KR100319608B1 (ko) * 1999-03-09 2002-01-05 김영환 적층형 반도체 패키지 및 그 제조방법
US6414396B1 (en) * 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
JP2002076252A (ja) * 2000-08-31 2002-03-15 Nec Kyushu Ltd 半導体装置
SG97938A1 (en) * 2000-09-21 2003-08-20 Micron Technology Inc Method to prevent die attach adhesive contamination in stacked chips
TW461064B (en) * 2000-12-26 2001-10-21 Siliconware Precision Industries Co Ltd Thin-type semiconductor device having heat sink structure
JP2002231885A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置
JP2002231882A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置
KR20050016540A (ko) * 2002-06-11 2005-02-21 리플렉티버티 인코퍼레이티드 웨이퍼 기판 상에 마이크로-전기기계식 장치를 적층,현출, 및 패키지하는 방법
US7071547B2 (en) * 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
KR100480437B1 (ko) * 2002-10-24 2005-04-07 삼성전자주식회사 반도체 칩 패키지 적층 모듈
US6686656B1 (en) * 2003-01-13 2004-02-03 Kingston Technology Corporation Integrated multi-chip chip scale package
US20050067694A1 (en) * 2003-09-30 2005-03-31 Pon Florence R. Spacerless die stacking
KR100510556B1 (ko) * 2003-11-11 2005-08-26 삼성전자주식회사 초박형 반도체 패키지 및 그 제조방법
JP2005302815A (ja) * 2004-04-07 2005-10-27 Toshiba Corp 積層型半導体パッケージおよびその製造方法
JP2005302871A (ja) * 2004-04-08 2005-10-27 Toshiba Corp 積層半導体装置及びその製造方法。
US7116002B2 (en) * 2004-05-10 2006-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Overhang support for a stacked semiconductor device, and method of forming thereof
JP3842272B2 (ja) * 2004-06-02 2006-11-08 株式会社Ｇｅｎｕｓｉｏｎ インターポーザー、半導体チップマウントサブ基板および半導体パッケージ
JP4494240B2 (ja) * 2005-02-03 2010-06-30 富士通マイクロエレクトロニクス株式会社 樹脂封止型半導体装置
US7271496B2 (en) * 2005-02-04 2007-09-18 Stats Chippac Ltd. Integrated circuit package-in-package system
JP4934022B2 (ja) * 2005-03-17 2012-05-16 パナソニック株式会社 モジュール基板
JP2006310649A (ja) * 2005-04-28 2006-11-09 Sharp Corp 半導体装置パッケージおよびその製造方法、ならびに半導体装置パッケージ用一括回路基板
US7288835B2 (en) * 2006-03-17 2007-10-30 Stats Chippac Ltd. Integrated circuit package-in-package system
US9202776B2 (en) * 2006-06-01 2015-12-01 Stats Chippac Ltd. Stackable multi-chip package system
US7622333B2 (en) * 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US7645638B2 (en) * 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system

Also Published As

Publication number Publication date
US20080136006A1 (en) 2008-06-12
JP2008147669A (ja) 2008-06-26
TWI345298B (en) 2011-07-11
JP2012064983A (ja) 2012-03-29
TW200834873A (en) 2008-08-16
US7772683B2 (en) 2010-08-10
KR20080053233A (ko) 2008-06-12
JP5397964B2 (ja) 2014-01-22
KR101454883B1 (ko) 2014-10-28

Similar Documents

Publication Publication Date Title
JP4947656B2 (ja) 積重ねられた集積回路パッケージインパッケージシステムおよびその製造方法
JP4900829B2 (ja) 積重ねられた集積回路パッケージインパッケージの製造方法および積重ねられた集積回路パッケージインパッケージシステム
JP2008147670A5 (https=)
US7368319B2 (en) Stacked integrated circuit package-in-package system
US7288835B2 (en) Integrated circuit package-in-package system
US7420269B2 (en) Stacked integrated circuit package-in-package system
JP5447904B2 (ja) マルチチップパッケージシステムおよびその製造方法
US7312519B2 (en) Stacked integrated circuit package-in-package system
US8729687B2 (en) Stackable integrated circuit package system
US8106500B2 (en) Stackable integrated circuit package system
US7498667B2 (en) Stacked integrated circuit package-in-package system
US9236319B2 (en) Stacked integrated circuit package system
US8067268B2 (en) Stacked integrated circuit package system and method for manufacturing thereof
JP5067662B2 (ja) 装着可能な集積回路パッケージインパッケージシステムおよびその製造方法
US8823160B2 (en) Integrated circuit package system having cavity
US8659175B2 (en) Integrated circuit package system with offset stack
KR101615293B1 (ko) 집적회로 패키지-인-패키지 시스템
US7439620B2 (en) Integrated circuit package-in-package system
US7446396B2 (en) Stacked integrated circuit leadframe package system

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101206

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101206

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20101206

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20101224

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110418

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110426

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110725

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110728

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110815

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111004

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111227

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120207

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120301

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150316

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4947656

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250