TWI307121B - Method and compositions for hardening photoresist in etching processes - Google Patents

Method and compositions for hardening photoresist in etching processes Download PDF

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Publication number
TWI307121B
TWI307121B TW092121695A TW92121695A TWI307121B TW I307121 B TWI307121 B TW I307121B TW 092121695 A TW092121695 A TW 092121695A TW 92121695 A TW92121695 A TW 92121695A TW I307121 B TWI307121 B TW I307121B
Authority
TW
Taiwan
Prior art keywords
plasma
photoresist
photoresist material
wafer
curing
Prior art date
Application number
TW092121695A
Other languages
English (en)
Chinese (zh)
Other versions
TW200407998A (en
Inventor
Yousun Kim Taylor
Wendy Nguyen
Chris G N Lee
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of TW200407998A publication Critical patent/TW200407998A/zh
Application granted granted Critical
Publication of TWI307121B publication Critical patent/TWI307121B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Landscapes

  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
TW092121695A 2002-08-14 2003-08-07 Method and compositions for hardening photoresist in etching processes TWI307121B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/219,995 US6923920B2 (en) 2002-08-14 2002-08-14 Method and compositions for hardening photoresist in etching processes

Publications (2)

Publication Number Publication Date
TW200407998A TW200407998A (en) 2004-05-16
TWI307121B true TWI307121B (en) 2009-03-01

Family

ID=31886605

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092121695A TWI307121B (en) 2002-08-14 2003-08-07 Method and compositions for hardening photoresist in etching processes

Country Status (8)

Country Link
US (2) US6923920B2 (https=)
EP (1) EP1529308A1 (https=)
JP (1) JP2005535936A (https=)
KR (1) KR100990064B1 (https=)
CN (1) CN100423191C (https=)
AU (1) AU2003257999A1 (https=)
TW (1) TWI307121B (https=)
WO (1) WO2004017390A1 (https=)

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US6962878B2 (en) * 2003-04-17 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method to reduce photoresist mask line dimensions
US7005386B1 (en) * 2003-09-05 2006-02-28 Advanced Micro Devices, Inc. Method for reducing resist height erosion in a gate etch process
JP2005109068A (ja) * 2003-09-30 2005-04-21 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US20050147926A1 (en) * 2004-01-02 2005-07-07 Nanya Technology Corporation Method for processing photoresist
US20060154184A1 (en) * 2005-01-12 2006-07-13 International Business Machines Corporation Method for reducing feature line edge roughness
KR100674967B1 (ko) * 2005-04-06 2007-01-26 삼성전자주식회사 더블 패터닝 방식을 이용한 미세 피치를 갖는 포토레지스트패턴 형성방법
US7390753B2 (en) * 2005-11-14 2008-06-24 Taiwan Semiconductor Mfg. Co., Ltd. In-situ plasma treatment of advanced resists in fine pattern definition
JP5362176B2 (ja) 2006-06-12 2013-12-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8298958B2 (en) * 2008-07-17 2012-10-30 Lam Research Corporation Organic line width roughness with H2 plasma treatment
JP5128421B2 (ja) * 2008-09-04 2013-01-23 東京エレクトロン株式会社 プラズマ処理方法およびレジストパターンの改質方法
JP5544914B2 (ja) * 2010-02-15 2014-07-09 大日本印刷株式会社 反射型マスクの製造方法
KR101348655B1 (ko) * 2010-03-24 2014-01-08 한국전자통신연구원 미세유체 제어 장치 및 그 제조 방법
JP5142236B1 (ja) 2011-11-15 2013-02-13 エルシード株式会社 エッチング方法
US9105587B2 (en) * 2012-11-08 2015-08-11 Micron Technology, Inc. Methods of forming semiconductor structures with sulfur dioxide etch chemistries
JP6017928B2 (ja) * 2012-11-09 2016-11-02 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
CN103021925A (zh) * 2012-12-21 2013-04-03 上海宏力半导体制造有限公司 Sti的制作工艺、沟槽的刻蚀方法和光刻胶的处理方法
KR101989707B1 (ko) * 2014-07-08 2019-06-14 도쿄엘렉트론가부시키가이샤 네거티브톤 현상제 겸용 포토레지스트 조성물 및 이용 방법
JP6736314B2 (ja) * 2015-06-30 2020-08-05 エイブリック株式会社 半導体装置の製造方法
CN107564803B (zh) * 2017-08-31 2020-04-17 京东方科技集团股份有限公司 刻蚀方法、工艺设备、薄膜晶体管器件及其制造方法
KR102841479B1 (ko) 2021-05-10 2025-07-31 삼성전자주식회사 반도체 장치의 제조 방법

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US5749389A (en) * 1993-12-22 1998-05-12 Liquid Air Corporation Purgeable connection for gas supply cabinet
US5976769A (en) 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
JPH09270420A (ja) 1996-03-29 1997-10-14 Nippon Steel Corp 半導体装置の製造方法
US5843835A (en) 1996-04-01 1998-12-01 Winbond Electronics Corporation Damage free gate dielectric process during gate electrode plasma etching
JP3484317B2 (ja) * 1997-03-19 2004-01-06 沖電気工業株式会社 半導体装置の製造方法
US6103632A (en) 1997-10-22 2000-08-15 Applied Material Inc. In situ Etching of inorganic dielectric anti-reflective coating from a substrate
US6121154A (en) 1997-12-23 2000-09-19 Lam Research Corporation Techniques for etching with a photoresist mask
US6121155A (en) * 1998-12-04 2000-09-19 Advanced Micro Devices Integrated circuit fabrication critical dimension control using self-limiting resist etch
US6299788B1 (en) 1999-03-29 2001-10-09 Mosel Vitelic Inc. Silicon etching process
US6335292B1 (en) 1999-04-15 2002-01-01 Micron Technology, Inc. Method of controlling striations and CD loss in contact oxide etch
KR100447263B1 (ko) * 1999-12-30 2004-09-07 주식회사 하이닉스반도체 식각 폴리머를 이용한 반도체 소자의 제조방법
JP2001237218A (ja) 2000-02-21 2001-08-31 Nec Corp 半導体装置の製造方法
WO2001091167A1 (en) * 2000-05-25 2001-11-29 Toppan Printing Co., Ltd. Substrate for transfer mask, transfer mask, and method of manufacture thereof
US6630288B2 (en) * 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
US6673498B1 (en) * 2001-11-02 2004-01-06 Lsi Logic Corporation Method for reticle formation utilizing metal vaporization

Also Published As

Publication number Publication date
US6923920B2 (en) 2005-08-02
JP2005535936A (ja) 2005-11-24
US20050230352A1 (en) 2005-10-20
AU2003257999A1 (en) 2004-03-03
TW200407998A (en) 2004-05-16
CN1689142A (zh) 2005-10-26
EP1529308A1 (en) 2005-05-11
KR100990064B1 (ko) 2010-10-26
KR20050047091A (ko) 2005-05-19
WO2004017390A1 (en) 2004-02-26
CN100423191C (zh) 2008-10-01
US20040079727A1 (en) 2004-04-29

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