TW462088B - Deep submicron process for polysilicon etching - Google Patents

Abstract

This invention provides an etching process of semiconductor polysilicon gate, which consists of the following steps. Firstly, a semiconductor substrate with a photoresist pattern defining the polysilicon gate structure is loaded into an etching chamber. A photo pattern thinning technique is used to achieve the critical dimension. Then, CF4 dominant etching gas is employed to form hard mask and also clean the polymer deposited on the etching chamber. In the same etching chamber, a photo resist stripping process is performed and breakthrough etching process is carried out to clean the etching chamber, native oxide on the substrate and organic polymer deposited on the side wall of the hard mask using CF4 as the major etching gas. Finally, polysilicon gate etching step is performed and the substrate is moved to the phosphoric acid tank to remove the hard mask.

Description

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V. Description of the Invention (l) I Field of the Invention: i: The present invention relates to a semiconductor etching process, and in particular, to a deep-submicron and micro-process method for etching a polycrystalline silicon gate layer. Etching and photoresist removal and the use of a hard mask to etch the polycrystalline silicon layer are performed in the same process chamber. i Background of the Invention: With the rapid progress of integrated circuit technology, not only the size of components has been shortened, but also the degree of aggregation of unit wafers has been required to be higher and higher. Therefore, the process is becoming more and more complicated. For example, lithography, deposition, ion cloth, planting, etching, etc. often take dozens or even hundreds of times. Among them, the lithography process is the key and indispensable process step that occupies a high proportion in the overall process step. Therefore, being able to master the leading technology of the lithography process has the advantages of controlling lower process costs and stable quality. The leading technology of lithography process f includes not only the minimization of overlapping errors, but also the critical dimension (critica 1 dimensi ο η; CD value) is controlled more precisely, and the lithography pattern line width is more fine-grained, including lithography. Process cycle: time (cyc 1 etime) control to improve productivity. However, at present, there are some process steps in the lithography process, such as the formation of complex silicon gate etch, especially deep sub-micron and below processes.

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4 6 2 〇 B B i '~' V. Description of the invention (2) I guarantee the accuracy of the CD value, the formation of the hard mask and the removal of the light from the hard mask. The I-blocking pattern is not completed in the same last name. To facilitate the explanation of the above-mentioned traditional methods, please refer to FIG. 1A. The figure shows a stack of barrier structures 5 for forming a polycrystalline silicon gate. Among them, the stack junction structure 5 includes: semiconductor substrate 10 / thin gate oxide layer 20 / polycrystalline silicon layer 30 / thin silicon nitride oxide layer 40 / oxide layer formed by plasma-assisted chemical vapor deposition: (PEOX) 50 / Defines the photoresist pattern 60 of the polycrystalline silicon gate. Among them, the silicon nitride oxide layer is used as an anti-reflection coating to improve the lithographic resolution of the photoresist pattern, and it can also be used as a hard mask. Because the anti-reflection coating is very thin, it is only about 300 to 400 Angstroms. Therefore, there is a thin PEOX layer 50 (about 150 Angstroms) on it, which is used to prevent the silicon silicon layer from being etched during the process of etching the polycrystalline silicon layer. The etch selectivity between the oxide layer and the polycrystalline silicon layer is too close, so that the etching of the polycrystalline silicon layer is exhausted before the end of the polycrystalline silicon layer is etched. For processes below the deep sub-micron process, for example, 0.15 micron, the limit of deep ultra-violet has been exceeded. Therefore, when the semiconductor substrate structure 5 is developed after the photoresist pattern 60 is developed, the CD value is first checked, and then hard-baked, and then loaded into the etching chamber, and the structure 5 is thinned with an oxygen-containing plasma to define the CD value. For the size photoresist pattern, please refer to Figure 1B: a schematic cross-sectional view. Please refer to FIG. 1C, and then use the reduced photoresist pattern 60 as a mask, and etch a thin silicon nitride oxide layer 40 / PE0X 50 to form a hard mask. After etching 4 6 2088 f five 'invention description (5 and then check the size (AE I). Then, the semiconductor substrate structure 5 is moved to another photoresist pattern stripping chamber to strip the photoresist pattern 60. Therefore, the above-mentioned etching process is called ex-situ. The reason why this step must be moved to the photoresist pattern stripping chamber is because the inner wall of the original etching chamber usually has a considerable amount of high-molecular polymer deposition. The sidewall of the mask is also, if still: stripping the photoresist pattern 60 ′ in the same process will make the sidewall of the hard mask high molecular polymer is not cleaned, and the CD value is not easy to accurately control. Generally speaking, the photoresist pattern The stripping chamber, in addition to removing the photoresist pattern with an oxygen-containing plasma, includes: removing a photoresist residue with a mixed solution of sulfuric acid and a peroxide. In addition to stripping the photoresist pattern, it can also use a hard Qin curtain The high-molecular polymer on the side wall is cleaned to obtain the correct CD value. Then, after passing the AE I CD value test again and after hard baking, please refer to Figure 1D, and then move back to the original touch chamber to etch and restore.晶石 夕 层 3 0. Compound carved with # 刻The polycrystalline silicon layer is etched by a silicon plasma, and the gate oxide layer 20 is used as an etching stop layer. After the CD value is confirmed by the AE I program, the semiconductor substrate 5 is moved to a hot phosphoric acid bath to strip the nitrogen silicon oxide layer. In the above etching steps, the semiconductor substrate 5 must be removed and then returned to the original etching chamber. Not only will there be risks (such as contamination of other environments or fragments), but also time will be lost (generally it takes at least about 5 hours to complete). Based on the above problems, The present invention will provide a brand new method. Purpose and summary of the invention: 4 6208 8! ------------ ............------------ ---------: V. Description of the invention (4) The purpose of the present invention is to provide a polycrystalline silicon gate that shortens the etching cycle time; the pole etching method does not need to move out of the etching chamber when the photoresist pattern is stripped. Carry on, so it is i η-situ silver engraving.

I The present invention discloses a method for engraving a semiconductor multi-crystal chip, in particular, an etching method for a sub-micron gate electrode, including at least the following steps: First, a semiconductor substrate is loaded in an etching chamber, and the semiconductor substrate is at least It has a polycrystalline silicon layer / nitrogen silicon oxide layer / oxide layer structure, and has a photoresist pattern: the case layer defines the polycrystalline gate. Next, a photoresist pattern reduction technology is applied to the semiconductor substrate to reduce the photoresist pattern to a critical size. Subsequently, CF is used as the main etching gas to etch the semiconductor substrate to form a hard mask. At the same time, this step has the function of cleaning the etching chamber. In order to ensure that there is no or minimum amount of high-molecular polymer deposition; then, still in the same etching chamber, strip the photoresist pattern; followed by CF, and then use CF as the main etching gas to carry out a break-through etch step to etch to clean up the etch Natural oxide layer and hard: organic polymer on the side wall of the semiconductor substrate and the semiconductor substrate; after exposing the semiconductor substrate, the polycrystalline silicon gate is etched. Finally, the semiconductor substrate is moved to a phosphoric acid bath to remove the silicon nitride oxide layer. Detailed description of the invention: In view of the background of the invention, when

6 2 0 8 B V. Description of the invention (5); “i” because it involves the removal of the photoresist pattern on the wafer, the wafer must be removed first, and after it is removed, it will go back to the original name engraving room, so it is not beneficial. To cycle time. |

丨 It is usually more than 5 hours, which is very typical. I ί The method provided by the present invention is particularly suitable for processes of deep sub-micron and below | For example, 0.15 μm or less, please refer to the stack structure shown in FIG. 2A |: 105. Including: semiconductor substrate 1 1 0 / thin gate oxide layer 1 2 0 / polycrystalline silicon layer 1 130 / thin nitrogen silicon oxide layer 140 / oxide layer 150 / defining photoresistance of the polycrystalline silicon gate 丨 丨 pattern 1 6 0 . Among them, the silicon nitride oxide layer is used as an anti-reflection coating to facilitate the resolution of the lithography step of the photoresist pattern. The oxide layer is formed by PEOX, or a silicon nitride layer. In a preferred embodiment, the thickness of the anti-reflection coating is about 200 to 50 angstroms. A better thickness is about 300 to 400 Angstroms, and PEOX is about 100 to 2000 Angstroms. The thickness of the polycrystalline silicon layer is about 1450 to 200 angstroms. Since the etching step of cutting the photoresist pattern to the polycrystalline silicon gate is performed in the same etching chamber, the anti-reflection coating is not allowed to be too thick. As before, when the above-mentioned semiconductor substrate structure 105 is developed with a photoresist pattern, the CD (critical dimension) value (ADI CD) is checked, and then it is hard-baked, and then loaded into the etching chamber. 5 Perform a thinning step to define the CD size of the photoresist pattern. Still refer to Figure 2A: cross-sectional schematic diagram. In a preferred embodiment, the conditions for reducing the photoresist pattern are as follows: the etching chamber pressure is about 4 to 15 millitorr, the plasma source power is about 200 to 400 watts, and the bias power is 40 to 80 watts. , HBr flow 80 to 100

Page 8 6 2 Ο 8 8 I ----- ----------__________________ Five 'invention description (6) ~ — ~~~ One: Seem' Ar flow about 40 to 80 SCC [ fl, the amount of madness is about 2 to 10 sccm, and the etching time is about 20 to 60 seconds. I: Please refer to FIG. 1B ', and then use the reduced photoresist pattern 16o as a mask; 丨 use a fluorine-based plasma gas to perform a hard mask layer (nitrogen silicon oxide layer 140 / oxide layer 150). Etching, while cleaning the organic polymer on the etching chamber and the side wall of the semiconductor substrate stacking structure. Among them, the fluorine-based plasma gas system CF4, SF, or other etching gas whose fluorine / carbon ratio is at least greater than 3 or more. In a preferred embodiment, after the etching gas system is generated by a plasma source, it is dispersed in an isotropic manner in an etching chamber, and then guided by a biased M power under the semiconductor substrate. The semiconductor substrate is anisotropically etched to etch the hard mask. Therefore, the residual macromolecules on the inner wall of the etching chamber and the semiconductor substrate will be removed simultaneously. In a preferred embodiment, the etching conditions in this step are as follows: the pressure of the etching chamber is 8 to 12 mTorr, the power of the plasma source is about 550 to 650 watts, and the bias power is about 40 to The flow rate of 80 watts' c F is about 10 to 30 sccm, the flow rate of Ar is about U0 to 16 Oseem, and the etching time is detected by using the polycrystalline silicon layer 120 as the end point. i! After the hard mask etching is completed, the photoresist pattern 1 60 is peeled off. The conditions are as follows: the pressure of the etching chamber is 4 to 15 mTorr, the power of the plasma source is about 300 to 500 watts, and the bias power is about 80 to 100 watts. 6 0 seem 'The end time of the etching is determined by the end point detection to ensure that there is no residue: photoresist. Please note that the photoresist pattern stripping step of the present invention does not need to remove the semiconductor substrate 105 from the etching chamber, and can be performed in the same etching chamber. this

Page 9 d 6208 8 V. Description of the invention (7) In addition, due to the above-mentioned etching conditions, a part of the oxide layer (such as PE0X) is also etched. Subsequently, the natural oxide layer on the polycrystalline silicon layer is still subjected to a breakthrough step in the same etching chamber as a previous preparation for the i polycrystalline silicon layer etching. The natural oxide layer is deposited when the photoresist pattern stripping step is performed and when the hard cover layer is partially opened. The etching conditions in this step are as follows: the etching chamber pressure is 4 to 15 mTorr, and the plasma source power is about 30 The bias power of 0 to 500 watts is about 30 to 50 watts, the amount of CF is about 60 to 100 Osccm, and the etching time is about 5 to 15 seconds. In this step, in addition to eroding the natural oxide layer, it is also possible to clean the inner wall of the etching chamber and the residual high molecular polymers on the semiconductor substrate. Because the fluorocarbon gas used in the present invention is at least a fluorine / carbon ratio greater than 3 or more The etching environment can always be maintained in the case of very little polymer residue. Therefore, before the polycrystalline stone evening layer # is engraved, keep clean conditions, you can control the CD of A E I, and maintain reliable stability, which will be described later. After the natural oxide layer is etched through, the main etching step of the polycrystalline silicon layer 120 is performed. In a preferred embodiment, the etching conditions are as follows: the etching chamber pressure is about 4 to 15 millitorr, and the plasma The source power is about 550 to 650 watts, the bias power is about 30 to 50 watts, the HBr flow rate is about 160 to 2 0 0 seem, the C1 crazy amount is about 10 to 30 sccm, and the He ~ 0 meets the flow rate of about 2 Up to 10 sccm, the step of money engraving uses the gate oxide layer as the endpoint detection point.

Page 10 4 6 208 8 V. Description of the invention ¢ 8) Finally, take out the semiconductor substrate 105 and enter the phosphoric acid tank to remove the hard mask, and then load the second batch of semiconductor substrates in the etching chamber for another batch Carved last name. Since the etching process of each semiconductor substrate is performed by the method of the present invention, it can be kept in a clean condition when entering the etching chamber. Therefore, the method of the present invention can not only be controlled extremely well in A E I C D: Good. Figure 3 shows the stability of wafer-to-wafer (wafer to wa f e r) at the same time point. The vertical axis (left) indicates that the final CD value at the rest of the time is stable at 0.125 // m. The vertical axis (right) indicates the variability value (3σ standard deviation is less than 8nm). And Figure 4 shows that the wafer can also be maintained at different etching time points: good CD control stability (the meaning of the left and right vertical axes is the same as that in Figure 3). The advantages of the present invention are as follows: 〇) Since the etching system of the present invention is both photoresist stripping and polycrystalline silicon layer etching: performed in the same etching chamber, the semiconductor substrate can be removed and moved into the etching chamber. risk. : (2) Also because the photoresist stripping and the polycrystalline silicon layer are performed in the same etching chamber as above, the last etching can save a lot of silver etching cycle time from more than 5 hours to less than 2 hours. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others that do not depart from the disclosure of the present invention

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d 620B B V. Description of the invention ¢ 9) Equivalent changes or modifications made under the spirit should all be included in the scope of patent application described below. iiBi Page 12 46208 8 Brief description of the drawings Brief description of the drawings: The preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figure A: Figures 1A to 1D According to the conventional method, since the button substrate is engraved, since it is an ex-situ process, the money engraving cycle is relatively long. FIGS. 2A to 2C are schematic cross-sectional views of etching a semiconductor substrate according to the method of the present invention. The method of the present invention belongs to the process of i η-s i t u, so the etching cycle time can be shortened. Fig. 3 shows a schematic diagram of analyzing the CD value control stability by using the method of the present invention to analyze the CD value using w af e r -1 0-w a f e r. FIG. 4 shows a schematic diagram of the stability of the control of the CD value by analyzing r u η -1 0-r u η by the method # of the present invention.

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Claims (1)

4 620 8 8; VI. Patent Application Range | ι. A method for etching a semiconductor polycrystalline silicon gate, the method includes at least the following steps:: Loading a semiconductor substrate in an etching chamber, at least the semiconductor substrate has been | Contains a polycrystalline silicon layer / anti-reflective coating / insulating layer structure, and a photoresist pattern layer has been formed on the structure to define the gate; i! | 1 The photoresist pattern is used as the cover layer, the first Fluoride-based plasma gas was used for the second time: the nitrogen silicon oxide layer / insulation layer was etched to expose part of the polycrystalline silicon layer, and the organic polymer on the etching chamber and the side wall of the gate structure of the semiconductor substrate was cleaned. The fluorine / carbon ratio of the base plasma gas is at least greater than 3; the photoresist pattern is stripped; the second time the fluorine-based plasma gas is used for the organic polymer on the sidewall of the gate structure of the semiconductor substrate and the compound crystal and the complex crystal The natural oxide layer on the silicon layer is etched, and the natural oxide layer is generated when the photoresist pattern is stripped, wherein the fluorine / carbon ratio of the fluorine-based plasma gas is at least greater than 3; Take the hard cover picture. , To form a polycrystalline silicon gate electrode; said semiconductor substrate is removed and the etch chamber. 2. The method according to item 1 of the application scope further includes applying a photoresist pattern reduction technique to the semiconductor substrate to reduce the photoresist pattern to a critical size. ^! | 丨 3. The method of claiming patent scope 2, wherein the photoresist pattern reduction technique mentioned above includes at least the following conditions: the pressure adjustment of the etching chamber is about 4 to 15 mTorr, and the power of the plasma source is about 2 0 to 4 0 watts with a bias power of about 40 to 80 watts Page 14 4 6 208 8 I ''-" ~ u ~~~ 1 1 ----------- ^-'~~------ 6. Scope of Patent ApplicationΗ B r The flow rate is about 80 to 100 seem, the flow rate of Ar is about 40 to 80 sccm, the amount of 0 is about 2 to 10 seem, and the engraving time is about 20 to 60 seconds. 4. The method according to item 1 of the application scope, wherein the above-mentioned insulating layer is selected from one of a silicon dioxide layer and a nitride layer. 1. The method as claimed in claim 4 wherein the above-mentioned insulation layer is used as a hard cover curtain layer. 6. The method as claimed in claim 1, wherein the anti-reflective coating comprises at least a silicon nitride oxide layer. 7. The method as claimed in claim 1, wherein the thickness of the anti-reflective coating is about 20 to 50 nm. 8. The method according to item 1 of the application scope, wherein the above-mentioned fluorine-based plasma gas contains fluorine / carbon at least greater than 3. 9. The method according to item 1 of the application scope, wherein the above-mentioned first fluorine-based plasma includes at least about 10-30 seem of CF ammonia body flow, and an Ar flow rate of about 140-160 sccm °. The method of item 1, in which the second fluorine-based plasma has at least an etching chamber pressure of 4 to 15 millitorr, and the power of the plasma source is about 300 to 462088. 6. The scope of patent application 丨 50 watts, bias power About 30 to 50 watts, CF flow rate is about 60 to 100 seem, | button engraving time is about 5 to 15 seconds. i 1 1. The method of claim 1 further comprises removing the hard mask pattern to expose the unetched polycrystalline silicon layer. 1 2. A method for etching a semiconductor polycrystalline silicon gate, the method includes at least the following steps: a semiconductor substrate is loaded into an etching chamber, and the semiconductor substrate has at least a polycrystalline silicon layer / nitrogen silicon oxide layer / Oxide layer / photoresist pattern layer structure; applying a photoresist pattern reduction technology to the semiconductor substrate to reduce the photoresist pattern to a critical size; using the photoresist pattern as a cover layer, performing the first time with a fluorine-based plasma gas Etching of nitrogen silicon oxide layer / oxide layer to expose part of the polycrystalline silicon layer, and simultaneously clean the organic polymer on the etching chamber and the side wall of the gate structure of the semiconductor substrate. The fluorine / carbon ratio of the fluorine-based plasma gas is at least Greater than 3 ;: stripping the photoresist pattern; 1 etching the organic polymer on the etching chamber and the side wall of the gate structure of the semiconductor substrate and the natural oxide layer on the polycrystalline silicon layer with a fluorine-based plasma gas for the second time , The natural oxide layer is generated when the photoresist pattern is stripped, wherein the fluorine / carbon ratio of the fluorine-based plasma gas is at least greater than 3; etching the polycrystalline silicon layer, and using the hard mask pattern as a mask, To form A compound gate, and removing the semiconductor substrate from the etching chamber. Page 16 462088 6. Application scope i I!! 13. The method according to item 12 of the scope of application, wherein the above-mentioned photoresist pattern reduction technology i includes at least an etching chamber pressure of 4 to 15 mTorr and plasma source power About 200 to 400 watts, bias power of about 40 to 80 watts, HBr flow rate of about 80 to 100 sccm, Ar flow rate of about 40 to 80 sccm, 0 sparse volume of about 2 to 10 sccm, the rest The time is about 20 to 60 seconds. 14. The method as claimed in claim 12, wherein the above-mentioned nitrogen-silicon oxide layer is about 20 to 50 nm thick. 1 5. The method according to item 12 of the application scope, wherein the above-mentioned fluorine-based plasma gas contains fluorine / carbon at least greater than 3. 16. The method according to item 12 of the application range, wherein the first fluorine-based plasma described above includes at least CF-30 ammonium flux and about 140-160 seem Ar flux. 17. The method according to item 12 of the application, wherein the second fluorine-based plasma has at least an etching chamber pressure of 4 to 15 mTorr, a plasma source power of about 300 to 500 watts, and a bias voltage. The power is about 30 to 50 watts, the CF travel is about 60 to 100 seem, and the insect engraving time is about 5 to 15 seconds. 18. The method according to item 12 of the scope of application, wherein the polycrystalline silicon is etched as described above; the layer step is etched with HBr, Cl2, He-0 slurry mixed oxide.丨 Page 17 462088 6. Application for Patent Scope 19. The method for applying for patent scope 12 further includes removing the hard mask pattern to expose the unetched polycrystalline silicon layer.