TWI286358B - Super anneal for process induced strain modulation - Google Patents

Super anneal for process induced strain modulation Download PDF

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TWI286358B
TWI286358B TW094137436A TW94137436A TWI286358B TW I286358 B TWI286358 B TW I286358B TW 094137436 A TW094137436 A TW 094137436A TW 94137436 A TW94137436 A TW 94137436A TW I286358 B TWI286358 B TW I286358B
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stress
layer
forming
region
substrate
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TW200701370A (en
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Mong-Song Liang
Chien-Hao Chen
Chun-Feng Nieh
Pang-Yen Tsai
Tze-Liang Lee
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Taiwan Semiconductor Mfg
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Description

1286358 九、發明說明： •【發明所屬之技術領域】 • 本毛月奋大致關於金氧半(metal-oxide-semiconductor，MOS)元件，尤才t 具有應力之通道區的MOS元件與其相關製程。 【先前技術】 VLSI電路的縮小化是一個半導體業界不斷追求的目標。當電路變的更 小更快，儿件的驅動電流之改善也更顯的重要。元件電流大致上跟閑極的 _長度閘極電谷、還有載子移動率(carrier m〇bility)相關。較短的多晶石夕閑 極長度'較大的閘極電容、與較高的載子移動率等都可以改善元件電流的 表現閘極長度的縮短可以透過元件尺寸的縮小而達成，這是業界持續努 力的目標。閑極電容的增大也會隨著閘介電層的變薄、閘介電常數的增加 等來達成。為了改善元件電流的表現，也有許多的方法來增加载子移動率。 在各種增加載子移動率的方法當中，有一種已知的方法是形成一帶有 應力(strain or stress)的矽通道。應力可以，增強電子或是電洞的移動率。所 以’ MOS元件的特性就可以透過帶有應力的通道來改善。這樣的技術，就 可以在固定閘極長度的條件下，同時也沒有增加電路設計的複雜度下，改 P善元件的特性。 虽矽被鈿加壓應力時，常溫下、共平面(in-phase)的電子移動率就可以 颁者的柘加。一種提供這樣應力的方法是透過生長一比例漸進的磊晶 層來達成。這樣的比例漸進的SiGe羞晶層可以是一無應力的㈣職^驗. 層。一層石夕層接著形成在此無應力的SiGe層上。這樣，此矽層中就會有應 力，然後，M〇S元件才形成在此石夕層上。目為SiGe㈣晶格常數(iattice constant)大於矽的晶袼常數，所以此石夕層就會有雙軸應力恤㈤她㈣， 而其中的載子就可以呈現出在應力下時的移動率來。 應力在個元件中，可以依照方向的不同，有三個部份：平行於Mqs
0503-A31814TWF 5 1286358 元件通道長度的部份，平行於M0S元件通道寬度的部份，以及垂直於通道 .平面的部份。如果應力的方向是平行通道長度或是寬度，這樣的應力稱為” , 共平面，，應力。研究有發現，屬於共平面張(tensile)應力的雙轴應力可以改善 NMOS的效月b ’而平行於通道方向的壓(c〇mp謂㈣應力可以改善舰〇s 的效能。 ^應力也可赠過在MOS元件上形成—應力顏(strained咖) 來貝現。办說，-接觸働H亭止(咖邮麵_，ces)層就可以當這樣 的應力盖層。當-應力盖層沉積時，因為應力蓋層跟底下的物質之間晶格 _ _距離的差異，為了要嘗試絲齊對齊彼此的晶袼，共平面應力就會因 而產生。第1關示了具有—應力通道區的一傳統_§元件。應力蓋層， 如同側好9與CES層14所示，可以對源/汲極區珥包含㈣區15)引入 應力，而讀的應力可以導入通道區u巾。所以通道區u _的載子移動 率就可以改善。 二傳統械應力蓋層的方法有不少的缺點，而且，其效果也受限於應力 b本身的t如⑤’應力i層的厚度不可以太厚，否則將增大後續 填缝技術的困難度。因此，應力蓋層所可以提供的應力就相當的有限。此 _外’要形成-個應力蓋層來同時符合不同元件(譬如觀〇3與pM〇s)所要 求的不H往往是非常的複雜而且成本非常的高。這樣製程所產生的 應;力是可以明顯的影響電晶體元件的效能。目前，為了更好的效能，已經 有許^的局部的機械應力控制技術被發展來增強載子的移動率。譬如說， ^有高應力的氮化石夕層已經有被拿來當作CES層或是側壁子，_對於電 =騎道區提供強而有力的應力。然而，這些方法都受限於這些應力層 的特性。而且，要沉積一高品質、具有高應力的應力層，也是-件困難的 事。 、
士因此，要如何改善—蓋層，來提供MOS元件的通道區適當的應力，並 同時在沒有增加太麵製程複雜度的條件之下，就成了 一個迫切析求的目 0503-A31814TWF 1286358 標。 • 【發明内容】 • 本發明的實施例提供一種形成一半導體結構的方法。首先提供一基 底，該基底包含有一第一元件區。接著形成一應力層於該基底上。然後， 以一高能量之放射源對該基底曝照，且對於該第一元件區上的該應力層進 行熱退火處理，處理時間少於1秒。 r 本發明的實施例亦提供一種形成一半導體電晶體的方法：提供一基 . 底，包含有一主動區；形成一第一閘極於該主動區上；形成一應力層，該 應力層具有一第一部份覆蓋於該第一閘極上；.以及，以一高能量之放射源 對該基底曝照，且對於該應力層的該第一部份進行一第一熱退火處理，處 理時間少於1秒。 本發明的實施例亦提供-半導體結構。該半導體結構包含有一基底、 以及-應力層。該基底具有-第-元件區與—第二S件區。該應力層於該 第一兀件區與該第二元件區上。該應力層在該第一元件區内有一第一部 份，具有一第一應力。該應力層在該第二元件區内有一第二部份，具有一 第二應力。該第-跟該第二應力大致上不同。該第_跟該第二應力其中之 曹-係由被-極速退火製程所產生，且該極速退火製程的熱處理時間少於_ 秒。 驗本發明之上述目的、職和優點能更鶴雜，下文跡一較佳 實施例，並配合所附圖式，作詳細說明如下： ' \ ' 【實施方式】 —種在形成應力層之後，调整其應力的方法顯示於第2圖到第10圖的 圖示中。在這些不同的圖與實施例當中，一樣的符號將用在一樣的零件上。 請看第2圖’其中有顯示了—基底·基底4G可以用—般熟知的基底
0503-A31814TWF 7 1286358 材料，譬如說石夕、SiGe、長在SiGe上帶有應力的石夕、絕緣層上覆石夕㈣c〇n . 〇n 1臟1at〇r，S〇I)、絕緣層上覆石夕錯(silic〇n ge職on insulator， 絕緣層上覆鍺(germanium on insulator，SGOI)、等等。這樣的基底4〇可以 可有苐一元件區100跟第一元件區200，用來形成不一樣的邏輯元件。於一 實施例中，元件區100跟200的其中之一用來形成PM〇S ;另一個用來形 成NMOS。於其他一實施例中，元件區100跟2〇〇的其中之一是核心 region)，用來形成核心元件(core device);另一個是周邊區，用來 形成像輸出入(Input/output)元件。於其他一實施例中，元件區1〇〇跟2〇〇的 • 其中之一是邏輯區(1〇每c reSion)，具有一邏輯電路；另一個是記憶區(memoiy) 區，具有€憶元件(memory cell)，譬如說，靜態隨機存取記憶體(SRAM)或 是動態隨機存取記憶體(DRAM)。 第一元件區1〇〇中形成了一第一閘結構，具有一閘介電層124以及一 間電極126。第二元件區200中形成了一第二閘、結構，具有一閘介電層224 以及一閘電極226。如同一般所熟知的，為了要形成這些閘結構，一閘介電 層先开> 成在基底40上。這樣的閘介電層最好是高介電常數(紐或κ)的材料。 一閘電極層’可以是多晶矽、金屬、或是金屬矽化物等·，接著形成在閘介 電層上。閘介電層跟閘電極層接著可以被圖案化，來形成閘電極126與226、 跟閘"笔層124與224。輕摻雜源/汲極區(lightly-doped source/drain region)128跟228可以接著用佈植入適當的雜質而形成，在第一元件區1〇〇 與第二元件區200中… 第3圖顯示了 一閘侧壁子層42沉積在先前所完成的結構上/在此說明 書中，閘側壁子層42有時也會是一應力層。但是應力層也可能是、或是包 含有其他層，譬如說後續形成的CES層或是層間介電(interlayerdielectric， ILD)層。而對於任何一應力層所使用的極速退火製程也可以適用到其他層。 在此實施例中，閘側壁子層42為單一的一層’覆蓋^^第一元件區⑺。 跟第二元件區200上··在第一元件區1〇〇的閘側壁子層標示為42ι，在第二 8 1
0503-A31814TWF 1286358 元件區200的閘側壁子層標示為422。閘側壁子層42的材料可以是SiN、氮 氧化石夕(oxynitride)、氧化石夕(oxide)等等，而且可以用傳統的沉積方法形成， 舌如電水輔助化學氣相沉積^plasma enhanced chemical vapor deposition， m PECVD)、低壓化學氣相沉積(i〇w pressure chemicaj vap〇r deposition， LPCVD)快速熱退火化學氣相沉積（rapid thermal chemical vapor deposition ’ RTCVD)、原子層沉積(atomic layer deposition，ALD)、物理氣 相沉積(physical vapor deposition，PVD)尊。如同業界所知的，閘侧壁子層 42的應力可以透過適當的材質選取以及形成的方法來調整。形成的方法 _ 中’可以調整的製程參數有溫度、沉積速度、功率等等。熟知此技術之人 士可以透過實驗，發現這些製程參數跟一沉積層之應力的關係。在沉積之 後，閘侧壁子層42具有一第一内在應力。 一罩幕層1如接著覆蓋在第一元件區100上，如同第4圖所示。在一 實施例中，罩幕層130可以是一光阻層。.罩幕層130可能是一光阻層、一 抗反射層(anti-reflect coating，ARC)、一硬光罩層、或者上述之組合層。 接著用一極速退火(super anneal)製程對於閘側壁子層42進行熱退火處 理。處理方式可以是以一高能量之放射源，譬如雷射或是閃光燈，在很短 _ 的8^間内’來對基底40曝照。罩幕層130可以吸收或是反射放射源所放射 .出來的能量，藉以保護其下的閘侧壁子層42l，免於受到極速退火。因為溫 度的極速上升，暴露的閘側壁子層422將會被熱退火處理。該放射源的波長 可以介於一奈米(nm)到一毫米(_)之間。透過波長的選取，就可以控制基 底40被熱退火處理的深度。一般而言，波長越長，被熱退火處理的深度越 深°熱退火處理時間最好少於1秒。在另一個實施例中，熱退火處理時間 "於約1微微秒(pico_seconcj)到約1毫秒㈣迎—從⑵以)之間。熱退火處理溫 度最好大約高於1〇〇〇〇C，可以透過調整高能量之放射源的能量來控制。在 其他貫施例中，此極速退火製程包含有一快速退火(ilash anneal)。罩幕層13〇 可以在極速退火製程後去除。
0503-A31814TWF 9 !286358 在閘側壁子層4¾中的應力會受到極速退火製程的影響而調整。一般來 、 說’ ^雜極速退火製程減理後，其中的應力應該會往張應力(tensile) , 方向變大。譬如1兒，如果壓應力(嶋pressive strain)是用負值表示，而張應 力是用正值表示的話，那經過極速退火製程熱處理後，那一層的應力之值 =該是增加的。實驗顯示了應力之增加量跟極速退火製程的能量基本上 疋王現JL相關.能4越高，應力增加量越大。目此，可以藉由不同能量的 極速退火製程，來調整一應力層其中的應力。 在極速退火製程後’閘側壁子層处具有一第二内在應力。因為被遮住 •的閘側壁子層421還是停留在有第一内在應力的狀況下，所以，之後在第一 元件區100跟第二元件區2〇0中形成的側壁子就會有不同的應力。譬如說， 閘側壁子層42]可能有壓應力，而因為被極速退火製程所影響，閘側壁子層 42s具有張應力。在另一個實施例中，閘側壁子層421與422都是有壓應力， 只是閘側壁子層422中的張應力比較高。 帛4圖顯示健有部分的應力層(譬如閘側壁子層422)被熱退火處理。 這是-個非常有用的特徵。因為不同的元件(譬如顺〇§跟pM〇s)所需要 的應力’就可以分別的調整，而不會影響到其他的元件所要的應力。所以， • 本發明的實施例提供了一個非常具有彈性的方式來調整應力。 在第二兀件區200被熱處理後，也可以選擇性的把第二元件區2〇〇遮. 住’，對於閘側壁子層兑進行熱處理(未顯示）。然而，如果都是進行極速退 火製程，這兩個極速退火製程的製程參數，像是波長、能量等，最好是不 _樣。這樣，閘侧壁子層421與42〗的内在應力才會不一樣。 、閘側壁子層4¾最後會用來形成側壁子。而閘側壁子層422的密度會因 為極速退火製程的影響，而變的比較緻密。一般來說，在侧壁子形成之後 到源/汲極區完成之前都會經歷一些浸濕製程(wet邮，像是一些清 洗製程(cleaning process)。而這些浸濕製程的副作甩，往往就是斂就到側壁 子。所以，往往軸了側壁子的厚度上之控制問題，尤其是當對側壁子的 0503-A31814TWF 1Π 1286358 蝕刻率非常高的時候。變的比較緻密的側壁子可以降低後續浸濕製程所造 • 成的影響，所以側壁子的製作也會變的比較好控制。此外，因為極速退火 • 製程是一個非常非常短時間的製程，儘管在對於閘侧壁子層42進行熱處理 恰，底下的LDD區128跟228也很有可能會被同時熱處理，LDD區128 跟228中的雜質擴散應該是可以控制的很好。 在一貫施例中，罩幕層130並沒有形成1透過使用可以集中控制其放 ’ 射線的放射源，譬如說光束大小範圍可以調整的雷射，就可以選擇第一元 、 件區100或是第二元件區200，來各別進行極速退火製程i . 第5圖顯示了侧壁子⑶跟232的形成，一般是經歷了非等向性侧。 譬如說’反應離子蝕刻(reactive ion 码可以移除在垂直表面上的 閘側壁子層42。所形成的側壁子132、232就會有有不同的内在應力，就可 以分別對於其附近MOS元件的通道區施以相對應的不同應力。 跟第5圖類似的結構也可以用不一樣的製程流程來製作，如同第6圖 與第7圖所示。第6圖顯示第3圖中的結構在一後續步驟中的剖面圖。在 尚未經歷極速退火製程之前，閘側壁子層42就先蝕刻，所以側壁子132與 232有一樣的内在應力。在第7圖中，一罩幕層14〇形成在基底恥上，用 φ 來保護側壁子132，而極速退火製程就只有對於側壁子232進行熱處理。罩 幕層140最好跟第3圖中的罩幕層13〇類似。.罩幕層14〇可以在稍候的製 程去除。 第8圖顯示了源/汲極區丨44與244以及金屬矽化物層與2奶的形 成。源/汲極區144與24的表面可能比基底4〇的表面低或是高，低的話可 以用蝕刻的技術，高的話可以用磊晶成長，相對應的後續形成的應力層也 會變低或是變高。在一例子中，源/沒極區144與244是以離子佈植的方式， 將雜質植入基底40中而形成。側壁子132以及232用來當作罩幕，所以源 /沒極區144與244的邊緣會跟側壁子132以及232大致切齊。閘電極126 與226最好也一起被離子植入，用以降低其電阻。
0503-A31814TWF 1286358 金屬矽化物層146與246可以用自行校準矽化(Salicide)製程形成在源/ • 及極區I44與244中。為了形成一金屬石夕化物，一薄薄的金屬層，像是銘 (cobalt)、鎳(nickel)、鈦(Titanium)等，先形成在元件上。然後，進行一退火 製転’使得金屬層跟底下相接觸的矽產生反應，形成一金屬矽化物在其間。 沒有起反應，多餘的金屬可以去除。 第9圖為接觸蝕刻停止(c〇ntaci etch _，CES)層148形成之後的結構 圖。CES層148有第一部份148ι與第二部份MgyCEs層148可以有siN、 氮氧化矽(oxynitride)、氣化矽(oxide)、等。在一實施例中，CES層148先整 • 面的沉積上去，用的物質可以提供第一元件區100中的MOS元件所希望的 應力。透過-罩幕層149的協助，在第二元件區2〇〇中的CES層1482可以 用極速退火製程進行熱處理，所以產生了適當的應力。在另一個#施例中， CES層148】經歷了熱處理，但是哪層148A一罩幕層遮住。在另_個實 施例中，CES層响跟14¾被不同的極速退火製程所處裡，但是兩個極速 退火製程的製程參數不同。在極速退火製程之後，罩幕層149可以去除。 接著如同第10圖所示，一層間介電(土把卜㈣红dielectric，正〇)層 >儿積在CES層148的表面上。！LD層15〇有第一部份15〇1與第二部份15〇2。 φ 類似先相製表，一罩幕層152接著形成，用來覆蓋第-元件區1〇〇。一極 速退火製程接著進行，用來改變ILD層1502中的應力。 在刚述的實施例中，應力層，包含有側壁子232、CES層.148跟ILD 層150 ’是在不同的步驟中經歷了極速退火製程。然而，極速退火製程是可 以，接著在侧壁子232、CES層148跟肋層15〇各別完成之後就進行， 或疋兩層一層元成之後才進行。這樣複合帶有應力之侧壁子/⑽層如^ 層的、、Ό構可以形成在不同的元件區域上，某些部份帶有張應力，而某些部 ，因為極速退火製程:的影響，所帶的應力會變成壓應力。譬如說1 一 讀區100中有一 PM0S兀件，第二元餘區纖中有一丽〇8元件。在第 一元件區⑽中的應力層，像ICES層1482跟/或肋層15G2，會有壓應
0503-A31814TWF 1286358 力。所以相對的PM0S通道區就會有壓應力。在第二元件區2⑻中的應力 層被極速退火製程所影響，所以產生了張應力。所以，所以相對的 通道區就會有張應力。 極速退火製程可以對整個晶圓進行，或是對晶圓上的特定部分進行。 可以依照元件種類不同而進行，譬如說分成元件、pM〇s元件、雙 極性互補 MOS(bipolar complementaiy MOS，Bi-CMOS)元件、雙極性接面 電晶體(bipolar junction transistor，BJT)、電容等等。也可以依照電路種類不 同而進行，譬如說分成邏輯電路、高效能電路、低功率電路、sram、内建 RAM ^ BJT ^ Bi-CMOS ^ ^I(radio frequency ^ RF)f ^. ^(mix-mode) 電路等等。 以上的實施例有許多的好處。M0S元件上的側壁子、CES層、以及辽^ 層的應力都可以被調整，所以M0S元件中的通道區之應力也跟著改善。此 外’側壁子的敏密度改善了。利用對於不同元件進行極速退火製程，就可 以依照元件的需求，給予不_應力。而且，以低溫形成的側壁子所帶有 的缺點也被克服了。 本發明雖以較佳實施例揭露如上，然其並非狀限定本發明，‘任何熟 習此項技藝者，在不騰本發明之精神和範圍内，.當可做些許的更動與潤 飾’因此本發明之保護範圍當視後附之中請專麵圍所界定者為準。 0503-A31814TWF 13 1286358 【圖式簡單說明】 - ^圖頒不了具有一應力通道區的一傳統MOS元件。 . 弟2 ®到第1G _示在不_程步驟時，調整應力層之應力的方 使用的晶圓剖面圖。 【主要元件符號說明】 側壁子9 .; CES 層 14 ; 基底40 ; 第一元件區100; 閘介電層124、224 ; 輕摻雜源/汲極區128、228 ; 側壁子132、232 ; 金屬矽化物層146、246 ; ILD 層 150、150!、1502。 源/沒極區12 ; LDD 區 15 ; 間側壁子層42、42ι、422 ; 第二元件區200 ; 閘電極126、226 ; 罩幕層 130、140、149、152 源/ί及極區144、244 ; CES 層 148、148!、1482 ; 0503-A31814TWF 14

Claims (1)

1286358 4十、申請專利範圍： • l一種形成一半導體結構的方法，該方法包含有： 提供一基底，包含有一第一元件區； 形成一應力層於該基底上；以及 以一高能量之放射源對該基底曝照，且對於該第一元件區上的該應力 層進行熱退火處理，處理時間少於1秒。 z如申請專利範圍第〗項所述之形成一半導體結構的方法，其中，該 處理B爾係介於约1微微秒&ic〇_sec〇nd)到約i毫秒㈣^ 馨 3·如申請專利範圍第丨項所述之形成一半導體結構的方法，其中，該 基底具有一第二元件區，且於該第二元件區中的該應力層並沒有受到熱退 火處理。 · 4.如申清專利範圍第3項所述之形成一半導體結構的方法，其中，該 第二元件區係為-週邊區(peripheiyregi〇n)或是_記憶體元件區。 5·如申請專利範圍帛3項所述之形成一半導體結構的方法，另包含有. 對於該第二元倾進行熱敎處理，且對於該第二元件區進行之熱退火處 理與對於該第一元件區進行之熱退火處理大致不相同。 6.如申請專利範圍第」項所述之形成一半導體結構的方法，立中，該 讚應力層係、為-閘側壁子(gate spacer)、一蓋層 (inter layer dielectric layer)其中之一、或是其组合。 7.如申請專利範圍第i項所述之形成一半導體結構的方法，其中，該 第一元件區係為一邏輯元件區。 8· —種形成一半導體電晶體的方法，該方法包含有： 提供一基底，包含有一主動區； 形成一第一閘極於該主動區上； •形成-應力層，該應力層具有_第_部份覆蓋於該第—閘極上；以及 以-南能量之放射源對該基底曝照，且對於該應力層的該第一部份進 0503-A31814TWF 15 1286358 行一第一熱退火處理，處理時間少於1秒。 9·如申請專利範圍第8項所述之形成一半導體電晶體的方法，其中， 該處理時間係介於約i微微秒(pico-second)到約1毫秒(milli-Sec〇nd)之間。 10. 如申請專利範圍第8項所述之形成一半導體電晶體的方法，其中， 該放射源係為一雷射或是一閃光燈。 11. 如申請專利範圍第8項所述之形成一半導體電晶體的方法，其中.， 該放射源具有一波長，介於一奈米(nm)到一毫米(mm)之間。 12. 如申請專利範圍第8項所述之形成一半導體電晶體的方法，其中， 當進行該第一熱退火處理時，該應力層的該第一部份所承受的溫度係大約 高於1000。〇 13. 如申請專利範圍第8項所述之形成一半導體電晶體的方法，其中， 形成該應力層之步驟包含有： 形成一閘側壁子層；以及 於進行該第一熱退火處理之前，ϋ刻該閘侧壁子層，以形成一閘侧壁 子。 14·如申請專利範圍第8項所述之形成一半導體電晶體的方法，其中， 形成該應力層之步驟包含有： 形成一閘側壁子層；以及 於進行該第一熱退火處理之後，餘刻該閘側壁子層，以形成一閘側壁 子。 15·如申請專利範圍第8項所述之形成一半導體電晶體的方法，其中， 形成該應力層之步驟包含有： 形成一第二閘極於該基底上； 其中’該應力層的一第二部份係覆蓋於該第二閘極上，且於進行該第 一熱退火處理時，該應力層的該第二部份並沒有被退火。 16·如申請專利範圍第15項所述之形成一半導體電晶體的方法，其 0503-A31814TWF 16 1286358 中’該應力層的該第二部份進行n退火處理，該第二熱退火處理與 該第-熱退火處理大致不相同，且該第二熱退火處理伽—高能量之放射 源對該基底曝照，處理時間少於i秒。 17. —半導體結構，包含有： 一基底，具有一第一元件區與一第二元件區；以及 一應力層，於該第一元件區與該第二元件區上； 其中，該應力層在該第一元件區内有一第一部份，具有一第一應力， 該應力層在該第二元件區内有一第二部份，具有一第二應力，且該第一跟 該第二應力大致上不同； 其中，該第一跟該第二應力其中之一係由被一極速退火製程所產生， 且該極速退火製程的熱處理時間少於一秒。 18. 如申請專利範圍第17項所述之半導體結構，其中，該應力層包含 一閘側壁子。 19. 如申凊專利範圍第17項所述之半導體結構，其中，該應力層包含 一蓋層。 20. 如申請專利範圍第17項所述之半導體結構，其中，該第一應力係 為Μ應力’該弟一應力係為張應力’其中’ 一 NMOS元件係形成於該第·一 元件區，一 PMOS矽形成於該第二元件區。 21. 如申請專利範圍第17項所述之半導體結構，其中，該第二元件區 係為一周邊區。 0503-A31814TWF 17
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