TWI270935B - Metal gate electrode using silicidation and method of formation thereof - Google Patents

Metal gate electrode using silicidation and method of formation thereof Download PDF

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Publication number
TWI270935B
TWI270935B TW092110111A TW92110111A TWI270935B TW I270935 B TWI270935 B TW I270935B TW 092110111 A TW092110111 A TW 092110111A TW 92110111 A TW92110111 A TW 92110111A TW I270935 B TWI270935 B TW I270935B
Authority
TW
Taiwan
Prior art keywords
polycrystalline
gate
dielectric
layer
substrate
Prior art date
Application number
TW092110111A
Other languages
English (en)
Chinese (zh)
Other versions
TW200403729A (en
Inventor
Witold P Maszara
Zoran Krivokapic
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200403729A publication Critical patent/TW200403729A/zh
Application granted granted Critical
Publication of TWI270935B publication Critical patent/TWI270935B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50—Alloying conductive materials with semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
TW092110111A 2002-04-30 2003-04-30 Metal gate electrode using silicidation and method of formation thereof TWI270935B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/135,227 US6599831B1 (en) 2002-04-30 2002-04-30 Metal gate electrode using silicidation and method of formation thereof

Publications (2)

Publication Number Publication Date
TW200403729A TW200403729A (en) 2004-03-01
TWI270935B true TWI270935B (en) 2007-01-11

Family

ID=27610948

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092110111A TWI270935B (en) 2002-04-30 2003-04-30 Metal gate electrode using silicidation and method of formation thereof

Country Status (8)

Country Link
US (2) US6599831B1 (https=)
EP (1) EP1502305A1 (https=)
JP (1) JP2005524243A (https=)
KR (1) KR20040102187A (https=)
CN (2) CN1729576A (https=)
AU (1) AU2003231119A1 (https=)
TW (1) TWI270935B (https=)
WO (1) WO2003094243A1 (https=)

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EP1744351A3 (en) * 2005-07-11 2008-11-26 Interuniversitair Microelektronica Centrum ( Imec) Method for forming a fully silicided gate MOSFET and devices obtained thereof
JP2007027727A (ja) * 2005-07-11 2007-02-01 Interuniv Micro Electronica Centrum Vzw フルシリサイド化ゲートｍｏｓｆｅｔの形成方法及び該方法により得られるデバイス
KR100646937B1 (ko) 2005-08-22 2006-11-23 삼성에스디아이 주식회사 다결정 실리콘 박막트랜지스터 및 그 제조방법
JP2007173347A (ja) * 2005-12-20 2007-07-05 Renesas Technology Corp 半導体装置及びその製造方法
WO2007077814A1 (ja) * 2006-01-06 2007-07-12 Nec Corporation 半導体装置及びその製造方法
JP2007251030A (ja) * 2006-03-17 2007-09-27 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7491643B2 (en) * 2006-05-24 2009-02-17 International Business Machines Corporation Method and structure for reducing contact resistance between silicide contact and overlying metallization
US7297618B1 (en) 2006-07-28 2007-11-20 International Business Machines Corporation Fully silicided gate electrodes and method of making the same
WO2008035490A1 (en) * 2006-09-20 2008-03-27 Nec Corporation Semiconductor device and method for manufacturing same
JPWO2008065908A1 (ja) * 2006-11-29 2010-03-04 キヤノンアネルバ株式会社 金属ｉｖ族元素化合物膜の形成方法及び半導体装置の製造方法
US7727842B2 (en) * 2007-04-27 2010-06-01 Texas Instruments Incorporated Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device
US8183137B2 (en) * 2007-05-23 2012-05-22 Texas Instruments Incorporated Use of dopants to provide low defect gate full silicidation
JP2009026997A (ja) * 2007-07-20 2009-02-05 Renesas Technology Corp 半導体装置およびその製造方法
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Also Published As

Publication number Publication date
CN102157362A (zh) 2011-08-17
US6599831B1 (en) 2003-07-29
CN1729576A (zh) 2006-02-01
WO2003094243A1 (en) 2003-11-13
CN102157362B (zh) 2012-05-16
JP2005524243A (ja) 2005-08-11
US20030203609A1 (en) 2003-10-30
AU2003231119A1 (en) 2003-11-17
EP1502305A1 (en) 2005-02-02
TW200403729A (en) 2004-03-01
KR20040102187A (ko) 2004-12-03
US6873030B2 (en) 2005-03-29

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