TWI270145B - Low-GIDL MOSFET structure and method for fabrication - Google Patents

Low-GIDL MOSFET structure and method for fabrication Download PDF

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TWI270145B
TWI270145B TW093100591A TW93100591A TWI270145B TW I270145 B TWI270145 B TW I270145B TW 093100591 A TW093100591 A TW 093100591A TW 93100591 A TW93100591 A TW 93100591A TW I270145 B TWI270145 B TW I270145B
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gate
conductor
gate conductor
mosfet device
polysilicon
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Omer H Dokumaci
Bruce B Doris
Oleg Gluschenkov
Jack A Mandelman
Carl Radens
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Description

1270145 五、發明說明（1) 一、【發明所屬之技術領域】 本發明一般關於一低G I DL (閘極引發汲極漏）電流金屬 氧化半導體場效應電晶體（M0SFET)裝置之結構及其製造方 法。 二、 【先前技術】 當裝置尺寸縮減時，由於閘極引發汲極漏（G I DL)電流 之可靠度問題，迫使操作電壓低於最佳裝置效能之期望。 此閘極引發汲極漏電流係沿著閘極導體重疊汲極擴散 區域之區域，起因為場效應電晶體產生位於表面汲極空乏 區域之電洞配對。此係發生於一 N型金屬氧化半導體場效 應電晶體（N Μ 0 S F E T ) ’當裝置被施以一偏壓使汲極電位較 閘極電位為正（大於+ 1伏特）時，或於一 Ρ型金屬氧化半導 體場效應電晶體（ΡΜ0SFΕΤ)閘極電位較沒極電位為正時（大 於+ 1伏特）。 三、 【發明内容】 當裝置尺寸縮減時，由於閘極引發汲極漏（G〗DL)電流 之可靠度問題，迫使操作電壓低於最佳裝置效能之期望。 此閘極引發汲極漏電流係沿著閘極導體重疊汲極擴散 區域之區域’起因為場效應電晶體產生位於表面汲極空乏 區域之電洞配對。此係發生於一 _金屬氧化半導體場效
第6頁 1270145 五、發明說明（2) 應電晶體（N Μ 0 S F E T ) ’當裝置被施以一偏壓使汲極電位較 閘極電位為正（大於+1伏特）時，或於一 Ρ型金屬氧化半導 體場效應電晶體（PM0SFET)閘極電位較汲極電位為正時（大 於+ 1伏特）。 四、【實施方式】 圖1 - 9說明根據本發明之技術，一種製造一低閘極引 發汲極漏電流M0SFET (金屬氧化半導體場效應電晶體）裝置 之方法。 圖1說明於M0SFET之首要/主要中間閘極電極多晶矽沉 積被圖案化後之一裝置，此圖案化係藉由一般微影以及 R I Ε (反應性離子蝕刻）製程。 poly )可 ’將閘極 NFET，或 閘極多晶體多晶矽（gate pc(p〇ly crystal) 能在餘刻别先被選擇性地摻雜。於說明實施例中 掺雜P型雜質以產生一高v t (起始電壓）表面通道 者疋一低 Vt埋通道（buried 回 口兄 ； ’，一 "％刊竹况檟形成一平板膜 film)於垂直表面上後之結構。此平板膜舉例 况為一軋化矽。此非等向性介電材料沉積， 為 HDP(高密度電漿），較佳為氧化物。 W +况為
4IBM03149TW.ptd 第7頁 1270145
圖3說明一結構，此結構係經沉積一導電性擴散障蔽 (conductive diffusion barrier)(即 wn(鎢 /氮化嫣）、 T i N，用以防止側壁之金屬與閘極多晶矽反應）、一金屬間 隙壁如CVD(化學氣相沉積），以及使用CVD及等向性RIE延 PC側壁形成一鎢/氮化鎢間隙壁。 金屬側壁間隙壁係防止一整流接面（rectifying j unc t i on)形成於閘極電極多晶矽以及之後形成的側壁凹 痕（d i v 〇 t )多晶石夕閘極延伸之間。 圖4說明於平板膜HDP介電材料被剝離以形成懸吊 (h a n g i n g )之間隙壁後之結構。
圖5說明於多晶石夕以及石夕底材選擇性地氧化於ψ金屬間 隙壁後之結構（舉例來說見S. I wata et al.， IEEE
Trans· Electron Device, ED-31， ρ·2274 (1984))0 暴 露的多晶矽閘極電極之側壁被氧化，而此氧化障蔽提供了 一絕緣障蔽，以避免因n+閘極側翼（side wing)閘極導體 與P+中間閘極導體多晶石夕之不同功函數產生一接面。 圖6說明於沉積一薄LPCVD(低壓化學氣相沉積）多晶矽 以填滿凹痕（d i vo t )後之結構，此凹痕之形成係於W間隙壁 下方之底切區域（undercut region)。
4IBM03149TW.ptd 第8頁 1270145 五、發明說明（4) 此薄LPCVD多晶矽可能摻雜戍夫 時，其摻雜極性與S/D擴散之極性相公：= 時，薄LPCVD多晶矽可能使用已知之任_ 二雜/儿積 例來說，低能量有角度的離子植入、電將或:且/方法，舉 (immer:ion)、氣相摻雜，或者是固態%源^^\所有的检 雜技術係使用一微影定義之區塊光罩層物 以區別NFETs以及PFETs。 视4 化物 圖7揭示以一等向性蝕刻將薄LpcVD石夕自場區域移除， 而留下於側壁凹痕内之薄LPCVD石夕後之結構，等向性蝕刻 舉例來說為化學乾蝕刻（CDE)，係使用Π或者丄 基(如-帶狀蚀刻（strap etch))。 疋C1之自由 圖8揭示於一般製程，包含有稱呼的（titled)以及無 稱呼的（non-title)的離子植入，形成s/D延伸/暈圈 (h a 1 〇 )以及間隙壁後之結構。源及汲極區域係重摻雜區 域，而延伸/暈圈係輕摻雜，於一第一實施例中輕微重疊 之側翼閘極導體係於8 0，而於第二實施例中輕微重疊之中 間閘極導體係於8 2。 且 圖9揭示以一般製程形成自行對準矽化物（sa丨丨c丨de) 後之裝置。 所述方法係製造一種低閘極引發汲極漏（G丨D L )電流
1270145
MOSFET裝置，此裝置包含一中間閘極導體，其邊緣可能輕 微重疊於源/汲極擴散，且側翼閘極導體藉由一絕緣及擴 散障蔽薄層而與中間閘極導體分隔。 對於一 NM0SFET裝置’側翼閘極導體較佳由多晶石夕 組成，而對於一 PM0SFET裝置，側翼閘極導體較佳係由p + 夕晶石夕組成。當期望得到一高Vt (臨界電壓）之nm〇SFET (如 應用於DRAM)，則中間閘極導體區域可能為p+，當為了增 進效能（PFETs可能需要使用互補式摻雜）須要得二一低 (臨界電壓）之nmosfet時，則中間閘極導體區域可能 M+。 /匕两 係藉由過度金屬側 ’閘極絕緣體G1之 係可獨立區分，這 中間導體下為厚。 此側翼閘極導體以及中間閘極導體 壁導體層而固定（strap)在一起，再者 厚度於中間閘極導體下以及側翼導體下 使得閘極絕緣體於側導體下可較佳地較 於閘極電極之邊緣以及閘極電極摻雜，相反捧雜 y、PCVD凹痕區域之間之互相擴散，係藉由側壁氧化>障蔽而 壓抑。而一介於相反摻雜凹痕以及閘極電極間之雨 藉由金屬間隙壁提供。 A ’、 同時將發現一鳥嘴（bird，s beak)延伸形成於中間間 極導體下方，這是因為外閘極導體（N+側壁）的閘極氧化物
1270145 五、發明說明（6) 再次生長。同時發生的還涉及於第二閘極氧化物之前的十 間閘極導體的邊緣幾何（關於N+侧壁閘極導體），於此穿程 中仍有30埃（A)閘極氧化層存在於中間間極下方。此結構 之後經一般閘極氧化循環（ 9 5 0C，15〇s，RT〇，1〇〇%乾燥 02)，長成3 0埃（A)於底材表面，於此區域接著將包含外N + 閘極部分，結果產生可被忽略的鳥嘴。明確地說，此鳥嘴 非常微小而假設其將對裝置的操作無關。 即使形成一巨大的鳥嘴，N+外閘極區域之i lv功函數 偏移將使得於外閘極區域發生第一次反轉，此N +外閘極區 域係關於P+内閘極區域。因此，通道電流將由中間閘極區 域控制，若中間閘極區域具有最高的V t，將使得鳥嘴對通 道電流產生最小的影響。 本發明提供一種製造一低閘極引發汲極漏（GIDL 力 MOSFET裝置之方法，包含形成一平板膜於一圖案化中間= 極導體之垂直表面以及圍繞底材區域，較佳係使用一 ^ 向性介電材料沉積以形成此平板膜於此圖案化中間閘極導 之垂直表面以及圍繞底材區域。此圖案化中間閘極導體之 形成車^圭係藉由沉積多晶矽於一底材上，並被一閘極介電 材料復孤之後藉由微影以及反應性離子钱刻製程以圖安 化MOSFET中間閘極導體。 θ木 此製程緊接著沉積一導電性擴散障蔽於此中間閘極導
4IBM03149TW.ptd
1270145 五、發明說明（7) 體之側壁，以及形成金屬間隙壁於此中間閘極導體之側壁 上，且覆於此導電性擴散障蔽上，之後剝離此平板膜以形 成懸吊之金屬間隙壁於底切區域上。 此製程緊接著氧化位在此懸吊之金屬間隙壁下方之此 中間閘極導體，以防止一整流接面形成於此中間閘極導體 以及隨後形成之左及右側翼閘極導體之間。然後沉積一多 晶矽層以填滿位在懸吊之金屬間隙壁下方之底切區域，在 此之後，藉由一等向性蝕刻移除多晶矽層，然而於懸吊之 金屬間隙壁下方之底切區域留下此多晶矽層，以形成左及 右側翼閘極導體。 此製程緊接著於形成源及汲極延伸/暈圈以及間隙 壁，並形成自行對準矽化物於導體上之後結束。於較佳實 施例中，中間閘極導體以及此左及右側翼閘極導體較佳係 由換雜多晶碎形成。 如所述之製程提供一種具有低閘極引發汲極漏（G I DL ) 電流之M0SFET裝置，此裝置包含一源極擴散區域、一汲極 擴散區域，以及一中間閘極。中間閘極包含一中間閘極導 體、一左側翼閘極導體，以及一右側翼閘極導體，其中每 一此左侧翼閘極導體以及右側翼閘極導體以一絕緣及擴散 障蔽薄層分隔。
4IBM03149TW.ptd 第12頁 1270145 五、發明說明（8) 中間閘極導體之左及右側向邊緣與源極擴散區域以及 汲極擴散區域之一重疊。左及右側翼閘極導體之左及右側 向邊緣與源極擴散區域以及汲極擴散區域之一重疊。 上電及與中 於導左體此 位壁之導與 一側體極壁 由屬導閘隙 藉.金極間間。 體之閘中壁隔 導方間於側分 極上中成屬而 閘此沿形金層 翼。係面右蔽 側起，接及障 右一壁流左散 及在隙整。擴 左定間一間性 及固壁止之電 以層側防體導 體電屬以導一 導導金用極由 極壁右，閘藉 閘側及成翼體 間屬左形側導 中金含壁右極 之包側及閘 方層右左間 閘極絕緣體之厚度於左及右側翼導體下係可獨立區 分，使其係較佳地較中間導體下之一閘極絕緣體為厚。 雖然本發明之低閘極引發汲極漏電流MOSFET之各實施 例及變體已在此詳細描述，但是顯而易知的是，本發明之 技術及揭示將使得熟知技藝者可聯想到許多替換的設計。
4IBM03149TW.ptd 第13頁 1270145 圖式簡單說明 五、【圖式簡單說明】 關於本發明之低閘極引發汲極漏電流金屬氧化半導體 場效應電晶體之結構及其製造方法，其前述之目的及其益 處，習知技藝人士可藉由數個實施例之詳細描述，伴隨結 合圖式而輕易了解，其中數個圖式中相似元件係標示為一 致之元件符號，且其中： 圖1〜9揭露一按照本發明之低閘極引發汲極漏電流金 屬氧化半導體場效應電晶體裝置之製造方法。 圖1說明於M0SFET閘極電極多晶矽沉積藉由一般微影 以及R I E製程圖案化後之結構。 圖2說明於使用一非等向性介電材料沉積如HDP形成一 平板膜於垂直表面後之結構。 圖3說明沉積一導電性擴散障蔽（即WN、T i N )，以及延 PC側壁形成一金屬化間隙壁，如CVD W/WN間隙壁，之後之 結構。 圖4說明於平板膜HDP介電材料被剝離以形成懸吊之間 隙壁後之結構。 圖5說明於多晶矽以及矽底材選擇性地於W金屬間隙壁
4IBM03149TW.ptd 第14頁 1270145 圖式簡單說明 氧化後之結構。 圖6說明於沉積一薄LPCVD (低壓化學氣相沉積）多晶矽 並填滿W間隙壁下方之底切區域形成之凹痕後之結構。 圖7揭示以一等向性蝕刻（如一帶狀蝕刻）將薄LPCVD石夕 自場區域移除，而留下於側壁凹槽内之薄LPCVD石夕後之結 構。 圖8揭示經一般製程，包含離子植入形成S/D延伸/暈 圈以及間隙壁後之結構。 圖9揭示以一般製程形成自行對準矽化物後之裝置。 體體 導導 極極 閘閘 翼間 明側中 說之之 號疊疊 符重重 件微微 元輕輕 式 0 2 圖 8 8
4IBM03149TW.ptd 第15頁

Claims (1)

1270145 六、申請專利範圍 1. 一種提供一低閘極引發漏（GIDL)電流之金屬氧化半導體 場效應電晶體（M0SFET)裝置，包含： 一源極擴散區域、一汲極擴散區域，以及一中間閘 極； 該中間閘極包含一中間閘極導體、一左側翼閘極導 體，以及一右側翼閘極導體，其中每一該左側翼閘極導體 以及右側翼閘極導體與該中間閘極導體以一絕緣及擴散障 蔽薄層分隔。 2. 如專利申請範圍第1項所述之M0SFET裝置，其中該中間 閘極導體之左及右側向邊緣與該源極擴散區域以及該汲極 擴散區域之一重疊。 3. 如專利申請範圍第1項所述之M0SFET裝置，其中該左及 右側翼閘極導體之左及右側向邊緣與該源極擴散區域以及 該汲極擴散區域之一重疊。 4. 如專利申請範圍第1項所述之，M0SFET裝置，其中該中間 閘極導體以及左及右側翼閘極導體藉由一上方之金屬側壁 導電層固定（strap)在一起。 5. 如專利申請範圍第1項所述之M0SFET裝置，其中於該左 及右側翼閘極導體下方之一閘極絕緣體之厚度較該中間導 體下方之一閘極絕緣體之厚度厚。
4IBM03149TW.ptd 第16頁 1270145 六、申請專利範圍 6. 如專利申請範圍第1項所述之M0SFET裝置，更包含左及 右金屬側壁間隙壁延該中間閘極導體之左及右側壁形成， 以防止一整流接面（r e c t i f y i n g j u n c t i ο η )形成於該中間 閘極導體與該左及右側翼閘極導體之間。 7. 如專利申請範圍第6項所述之M0SFET裝置，其中該左及 右金屬側壁間隙壁與該中間閘極導體藉由一導電性擴散幛 蔽層而分隔。 8. 如專利申請範圍第1項所述之M0SFET裝置，包含一 NM0SFET裝置，其中每一該左側翼導體以及該側翼閘極導 體係由Ν+多晶矽形成。 9. 如專利申請範圍第1項所述之M0SFET裝置，包含一 PM0SFET裝置，其中每一該左側翼導體以及該側翼閘極導 體係由Ρ+多晶矽形成。 1 0.如專利申請範圍第1項所述之M0SFET裝置，其中該中間 閘導體由Ρ+多晶矽形成，以形成一高Vt (臨界電壓）之 NM0SFET。 11.如專利申請範圍第1項所述之M0SFET裝置，其中該中間 閘導體由N +多晶矽形成，以形成一低V t (臨界電壓）之
4IBM03149TW.ptd 第17頁 1270145
六、申請專利範圍 NM0SFET。 12.如專利申請範圍第1項所述之M0SFET裝置，其中該中間 閘導體由N +多晶矽形成，以形成一高V t (臨界電壓）之 PM0SFET。 13.如專利申請範圍第1項所述之M0SFET裝置，其中該中間 閘導體由P+多晶矽形成，以形成一低Vt (臨界電壓）之 PM0SFET。 14·如專利申請範圍第1項所述之M0SFET裝置，其中該左及 右金屬側壁間隙壁與該中間閘極導體藉由一導電性擴散障 蔽層而分隔。 1 5.如專利申請範圍第1項所述之M0SFET裝置，其中該中間 閘導體由P+多晶矽形成，以形成一低Vt (臨界電壓）之 PM0SFET。
16·—種製造一低閘極引發漏（GIDL)電流m〇SFET裝置之方 法，包含： · 形成一平板（〇 f f s e t)膜於一圖案化中間閘極導體之垂 直表面並圍繞底材區域； 心積一 ^電性擴散障蔽於該中間閘極導體之側壁上； 形成金1隙壁於覆蓋在該中間間極導體之侧壁上之
1270145 -------------^- ------ 六、申請專利範圍 該導電性擴散障蔽； 剝離該平板膜以形成懸承之金屬間隙壁於底切區域 (undercut regions)上； 氧化位在該懸吊之金屬間隙壁下方·之該中間閘極導 體，以防止一整流揍面形成於該中間閘極導體以及隨後形 成之該左及右側翼閘極導體之間； 沉積一多晶矽層以填滿位在該懸吊之金屬間隙壁下方 之5亥底切區域； 藉由一等向性蝕刻移除該多晶矽層，然而於該懸吊之 金屬間隙壁下方之該底切區威留下該多晶矽層，以形成左 及右側翼閘極導體。 1 7 ·如專利申請範圍第1 6項所述之方法，其中於該移除步 驟後，形成源及汲極延伸/暈圈（halo)以及間隙壁，並之 後形成自行對準；5夕化物（s a 1 i c i d e )於導體上。 1 8 ·如專利申請範圍第1 6項所述之方法，其中該圖案化中 間閘極導體之形成係藉由沉積多晶矽於一底材上，並被一 閘極介電材料覆蓋，之叙圖案化該中間閘極導體係藉由微 景> 以及反應性離子蝕刻製程。 1 9 .如專利申請範圍第1 6項所述之方法，更包含使用一非 等向性介電材料沉積以形成該平板膜於該圖案化中間閘極 導之垂直表面以及圍繞底材區域。
4IBM03149TW.ptd 第19頁 1270145 六、申請專利範圍 2 0 .如專利申請範圍第1 6項所述之方法，更包含形成摻雜 多晶矽之該中間閘極導體以及該左及右侧翼閘極導體。
4IBM03149TW.ptd 第20頁
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EP1588403A2 (en) 2005-10-26
ATE551727T1 (de) 2012-04-15
US6841826B2 (en) 2005-01-11
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US20040248356A1 (en) 2004-12-09
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