CN101410951B - 低栅极感生的漏极泄漏的金属氧化物半导体场效应晶体管结构及其制备方法 - Google Patents

低栅极感生的漏极泄漏的金属氧化物半导体场效应晶体管结构及其制备方法 Download PDF

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CN101410951B
CN101410951B CN2004800023084A CN200480002308A CN101410951B CN 101410951 B CN101410951 B CN 101410951B CN 2004800023084 A CN2004800023084 A CN 2004800023084A CN 200480002308 A CN200480002308 A CN 200480002308A CN 101410951 B CN101410951 B CN 101410951B
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central conductor
mosfet device
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卡尔·拉登斯
奥默·H·多库马西
布鲁斯·B·多里斯
奥利格·格卢申科夫
杰克·A·曼德尔曼
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GlobalFoundries Inc
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Abstract

一种低GIDL电流MOSFET器件(90)结构及其制备方法，该器件提供了低GIDL电流。该MOSFET器件结构包含其边缘可与源极/漏极扩散(88，88)略微重叠的中部栅极导体(10)，以及通过薄的绝缘和扩散阻挡层(50，52)与中部栅极导体分开的侧翼栅极导体(70，70)。

Description

低栅极感生的漏极泄漏的金属氧化物半导体场效应晶体管结构及其制备方法
技术领域
本发明一般地涉及低栅极感生的漏极泄漏(Gate-Induced Drain Leakage，GIDL)电流的金属氧化物半导体场效应晶体管(MOSFET)器件结构及其制备方法。
背景技术
随着器件几何尺寸收缩，由于栅极感生的漏极泄漏(GIDL)电流所导致的可靠性问题迫使器件在低于所期望的最佳器件性能的电压下工作。
当器件偏置而使得在NMOSFET中的漏极电势比栅极电势更正向(大于+1V)时，或使得在PMOSFET中的栅极电势比漏极电势更正向(大于+1V)时，沿着栅极导体与漏极扩散区相重叠的区域在场效应管的表面漏极耗尽区中产生了电子-空穴对导致了GIDL电流。
发明内容
本发明提供了一种低GIDL电流的MOSFET器件结构以及一种制备低GIDL电流MOSFET器件的方法，该器件提供了相对传统MOSFET器件减少的低GIDL电流。该MOSFET器件结构包含其边缘可与源极/漏极扩散区略微重叠的中部栅极导体，以及通过薄的绝缘和扩散阻挡层从中部栅极导体分开的侧翼栅极导体。
对于NMOSFET器件，侧翼栅极导体优选地由N+多晶硅形成，而对于PMOSFET器件，侧翼栅极导体优选地由P+多晶硅形成。如果所期望的是高Vt(阈值电压)NMOSFET(如在DRAM应用中)，那么中部栅极导体区域可以是P+多晶硅，或者如果需要低Vt NMOSFET来增强性能(PFET可以使用互补掺杂)，那么可以是N+多晶硅。侧翼栅极导体和中部栅极导体可以通过重叠金属侧壁导电层而搭接在一起。此外，在中部栅极导体之下和侧翼栅极导体之下的栅极绝缘体的厚度是可以独立确定的。这允许在侧翼栅极导体之下的栅极绝缘体的厚度优选地比在中部栅极导体之下的栅极绝缘体的厚度要大。
附图说明
参考下面结合附图对本发明一些实施例的详细说明，本领域的技术人员可以更容易地理解本发明的低GIDL MOSFET及其制备方法的上述目的和优点，在附图中相同的元件由相同的标记指代，在附图中：
图1-9图示了根据本发明的教导的制备低GIDL MOSFET的方法。
图1图示了在MOSFET栅极电极多晶硅沉积已经通过标准光刻和RIE工艺构图之后的器件。
图2图示了在用比如HDP的各向异性介质沉积来形成水平表面上的偏移膜之后的器件。
图3图示了在沉积了导电扩散阻挡层(即，WN、TiN)和沿着PC的侧壁形成比如CVD W/WN分隔物的金属分隔物之后的器件。
图4图示了在剥离偏移膜HDP电介质来形成悬挂分隔物之后的器件。
图5图示了在相对W金属分隔物选择性地氧化多晶硅和硅衬底之后的器件。
图6图示了在沉积薄的LPCVD多晶硅来填充由W分隔物之下的底切(undercut)区域所形成的块(divot)之后的器件。
图7示出了在薄LPCVD硅通过各向同性蚀刻(类似带蚀刻(strap etch))从场区域去除而在侧壁块上留下了薄LPCVD硅之后的器件。
图8示出了在S/D延伸/晕圈(halo)和分隔物通过比如离子注入的传统工艺形成之后的器件。
图9示出了在硅化物通过传统工艺形成之后的器件。
具体实施方式
图1-9图示了根据本发明的教导的制备低GIDL MOSFET(金属氧化物半导体场效应晶体管)的方法。
图1图示了在MOSFET基本/主要中部栅极电极多晶硅沉积10已经通过在栅极氧化物介电绝缘体14所覆盖的衬底12上方进行标准光刻和RIE(反应离子蚀刻)工艺而构图之后的器件。
在蚀刻之前，可以选择性地掺杂栅极多晶体(poly crystal，PC)多晶硅。在所图示的实施例中，栅极10掺杂了P型杂质以得到高Vt(阈值电压)表面沟道NFET或低Vt掩埋沟道NFET。
图2图示了在各向异性介质沉积20被用来形成水平表面上的比如二氧化硅的偏移膜之后的器件，各向异性介质沉积20比如是高密度等离子体(HDP)，优选为氧化物。
图3图示了在沉积导电扩散阻挡层30(即，W/WN(钨/氮化钨)、TiN，以防止侧壁的金属和栅极多晶硅之间反应)并使用化学气相沉积(CVD)和各向异性RIE沿着PC的侧壁形成比如CVD钨/氮化钨分隔物的金属分隔物32之后的器件。
金属侧壁分隔物防止在栅极电极多晶硅和随后形成的侧壁块(sidewalldivot)多晶硅栅极延伸70之间形成整流结。
图4图示了剥离偏移膜HDP电介质20来在底切区40上形成悬挂分隔物32之后的器件。
图5图示了在相对W金属分隔物在50处选择性地氧化多晶硅和硅衬底之后的器件(例如，参看S.Iwata et al.，IEEE Trans.Electron Devices，ED-31，p.1174(1984))。暴露的多晶硅栅极电极的侧壁52被氧化，该氧化物阻挡层提供了一薄绝缘和扩散阻挡层以防止由于n+栅极侧翼栅极导体和p+中部栅极导体多晶硅的逸出功不同而导致产生结。
图6图示了在沉积薄LPCVD(低压化学气相沉积)多晶硅60来填充由W分隔物之下的底切区域所形成的块(divot)之后的器件。
该薄的LPCVD多晶硅可以掺杂或不掺杂地沉积。如果掺杂了，那么它掺杂的极性与S/D扩散区的相反。如果是未掺杂沉积的，那么该薄LPCVD多晶硅可以使用如下公知方法中的任何一种或其组合来进行掺杂，比如低能量角度离子注入、等离子体浸没、气相掺杂或固体源掺杂。所有的掺杂技术都将利用光刻工艺界定的区块掩模层(氧化物或氮化物)来在NFET和PFET之间进行区分。
图7示出了在薄的LPCVD硅从场区域去除之后的器件，通过诸如使用F1和C1基(类似带蚀刻(strap etch))的化学干法蚀刻(CDE)的各向同性蚀刻来去除薄的LPCVD硅，而在侧壁块上保留薄的LPCVD硅70。
图8示出了在S/D延伸/晕圈84和分隔物86通过传统工艺形成之后的器件，这些传统工艺包括具名(titled)或未具名的离子注入。源极和漏极区88是重度掺杂区域；而延伸/晕圈区84是轻度掺杂的，在第一实施例中与侧翼栅极导体在80略微重叠，在第二实施例中与中部栅极导体在82略微重叠。
图9示出了在自对准多晶硅化物(salicide)92通过传统工艺形成之后的低GIDL电流MOSFET器件90。
所述的制备方法产生了这样的低GIDL电流MOSFET器件90，其具有边缘可与源极/漏极扩散略微重叠的中部栅极导体，和通过薄的绝缘与扩散阻挡层与中部栅极导体分开的侧翼栅极导体。
对于NMOSFET器件，侧翼栅极导体优选地由N+多晶硅制成，而对于PMOSFET器件，侧翼栅极导体优选地由P+多晶硅制成。如果期望的是高Vt(阈值电压)NMOSFET(就如在DRAM应用中)，那么中部栅极导体区可以是P+多晶硅，而如果需要低VtNMOSFET以增强性能，那么中部栅极导体区可以是N+多晶硅(PFET将使用互补掺杂)。
侧翼栅极导体和中部栅极导体通过重叠侧壁导电层搭接在一起。此外，在中部栅极导体之下和在侧翼栅极导体之下的栅极导体GI厚度可以独立地确定。这允许在侧翼栅极导体之下的栅极绝缘体优选地比中部栅极导体之下的要厚。
在栅极电极边缘处反掺杂的LPCVD块区域和栅极电极掺杂区域之间的互扩散被侧壁氧化物阻挡层抑制。在反掺杂的块和栅极电极之间的电接触由金属分隔物提供。
已经进行了仿真来研究由于外部栅极导体(N+侧壁)的栅极氧化物的再生长所导致在中部栅极导体的边缘下鸟喙(bird’s beak)形成的程度。该仿真涉及在第二栅极氧化物(用于N+侧壁栅极导体)的再生长之前的中部栅极导体的边缘的几何形状，在处理中此时在中部栅极之下存在30的栅极氧化物。对该结构进行典型的栅极氧化循环(950℃、150s、RTO、100％干燥O2)以在随后将包含外部N+栅极导体段的区域中的衬底表面上生长30
Figure G2004800023084D00042
的氧化物，结果是出现的鸟喙可以忽略。显然，该鸟喙非常少，并且对器件的可操作性没有影响。
即使形成了大的鸟喙，N+外部栅极区域相对P+外部栅极区域的1.1V逸出功漂移将导致反型(inversion)首先在外部栅极区域出现。于是，沟道电流将由中部栅极区决定，中部栅极区具有最高的Vt，最小化了鸟喙将对沟道电流产生的任何影响。
本发明提供了制备低栅极感应的泄漏电流(GIDL)MOSFET器件的方法，该方法包括在构图的中部栅极导体和周围衬底区域的水平表面上形成偏移膜的步骤，优选地通过使用各向异性电介质沉淀来在中部栅极导体和周围衬底区域的水平表面上形成偏移膜。优选地通过在由栅极电介质覆盖的衬底上沉积多晶硅，然后通过光刻和反应离子蚀刻工艺构图MOSFET中部栅极导体，来形成该构图的中部栅极导体。
然后，该方法继续在中部栅极导体的侧壁上沉积导电扩散阻挡层，然后在中部栅极导体的侧壁上的导电扩散阻挡层上形成金属分隔物，在此之后剥离偏移膜以在底切区域上形成悬挂金属分隔物。
然后，该方法继续氧化在悬挂金属分隔物之下的中部栅极导体以防止在中部栅极导体与随后形成的左、右侧翼栅极导体之间形成整流结，然后沉积多晶硅层来填充悬挂金属分隔物之下的底切区域，在此之后通过各向同性蚀刻去除多晶硅层，同时在悬挂金属分隔物之下的底切区域中保留多晶硅层，以形成左、右侧翼栅极导体。
然后，该方法继续通过形成源极和漏极延伸/晕圈和分隔物，然后在导体上形成自对准多晶硅化物而完成。在优选实施例中，中部栅极导体和左、右侧翼栅极导体优选地由掺杂多晶硅形成。
所述的方法提供了一种具有低栅极感应的泄漏(GIDL)电流的MOSFET器件，其包括源极扩散区、漏极扩散区和中部栅极。中部栅极包括中部栅极导体、左侧翼栅极导体和右侧翼栅极导体，其中左侧翼栅极导体和右侧翼栅极导体由薄的绝缘和扩散阻挡层与中部栅极导体分开。
中部栅极导体的左、右横向边缘可以与源极扩散区和漏极扩散区中之一重叠。左、右侧翼栅极导体的左、右横向边缘也可以与源极扩散区和漏极扩散区中之一重叠。
中部栅极导体与左、右侧翼栅极导体通过重叠金属侧壁导电层而搭接在一起。重叠金属侧壁导电层包括沿中部栅极导体的左、右侧壁形成的左、右金属侧壁分隔物，以防止在中部栅极导体与左、右侧翼栅极导体之间形成整流结。左、右侧翼栅极导体通过导电扩散阻挡层与中部栅极导体分开。
在左、右侧翼栅极导体之下的栅极绝缘体的厚度可以独立地确定，使得它可以比中部导体之下的栅极绝缘体的厚度更厚。
所述中部栅极导体由N+多晶硅形成，以形成高阈值电压的P型金属氧化物半导体场效应晶体管。所述中部栅极导体是P+多晶硅形成，以形成低阈值电压的P型金属氧化物半导体场效应晶体管。
尽管本文对于本发明的低GIDL MOSFET及其制备方法的一些实施例和变形进行了详细地说明，但是应当清楚的是，本发明的公开内容和教导将对本领域的技术人员提示多种可选的设计。
工业实用性
本发明总体上对于电子器件，更确切地说，对于低GIDL MOSFET结构具有工业实用性。

Claims (17)

1.一种金属氧化物半导体场效应晶体管器件(90)，所述金属氧化物半导体场效应晶体管器件提供了低栅极感应的漏极泄漏电流，包括：
源极扩散区(88)、漏极扩散区(88)和中部栅极(10)；
所述中部栅极包括中部栅极导体(10)、沿所述中部栅极导体的左、右侧壁形成的左、右金属侧壁分隔物(32)、所述左、右金属侧壁分隔物下的左侧翼栅极导体(70)和右侧翼栅极导体(70)，其中，所述左、右金属侧壁分隔物中的每一个都由导电扩散阻挡层(30)与所述中部栅极导体分开。
2.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述中部栅极导体的左、右横向边缘分别与所述源极扩散和漏极扩散区域重叠。
3.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述左侧翼栅极导体的左横向边缘和右侧翼栅极导体的右横向边缘分别与所述源极扩散和漏极扩散区域重叠。
4.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述中部栅极导体与所述左、右侧翼栅极导体通过所述左、右金属侧壁分隔物搭接在一起。
5.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述左侧翼栅极导体和右侧翼栅极导体之下的栅极绝缘体的厚度大于所述中部栅极之下的栅极绝缘体的厚度。
6.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述左侧翼栅极导体和右侧翼栅极导体中每一个都由薄的绝缘和扩散阻挡层(50，52)与中部栅极导体分开，以防止在所述中部栅极导体与所述左侧翼栅极导体和右侧翼栅极导体之间形成整流结。
7.根据权利要求1的金属氧化物半导体场效应晶体管器件，包括N型金属氧化物半导体场效应晶体管器件，其中所述左侧翼栅极导体和右侧翼栅极导体中每个都是由N+多晶硅形成。
8.根据权利要求1的金属氧化物半导体场效应晶体管器件，包括P型金属氧化物半导体场效应晶体管器件，其中所述左侧翼栅极导体和右侧翼栅极导体中每个都是由P+多晶硅形成。
9.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述中部栅极导体由P+多晶硅形成，以形成高阈值电压的N型金属氧化物半导体场效应晶体管。
10.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述中部栅极导体由N+多晶硅形成，以形成低阈值电压的N型金属氧化物半导体场效应晶体管。
11.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述中部栅极导体由N+多晶硅形成，以形成高阈值电压的P型金属氧化物半导体场效应晶体管。
12.根据权利要求1的金属氧化物半导体场效应晶体管器件，其中，所述中部栅极导体是P+多晶硅形成，以形成低阈值电压的P型金属氧化物半导体场效应晶体管。
13.一种制备低栅极感应的漏极泄漏电流的金属氧化物半导体场效应晶体管器件(90)的方法，包括：
在经构图的中部栅极导体(10)和周围衬底(12)区域的水平表面上形成偏移膜(20)；
在所述中部栅极导体上沉积导电扩散阻挡层(30)；
在所述中部栅极导体的侧壁上的导电扩散阻挡层之上形成金属分隔物(32)；
剥离所述偏移膜(20)来在底切区域(40)上形成悬挂金属分隔物(32)；
氧化在所述悬挂金属分隔物(32)之下的中部栅极导体以防止在所述中部栅极导体和随后形成的左、右侧翼栅极导体(70)之间形成整流结；
沉积多晶硅层(60)以填充所述悬挂金属分隔物下的底切区域；
通过各向同性蚀刻去除所述多晶硅层，同时在所述悬挂金属分隔物之下的底切区域(70)中保留多晶硅层以形成左、右侧翼栅极导体。
14.根据权利要求13的方法，其中，在所述去除步骤之后，形成源极和漏极延伸/晕圈和分隔物，然后在中部栅极导体上形成自对准多晶硅化物。
15.根据权利要求13的方法，其中，经构图的中部栅极导体是通过在栅极电介质覆盖的衬底上沉积多晶硅，然后通过光刻和反应离子蚀刻工艺构图中部栅极导体来形成的。
16.根据权利要求13的方法，还包括使用各向异性电介质沉积来在所述经构图的中部栅极导体和周围衬底区域的水平表面上形成偏移膜。
17.根据权利要求13的方法，还包括形成掺杂多晶硅的中部栅极导体和左、右侧翼栅极导体。
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ATE551727T1 (de) 2012-04-15
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US20040137689A1 (en) 2004-07-15
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US6841826B2 (en) 2005-01-11
KR100754305B1 (ko) 2007-09-03
JP4678875B2 (ja) 2011-04-27
WO2004066367A3 (en) 2009-05-28
CN101410951A (zh) 2009-04-15
TWI270145B (en) 2007-01-01
TW200504887A (en) 2005-02-01
US6878582B2 (en) 2005-04-12
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