TWI269405B - MOS transistor and method for fabricating the same - Google Patents

MOS transistor and method for fabricating the same Download PDF

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TWI269405B
TWI269405B TW091138012A TW91138012A TWI269405B TW I269405 B TWI269405 B TW I269405B TW 091138012 A TW091138012 A TW 091138012A TW 91138012 A TW91138012 A TW 91138012A TW I269405 B TWI269405 B TW I269405B
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TW200307347A (en
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Yong-Sun Sohn
Chang-Woo Ryoo
Jeong-Youb Lee
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Hynix Semiconductor Inc
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    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
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Description

1269405 許多η-型雜質而被束縛，然而，nMOS電晶體之短通道特性 係被降低。同時，當η型雜質以最小限度的增加數量做離 子植入，以增加nMOS電晶體之驅動電流’臨限電壓VT係 動態地增加，且驅動電流降低。因此，減少M0S電晶體之 閘極長度成爲CMOS電晶體製造製程中的一項限制。 爲克服上述之問題，另一項傳統CMOS電晶體之製造方法 係由Takashi Hori et al.導入之”具有傾斜植入衝_貫 穿停止層之0.1微米CMOS技術（TIPS)“ IDEM，1 994 (後文 中稱作Takashi).該Takashi教導製造具約〇·1微米閘 極長度之CMOS電晶體的方法。該Takashi之方法單獨地施 行離子植入以形成表面通道nMOS電晶體的衝擊停止結構， 及藉使用不同遮罩之埋入通道PM0S電晶體。 第2圖係爲解釋Takashi之CMOS電晶體形成製程的CMOS 電晶體剖面圖。 參照第2圖，閘極氧化物層25和閘極電極26，係形成 於半導體基板24上，且間隔27係形成於閘極電極26之兩 個橫向側。LDD區域28係形成於nMOS電晶體區域中閘極 電極26之兩側邊緣。n +源極/汲極區域係藉接觸LDD區域 28而形成，且p-型衝擊停止層30係藉施行硼之傾斜離子 植入於LDD區域28之底部而形成。在pMOS電晶體區域中 ，P +源極/汲極區域3 1係形成，且η -型衝擊停止層3 2係 藉傾斜離子植入硼於Ρ +源極/汲極區域3 1之一側上而形成 〇
Atsuki Hori et al·導入製造CMOS電晶體之另一項方 1269405 法，其係爲”藉5keV離子植入和快速熱回火製造而具有極 淺溝槽源極/汲極接面之0.05微米CMOS “ IEDM，1 994 (後 文中稱作Atsuki)。該Atsuki法教導製造nMOS電晶體和 PM0S電晶體，藉使用自對齊袋式植入（SPI )而具有0 . 5奈 米（nm)之閘極，及源極/汲極擴張（SDE)。 第3圖係解釋Atsuki形成製程之CMOS電晶體面圖。 參照第3圖，閘極氧化物層34及閘極電極35係形成於 半導體基板33之上。同時，間隔36係形成於閘極電極35 之兩橫向側。n +型源極/汲極區域38A，係藉接觸源極/汲 極擴張區域37A而形成。p-型自對齊袋式植入層係n +源極 /汲極擴張區域3 7 A傾斜植入硼而向下形成。η -型自對齊袋 式植入層39Β和Ρ +源極/汲極擴張區域37Β，係形成於pMOS 電晶體中閘極電極35之兩側邊緣。p +型源極/汲極區域38B 係藉接觸P +源極/汲極擴張區域3 7B和η-型自對齊袋式層 39Β而形成。 如上所述’ Atsuki及Takasi提供nMOS電晶體及pMOS 電晶體之最佳化特性之方法。 然而’該等方法係對每一 nMOS電晶體區域及pMOS電晶 體區域使用不同遮罩。額外製程，如LDD摻雜製程及源極/ 汲極擴張區域製程係形成。結果，製造製程之複雜度增加 ’且製造費用同時增加。因此，上述之方法於製造半導體 記憶裝置是不適合的。 特別地’若At uski法，砷係用於形成nM〇S電晶體之源 極/汲極擴張區域。結果，當nMOS電晶體用於週邊電路之 1269405 型源極/汲極區域之底部上而形成；第二衝擊停止層藉接觸 p型源極/汲極區域之一側及間隔之底部上而形成；第三衝 擊停止層藉接觸η型源極/汲極區域之一側而形成；源極/ 汲極擴張區域藉接觸η型源極/汲極區域之一側及間隔之底 部上而形成；及一微量摻雜汲極（LDD)區域係圍繞源極/汲 極擴張區域。 · 依照本發明之另一項觀點，其係同時提供一種製造CMOS 電晶體之方法，包括：a )形成η型井區域於半導體板內；b ) 形成η型衝擊停止層於η型井內；c)形成p型井區於η型 井區內；d)同時形成第一 η型LDD區域於ρ型井區內，及 第二η型衝擊停止層藉離子植入雜質至閘極電極當作遮罩 ;e )形成一較第一 LDD區域群中之一第一 LDD區域具有高 濃度雜質之η型源極/汲極擴張區域。f )形成一圍繞源極 /汲極擴張區域之第二η型LDD區域；g)形成一間隔於閘極 電極之一側；h)形成接觸第一衝擊停止層和第二衝擊停止 層之P型源極/汲極區域；及i )形成接觸源極/汲極擴張區 域及第一和第二LDD區域之η型源極/汲極區域。 (四）實施方式 第4圖係依照本發明較佳實施例之CM0S電晶體的剖面圖 9 參照第4圖，一閘極氧化物層5 2 A係形成於半導體基板 4 1之nMOS區和pMOS區上，且一閘極圖樣係藉依序堆疊一 多矽晶層5 3，一金屬層5 4和一硬式遮罩層5 5，形成於閘 極氧化物層5 2 A上。一橫向氧化物5 6係形成於多矽晶層5 3 1269405 之橫向側，及一氮化物間隔5 7 A係形成於閘極圖樣之周圍 ，且接觸至閘極氧化物層52A。一氧化物間隔64A係形成 於氮化物間隔5 7 A之兩側。 在pMOS區域中之P +源極/汲極區域65及在nMOS區域中 之η +源極/汲極區域66，係藉由對齊氧化物間隔64之邊緣 而形成。第一 η-型衝擊停止層46，係藉彼此堆疊形成於ρ + 源極/汲極區域6 5的底部之下，及第二η -型衝擊停止層5 8 係形成於Ρ +源極/汲極區域6 5的一側上。一 ρ -型衝擊停止 層61係形成於η +源極/汲極區域66的一側上。 一 η +源極/汲極擴張區域62，係藉接觸η +源極/汲極區 域6 6的一側，及延伸至鬧極圖樣之一側而形成。一第二L D D 區域63係圍繞η +源極/汲極擴張區域62。 如第4圖所示，第二LDD區域6 3係藉多次摻雜相同雜質 而具又多層結構。η +源極/汲極擴張區域6 2和第二LDD區 域63係爲電氣導體之相同雜質摻雜層且具有不同擴張率。 第二LDD區域63.擴張較η +源極/汲極擴張區域62爲快。η + 源極/汲極擴張區域62係爲砷摻雜層，且第二LDD區域63 係爲磷摻雜層。第二LDD區域6 3之雜質濃度，係較n +源 極/汲極區域66和n +源極/汲極擴張區域62之雜質濃度爲 低。 第5A至5F圖係解釋依本發明較佳實施例之製造CMOS電 晶體方法的CMOS電晶體剖面圖。 如第5A圖所示，一裝置隔離層43係形成於半導體之基 板41上。矽局部氧化技術（L0C0S)或淺溝隔離技術（STI )係 1269405 被使用，以形成裝置隔離層43。 在形成裝置隔離層43後，第一遮罩43係形成。第一遮 罩4 3藉塗佈光敏薄膜於基板4 1上及經由曝光和顯影製程 圖樣·化光敏薄膜，而開放PM0S區域。在形成第一遮罩43 · 後，η -型井44和η -型p -通道堆砌停止層4 5，係藉植入磷 . 離子於pMOS區域上而依序形成。 再者，第一 η-型衝擊停止層46係藉離子植入如砷、銻 等較重離子種之η-型雜質，而形成於pMOS區域上，齊係 位於pMOS區域之通道形成區域的底部。在形成第一 η-型 衝擊停止層46後，ρ-型ρ-通道離子植入層47係藉植入離 子Ρ型雜質於導體基板41之下，以控制pMOS電晶體之臨 限電壓（threshold voltage)。 η-型井44之離子植入深度係爲最深，且η-型ρ-通道堆 砌停止層45、第一 η-型衝擊停止層46及ρ-型ρ-通道離子 植入層47之植入深度依順序而較淺。 如第5Β圖所示，在移除第一遮罩43後，第二遮罩4δ藉 塗佈光敏薄膜於pMOS區域以外之基板41上及經由曝光和 顯影製程圖樣化光敏薄膜，而開放nMOS區域。 再者，P-型雜質係藉使用第二遮罩層48,植入離子至開 · 放之nMOS區域以依序形成ρ-型井49和ρ-型η-通道場停 · 止層50。在形成ρ型η-通道場停止層50後，ρ-型η-通道 離子植入層51係藉植入離子ρ型雜質於導體基板41之下 ，以控制nMOS電晶體之臨限電壓（threshold voltage)。 P-型井49之離子植入深度係爲最深，且ρ-型η-通道場 - 14- 1269405 停止層5 0及p -型η通道離子植入層5 1之植入深度依順序 而較淺。 如第5C圖所示，在移除第二遮罩48後，閘極氧化物層 52係形成於半導體基板41上。上述閘極氧化物層52、多 晶矽層5 3、金屬層5 4和硬式遮罩5 5矽依序堆疊。 再者，硬式遮罩5 5、金屬層5 4和多晶矽層5 3係藉同時 使用閘極遮罩（未顯示）而圖樣化，或在硬式遮罩5 5首先圖 樣化後，金屬層54和多晶矽層53同時形成。 金屬層54和多晶矽層53之閘極電極，可以是多單一多 晶矽層，；然而多晶矽層和金屬層之堆疊層係用於高速操作 和低電阻率之電極。擴散阻障層、鎢之堆疊層如氮化鎢/鎢 (WN/W)及氮化鈦/鎢（TiN/W)和鎢矽化物，係用來作爲金屬 層5 4 〇 再者，閘極再氧化製程係施行，係藉用於閘極圖樣之飩 刻製程以恢復閘極氧化物層52之損傷。在閘極再氧化製程 後，因多晶矽層5 3之橫向側被氧化，而氧化物（後文中稱 橫向氧化物）形成於多晶矽層5 3之兩橫向側。 閘極再氧化製程係恢復在蝕刻閘極圖樣時之微小溝痕和 閘極氧化物層52之損失，及氧化閘極氧化物層52上保留 之蝕刻殘餘。同時，在閘極圖樣邊緣之閘極氧化物層5 2的 厚度，係增加以增加可靠度。 在閘極再氧化製程後，氮化物層5 7係形成於整個結構之 表面。氮化物層57和橫向氧化物56，係構成偏移間隔。 再者，第二η-型衝擊停止層58係形成於pMOS區域上， 1269405 且第一 LDD區域59係同時藉離子植入η-型雜質，於無光 罩處理的氮化物層5 7的整個表面而形成。 如第5D圖所示，第三遮罩60之形成，係藉塗佈光敏薄 膜於磷離子已植入於其上的上部結構整個表面上，且經由 曝光和顯影製程圖樣化光敏薄膜。第三遮罩60開放nM0S 區域且關閉pMOS區域。在形成第三遮罩60後，nMOS電晶 體之P -型衝擊停止層61之形成，係藉由傾斜角度摻雜p · 型雜質於經由第三遮罩60所露出的nMOS區域上。p-型衝 擊停止層6 1係位於第一 LDD區域之下方。 參照第5E圖，n +型源極/汲極擴張區域62，係藉未移除 第三遮罩60時離子植入高濃度的砷而形成。第二LDD區域 63係藉離子植入磷而形成。 第二LDD區域63之深度，係和第一 LDD區域59相同或 較淺，且較n +型源極/汲極擴張區域62爲深。第一 LDD和 第二LDD區域之雜質濃度係很低。
因第一 LDD區域59和第二LDD區域63係相同，第一 LDD 區域5 9之解釋在此省略，而第二LDD區域6 3之解釋如下 〇 最後，第二LDD區域63具有包圍η +型源極/汲極擴張區 域62之組態。 此時，磷之離子植入，係以具有90。或在兩方向或多重 植入方向以0°至15°之較低之傾斜角度。藉合倂上述兩項 方法而離子植入磷亦爲可能。 參照第5F圖，在除第三遮罩60後，氧化物層係沉積於 1269405 整個表面上。氧化物層64係藉蝕刻表面而形成於整個表面 上。此時，氮化物層和閘極氧化層係同時蝕刻，且保留當 作氮化物層間隔5 7 A和閘極氧化層5 2 A。 再者，源極/閘極區域係藉使用另一遮罩於各電晶體區域 上而形成。例如，P +源極/汲極區域65係藉離子植入高濃 度P-型雜質而形成，且n +源極/汲極區域66係藉離子植入 高濃度η -型雜質而形成。 第6Α至6G圖係解釋依本發明另一較佳實施例之製造 CMOS電晶體方法的CMOS電晶體剖面圖。第6Α至6G圖亦 顯示，若DRAM和CMOS電晶體形成於週邊電路I I上，nM0S 電晶體形成於單胞區域I上。 此後，在單胞區域I上pMOS電晶體之區域係爲單胞區。 在週邊電路I I上pMOS電晶體之區域係爲pMOS區域，及在 週邊電路I I上nMOS電晶體之區域係爲nMOS區域。 參照第6A圖，單胞區域I和週邊電路單元丨I係在單胞 區域I和週邊電路單元II已定義的半導體基板71上隔離 。裝置隔離層72係形成以隔離各單位元件。L0C0S法和STI 法可被用於形成裝置隔離層72。 再者，光敏層係塗佈在半導體基板71上，且藉曝光和顯 影製程圖樣化，以形成露出週邊電路單元II中pM〇s區域 的第一遮罩73。p通道場停止層75係藉離子植入n型雜質 磷而形成。在第一遮罩73形成後，η-型井74和η-型ρ-通 道場停止層7 5係藉離子植入η型雜質磷而形成。 較重離子種之η型雜質，如砷、銻，係離子植入至pM〇s 1269405 區域，以形成第一 η -型衝擊停止層76。在形成第一 η -型 衝擊停止層76後，ρ-型ρ通道離子植入層77係藉離子植 入Ρ型雜質形成於板導體基板71表面之下，以控制PM0S 電晶體之臨限電壓。 ， η型井74之離子植入深度係爲最深，且離子植入深度依 η-型ρ-通道場停止層75、第一 η-型衝擊停止層76和ρ-型 Ρ通道離子植入層7 7之順序而變淺。 參照第6Β圖，在移除第一遮罩層73後，第二遮罩層78 形成於除了 pMOS區域外的半導體基板71上，其係藉塗 佈光敏薄膜於基板上及經由曝光和顯影製程圖樣化光敏薄 膜。亦即，第二遮罩層78露出週邊電路單元II之單胞區 域I和nMOS區域， 再者，一 ρ型井79和ρ型η通道場停止層80，係藉離 子植入Ρ型雜質於第二遮罩層7 8所露出的單胞區域I和 nMOS區域而形成。！>型η通道離子植入層81係藉離子植入 Ρ型雜質而形成，以控制nMOS電晶體之臨限電壓。ρ型井 之離子植入深度係爲最深，且離子植入深度依ρ型η通道 場停止層8 0、ρ型η通道離子植入層8 1順序而變淺。 參照第6C圖所示，在移除第二遮罩層78後，第三遮罩 · 層82形成係藉塗佈光敏薄膜及經由曝光和顯影製程圖樣化 -光敏薄膜。第三遮罩層82露出之單胞區域I。在形成第三 遮罩層8 2後，臨限電壓控制層8 3係藉離子植入ρ型雜質 於露出之單胞區域I而形成，以控制單胞電晶體之臨限電 壓。 -18 - 1269405 參照第6D圖，在移除第三遮罩層82後，閘極氧化物層 84係形成於半導體之基板71上。多晶矽層85，金屬層86 和硬式遮罩87係堆疊於閘極氧化物層84之上。 聞極圖樣係藉由依序堆暨多晶砂層85’金屬層86和硬 式遮罩87而形成。多晶矽層85，金屬層86和硬式遮罩87 係藉使用閘極遮罩（未顯示）而同時圖樣化，或硬式遮罩8 7 先圖樣化，而多晶矽層85和金屬層86同時圖樣化。 包括多晶矽層85和金屬層86之閘極電極，可以是多單 一多晶矽層；然而多晶矽層和金屬層之堆疊層係用於高速 操作和低電阻率之電極。擴散阻障層、鎢之堆疊層如氮化 鎢/鎢（WN / W )及氮化鈦/鎢（T i N / W )和鎢矽化物，係用來作爲 金屬層。 再者，閘極再氧化製程係施行，係藉用於閘極圖樣之蝕 刻製程以恢復閘極氧化物層52之損傷。在閘極再氧化製程 後，因多晶矽層8 3之橫向側被氧化，而氧化物（後文中稱 橫向氧化物）形成於多晶矽層83之兩橫向側。 閘極再氧化製程係恢復在蝕刻閘極圖樣時之微小溝痕和 閘極氧化物層84之損失，及氧化閘極氧化物層84上保留 之蝕刻殘餘。同時，在閘極圖樣邊緣之閘極氧化物層84的 厚度，係增加以增加可靠度。 在閘極再氧化製程後，氮化物層89係形成於整個結構之 表面。氮化物層8 9和橫向氧化物88，係建構成第一偏移 間隔。 再者，第二η -型衝擊停止層90係形成於週邊電路單元11 - 19 - 1269405 的pMOS區域上，且在週邊電路單元II中nMOS區域上的第 一 LDD區域92和單胞電晶體的LDD區域91係同時藉離子 植入如磷之η型雜質，於無光罩處理的氮化物層89的整個 表面而形成。 如第6Ε圖所示，第四遮罩93之形成，係藉塗佈光敏薄 膜於磷離子已植入於其上的上部結構整個表面上，且經由 曝光和顯影製程圖樣化光敏薄膜。第四遮罩開放週邊電路 單元I I之nMOS區域且關閉pMOS區域和單胞電晶體區域。 在形成第四遮罩93後，nMOS電晶體之p型衝撃停止層94 係藉由傾斜角度摻雜P型雜質。P型衝撃停止層94係位於 第一 LDD區域92之下方。 參照第6F圖，n +型源極/汲極擴張區域95，係藉未移除 第四遮罩9 3時離子植入高濃度的砷而形成。第二LDD區域 9 6係藉離子植入磷而形成。 第二LDD區域96之深度，係和第一 LDD區域92相同或 較淺，且較n +型源極/汲極擴張區域95爲深。第一 LDD和 第二LDD區域之雜質濃度係很低。
因第一 LDD區域92和第二LDD區域96係相同，第一 LDD 區域9 2之解釋在此省略，而第一 LDD區域9 6之解釋如下 〇 最後，第二LDD區域96具有包圍n +型源極/汲極擴張區 域9 5之組態。
此時，磷之離子植入，係以具有90。或在兩方向或多重 植入方向以0°至15°之較低的傾斜角度，以形成第二LDD 基板 裝置隔離層 第一遮罩 η-型井 η-型ρ-通道場停止層 η-型ρ-通道場停止層 Ρ -型Ρ -通道離子植入層 第二遮罩 Ρ型井 Ρ型通道場停止層 Ρ -型η -通道離子植入層 第三遮罩 臨限電壓控制層 閘極氧化物層 多晶矽層 金屬層 硬式遮罩 橫向側氧化物 氮化物層 第二η ·型衝擊停止層 LDD區域 第一 LDD區域 第四遮罩 Ρ -型衝擊停止層 -24- 1269405 95 n + 型 源 極 /汲 極 擴 張區域 96 第 二 LDD 層 97 氧 化 物 間 隔 98 P + 型 源 極 /汲 極 丨品 域 99 P + 型 源 極 /汲 極 域 100 P + 型 源 極 /汲 極 區 域
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Claims (1)

1269405 次年夕月S/曰修(*#)正替換頁 拾、申請專利範圍 ^ ^ 八譬入 ~一·’ 第9 1 1 3 80 1 2號「金屬氧化物半導體（M0S)電晶體及其製造 方法」專利案 ( 2006年3月修正） 1 · 一種半導體，包括： 一閘極電極和一閘極氧化層於半導體基板上； 間隔係形成於該層之側面； 一第一傳導型源極/汲極區域形成於半導體基板內之間 隔之邊緣； 一第二傳導型衝擊停止層，形成於在半導體基板上第 一傳導型源極/汲極區域之間的區域； 一第一傳導型源極/汲極擴張區域佔據，自第一傳導型 源極/汲極區域至閘極電極兩側之擴張區域；和 一第一傳導型微量摻雜閘極（LDD )區域，係緊鄰源極/ 汲極區域且圍繞源極/汲極擴張區域，其中第一傳導型LDD 區域之接合深度係藉由衝擊停止層所束縛。 2 .如請專利範圍第1項之半導體，其中第一傳導型LDD區 域和第一傳導型源極/汲極區域及第一傳導型源極/汲極 擴張區域比較，係具有較低雜質濃度。 3 .如請專利範圍第1項之半導體，其中第一傳導型源極/汲 極擴張區域之厚度’係較第一傳導型源極/汲極區域爲 薄，且之深度，係較第一傳導型源極/汲極擴張區域爲深， 且較第一傳導型源極/汲極擴張區域爲薄。 4 .如請專利範圍第1項之半導體’其中第一傳導型LDD區 -1- 1269405 域係具有至少一種圍繞第一傳導型源極/汲極擴張區域的 雙重結構。 5 ·如請專利範圍第1項之半導體，其中進一步包括： 一第二傳導型場停止層，其係較第二傳導型衝擊停止 層爲深；及 一第二傳導型井區域，其係較第一傳導型場停止層爲 深。 6 .如請專利範圍第1項之半導體，其中第一傳導型源極/汲 極擴張區域和第一傳導型LDD區域係具有不同擴張速率 之傳導型雜質摻雜層，且在第一傳導型LDD區域中雜質 之擴散速率係較快。 7 .如請專利範圍第6項之半導體，其中砷係被植入第一傳 導型源極/汲極擴張區域，且磷係被植入第一傳導型LDD 區域。 8 . —種半導體裝置，包括： 一具有nMOS區和pMOS區之半導體基板； 一閘極電極及一閘極氧化層形成在每一nMOS區和 p Μ 0 S區之上； 間隔係接觸至該層之側面； 一 Ρ型源極/汲極區域藉排列在間隔之邊緣，形成於 pM〇S區域內； 一 η型源極/汲極區域藉排列在間隔之邊緣，形成於 nMOS區域內； 一第一衝擊停止層藉重疊ρ型源極/汲極區域之底部上 -2 - 1269405 而形成； · 一第二衝擊停止層藉接觸p型源極/汲極區域之一側及 間隔之底部上而形成； _ 一第三衝擊停止層藉接觸η型源極/汲極區域之一側而 形成； 一源極/汲極擴張區域藉接觸η型源極/汲極區域之一 側及間隔之底部上而形成；及 一微量摻雜汲極（LDD )區域係圍繞源極/汲極擴張區 域。 每 9 .如請專利範圍第8項之半導體裝置，其中LDD區域係藉 多次摻雜相同雜質而具有多層結構。 1 〇 .如請專利範圍第8項之半導體裝置，其中源極/汲極擴張 區域和LDD區域係具有不同擴張速率之傳導型雜質摻雜 層，且在第一傳導型LDD區域中雜質之擴散速率係較快。 1 1 .如請專利範圍第8項之半導體裝置，其中砷係被植入第 一傳導型源極/汲極擴張區域，且磷係被植入第一傳導型 LDD區域。 拳 1 2 ·如請專利範圍第8項之半導體裝置，其中LDD區域之雜 質濃度和η型源極/汲極區域及源極/汲極擴張區域比較 係較低。 1 3 .如請專利範圍第8項之半導體裝置，其中第一衝擊停止 層係爲砷摻雜層，且第二衝擊停止層係爲磷摻雜層。 14 . 一種製造CMOS電晶體之方法，包括： a )形成一 η型井區域於半導體基板內； -3- 1269405 b) 形成一 η型衝擊停止層於η型井內； c) 形成一 ρ型井區於η型井區內； d) 同時形成第一 η型LDD區域於ρ型井區內，及第二η 型衝擊停止層藉離子植入雜質至閘極電極當作遮罩； e )形成一較第一 LDD區域群中之一第一 LDD區域具有高 濃度雜質之η型源極/汲極擴張區域 f )形成一圍繞源極/汲極擴張區域之第二η型LDD區域； g )形成一間隔於閘極電極之一側； h )形成一接觸第一衝擊停止層和第二衝擊停止層之p型 源極/汲極區域；及 i )形成一接觸源極/汲極擴張區域及第一和第二LDD區域 之η型源極/汲極區域。 1 5 ·如請專利範圍第！ 4項之方法，其中第二LDD區域之深度 係和第一 LDD區域相同或較深。 1 6 .如請專利範圍第丨4項之方法，其中進一步包括 j )形 成第一 p型衝擊停止層於第一 LDD區域形成後之第一 LDD 區域底部。 1 7 ·如請專利範圍第} 4項之方法，其中第一和第二LDD區域 之雜質濃度，較源極/汲極擴張區域相對爲低。 1 8 .如請專利範圍第1 4項之方法，其中第一和第二LDD區域 係藉(離子植入第一 η -型雜質而形成，且源極/汲極擴張 I 區域係藉離子植入第二η -型雜質而形成，其中第一 η -型 雜質較第二η -型雜質散播更快。 1 9 .如請專利範圍第1 4項之方法，其中第一 η -型雜質係爲 一4 一 1269405 磷，及第二η -型雜質係砷。 20 .如請專利範圍第1 4項之方法，其中第一衝擊停止層係藉 植入砷或銻而形成。 2 1 .如請專利範圍第1 4項之方法，其中步驟e )係以離子植 入磷至整個表面。
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US6879006B2 (en) 2005-04-12
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