TWI264061B - Strained silicon-on-insulator (SSOI) and method to form same - Google Patents
Strained silicon-on-insulator (SSOI) and method to form same Download PDFInfo
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- TWI264061B TWI264061B TW092133334A TW92133334A TWI264061B TW I264061 B TWI264061 B TW I264061B TW 092133334 A TW092133334 A TW 092133334A TW 92133334 A TW92133334 A TW 92133334A TW I264061 B TWI264061 B TW I264061B
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- 239000012212 insulator Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title abstract description 40
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 abstract description 16
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 3
- 230000001131 transforming effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 194
- 235000012431 wafers Nutrition 0.000 description 22
- 239000013078 crystal Substances 0.000 description 16
- 238000001953 recrystallisation Methods 0.000 description 12
- 238000002513 implantation Methods 0.000 description 9
- 238000000137 annealing Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
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- 241000894007 species Species 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000000348 solid-phase epitaxy Methods 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000238631 Hexapoda Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 206010036790 Productive cough Diseases 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- QWAUSPYZWIWZPA-UHFFFAOYSA-N [Co].[Bi] Chemical compound [Co].[Bi] QWAUSPYZWIWZPA-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- 210000003298 dental enamel Anatomy 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
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- -1 oxygen ions Chemical class 0.000 description 1
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- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Description
1264061 號,標題為「低缺陷密度/任意晶格常數之異型磊晶層」令 所述内容,二者皆引用併入本文。 由於SiGe應力鬆弛層為使^層應變所必需,故該層堆疊 不可用於製造絕緣體上石夕(siHc〇n-〇n_insulat〇r ; S〇j)之 M〇SFET。當今技術狀態,裝置通常在一半導體層中運作, 由一隔離層將該層與半導體基板隔開。該技術通常稱之為 soi技術。生產soi材料或晶圓的標準方法稱為SIM〇x程 序。其包括以尚能量將極高劑量的氧離子植入半導體中, 退火處理後,氧在半導體表面下形成一氧化層。以此方式, 其具有與大部分基板分離之半導體頂層。但除sim〇X2 外,還有其他生產SOI晶圓的方法,該等方法通常基於晶圓 焊接技術。
SiGe應力鬆弛層上的應變的矽層僅對製造大量裝置有 用大里.裝置不具有S〇1裝置可獲得的優點,如降低接面電 容,及消除裝置間的閉鎖路徑,如j-p· c〇Hnge所著的「絕 、、彖上砍技術· VLSI之材料」(1997年波士頓,Kiuwer學術 出版社第二版)中所詳述内容。 最 期望有一種在絕緣體上直接形成拉伸應變的s丨層之 技術如此可將S0I技術的優點與應變的矽所得到的增強移 動性結合起來。此外,a免除了SiGe用作裝置基板的相關 問題。例如,在SlGe上製造應變的矽之m〇sfet時,在 I比在純Si中形成二矽化鈷的溫度高,及摻雜劑擴散較多 係主要問題,如R.ADonat。#人發表在應用物理學雜諸第 期第⑶…⑼乃「在SiGeC/s々SiGe/Sw上形成石夕化
〇 '89\89466 D〇C 1264061 鈷」中所述。 一絕緣體上應變的矽層可藉由晶圓焊接與層轉移形成。 在一種稱為SmartCut(SOITEC公司的註冊商標)的方法中, 用氫植入具有在S iGe缓衝層上生長的應變矽層之第一晶 圓,然後反轉,並焊接至具有絕緣體層的處置晶圓,該方 法如A. J. Auberton Herve在「S0I :系統材料」(國際電子 裝置會議(IEDM)技術文摘第3至10頁,丨996年丨2月,舊金山) 中所述。對接合晶圓進行退火處理,以強固焊接,及在植 入氫的深度附近產生泡傷(blistenng)。因而應變的碎層及 部分SiGe緩衝層即與第一晶圓分離,並藉由焊接至處二晶 圓而轉移。該方法也有缺點。第―,焊接方法需進行晶圓 焊接與層轉移,其為成本高而產出極低的程序。第二,剛 沈積的SiGe表面太粗輪,只有非常光滑平坦的表面才能實 現晶圓谭接。因此,通常要料間較長的化學機械研磨 1 meehani吻。llshing; CMp)步驟,以降低表面粗 楼度,使之達到可接受的水準。第三,要獲得牢固的焊接, 需在1〇〇〇°C以上的溫度下退火處理晶圓。但是,如此高溫 ^使應變”層應力鬆弛,造成帥邮'«層擴散至應 變的石夕層中。帛四,因此而使用較低的退火溫度又可導致 可靠性的問題。第 收名枯 將虱植入81(^緩衝層的SmartCut程 序可能難以控制,& μ、^八 為4 ’刀虱3使3丨〇6層中遠離泡傷位置 的缺陷重新定位。 【發明内容】 蓉於上述問顯,士 π ___ 本备明揭示一種形成拉伸應變的SOI層的
O:\39\89466 DOC l264〇6l 方法,並揭示一拉伸應變的s〇I層之結構。 應注意,為簡明起見,本文 以— 文所述係針對拉伸應變的矽之 付义情形。雖然應變的矽因复出 ^色的特性令人特別感興 嗖,但熟悉技術人士會注意^, 〜J 球方法係通用的,可用於 其他半導體層,如SlGe、Sic、GaAs、τ ρ Τ 卜
InP、inGaAs 等,更 7般而言,該方法可擴展為改變應變狀態,可以定量方式 (例如增大層中的壓力與張力)及 >、 ’疋f生方式(例如從壓縮性轉 诱為拉伸應變)進行,且可在廣泛 ^ 〃之的材枓内施行此類應變改 變,而不僅在半導體中。 ☆在-絕緣體頂部上⑴層中產生拉伸應變的本發明基本内 令如下。先取具有Si應力鬆弛層的標準s〇I晶圓,其為技術 中熟知的結構。然後,在S1層的頂部形成―砂應力鬆弛 層’在SiGe層的頂部分具有一既定以濃度。術言吾「應力鬆 他」意謂-層基本上不受應變或應力,但能夠藉由假定其 晶格常數均衡而應力鬆弛。然而在實務中,不會是完全的 層鬆他(即丨00%應力鬆弛),實際的鬆弛量取決於鬆弛siGe 膜中應變所用的方法及膜的厚度。例如,在30% Ge生長於 矽上的SiGe膜中,報告有65%的應力鬆弛,且係藉由離子 植入及快速熱退火而鬆弛(H -j. Herz〇g等人在⑻年8月 IEEE電子裝置雜誌第485頁23(8)發表的「藉由取植入製備 的SiGe虛擬薄基板上之si/SiGen型MODFET」)。可藉由生 長具有均勻Ge濃度的擬晶SiGe層、植入氦或氫及退火處理 該薄膜,鬆弛應變來形成一 SiGe應力鬆弛層。或者,可藉 由生長具有分級Ge組成的厚SiGe層,來實現^(^應力鬆弛
〇 \,S9\89466 DOC 1264061 層。在後一情形令,與Sl層之介面處,以濃度相當低’其 晶格常數卻不比Si層晶格常數大很多,但因發現以以層頂 4的Ge,辰度較南,故此處與s丨晶格常數的失配可能較為明 顯。接著,藉由離子植入,使絕緣體頂部的Si應力鬆弛層 與SiGe應力鬆弛層的底部分非晶性化。以此方式,— / 1 Θ日 性材料之頂部上具有一單晶以^層。非晶性化之後,從 應力鬆弛層的結晶頂部分開始,藉由固相磊晶包括絕緣體 上的矽層之非晶性材料,使之重新結晶。重新結晶期間, 結晶SiGe在其與非晶性材料之介面點處的晶格常數必須與 之相適應。由於結晶/非晶性介面處的晶格常數大於s丨層晶 格常數,加之必須適應以以應力鬆弛層之頂部分的較大晶 私^數,因而重新結晶後的§丨層將會處於拉伸應變狀態。 一旦移除SiGe層,即可獲得絕緣體上拉伸應變的矽層。 產生絶緣體上拉伸應變的矽層之具體實施例可做若干變 更。 在本务明項替代性具體實施例中,重複進行非晶性及 固態磊晶程序,可使S0I層中逐漸產生應變。每重複一次, 刀、及S1 Ge層的非晶性部分隨之增大,因而可對Ge濃度越來 越咼的種晶開始進行重新結晶處理。從具有較高Ge濃度的 區或開始重新結晶,對SOI層進行連續重複應變,使之達到 較南的應變位準,從而獲得較大晶格常數。 在本發明另一項具體實施例中,在每次重新結晶後,移 除亚重新形成分級SiGe層,且每次皆以較高的Ge濃度重新 形成該層。每次重複皆使SOI層具有更高的應變位準。
〇 \S9^39466 DOC 10 1264061 本發明之目的係提出一種方法,藉此將拉伸應變引入絕 緣體上的矽層中。本發明的目的還係講授絕緣體上拉伸應 變的矽及其製造方法。本發明的另一項目的係講授包括一 絕緣體上拉伸應變的石夕層之電子系統。本發明的還一項目 的係講授用於改變支撐平臺頂部上結晶層應變狀態之方法 的一般性。 【實施方式】 圖1示思顯示絕緣體上的石夕晶圓之分層結構的斷面圖。取 此一晶圓為本發明之起始點。該晶圓係分層結構,其一埋 入Si〇2層150夾在Si基板160與單晶Si層100之間。Si層100 具有一第一晶格常數,其為Si的應力鬆弛晶格常數。s〇I 晶圓為技術中已知,並且已經商用化。通常其藉由植入氧 分離(separation by implanted oxygen ; SIMOX)或晶圓烊接 之類技術製造而成。Si層100的厚度可變化。先進裝置的製 造要求結構越來越薄。而且,S i層越薄,其可承受的應變 越大’而不會犧牲結晶品質。因此,以層1〇〇的厚度範圍約 介於1 nm與1〇〇 nm之間,最好介於2 nm,50 之間。在執 行本發明步驟期間,不必改變該厚度。 圖2不意顯示具有形成於絕緣體上的矽晶圓之頂部上的 SiGe應力鬆弛層uo之分層結構的斷面圖。通常此一以&應 力鬆弛層具有一 Ge分級濃度。層11〇中Ge濃度的特徵性分級 將在層之底部具有約5% Ge,在此其形成與s丨層的第一介 面,還有約3〇%GeSSlGe層的頂表面。形成此類以^應^ 鬆弛層的方法係技術中已知。其有若干種製造浐序可用 0 \89\S0466 D0C -11 - 1264061 如LeGoues等人所持有的美國專利案第5,659,1 87號中所述 的逐步分級程序,其已併入本文。提及的一替代程序係植 入與退火辛王序,如S。H, Christiansen等人在2002年4月3日申 請的美國專利申請案第10/Π 5 160號「藉甴離子植入與熱退 火形成絕緣體上矽基板上之SlGe應力鬆弛層」(檔案律師號 YOR9200 1 0546US2),及2002年11月19日申請的美國專利申 請案第1 0/299880號(檔案律師號Y〇R92〇〇1〇546lJS3)中所 述,一者皆以提及方式併入本文。應注意,藉由He植入與 退火程序製造的SiGe應力鬆弛緩衝層100包含一缺陷區 域。在本發明中,以^層中的缺陷區域並不是個問題,因 其在本發明的植入步驟中非晶性化。
SiGe應力鬆弛層11〇的厚度範圍可相對較寬,其取決於^ 層1 00中所需的應變量及形成層1丨〇的方法。逐步分級方法 通常要求較厚的層,可高達約3000 nm,而其他方法,如植 入與退火程序,層110的最小厚度約為2〇 ηιη即可完成程序。 圖J示思顯示植入分層結構的斷面圖。將⑴層丄〇〇與 層11 0的底部分轉化為非晶性材料狀態係離子植入(以箭頭 2 00表不)的目標。植入種類通常為s丨或Ge,但熟悉技術人 士會認識到其他種類也可用於此目的。選擇植入能量與劑 量’使SiGe緩衝層11〇的底部分與501層} 00成為非晶性狀 態。 圖4示意顯示Si及SiGe應力鬆弛層之底部分非晶性化之 分層結構的斷面圖。植入200之後’ SiGe緩衝層丨1〇,的底部 分與SOI層1〇〇,非晶性化。加了符號「撇」的記號表示當此
〇 \89\89466 00C 1264061 寻為先河的相同層時’其材料狀態發生變化(對於s[Ge層僅 為部分變化’因其僅部分非晶性化)。非晶性丰導體層的擴 啟.以大括唬4 1 0表不。在S i. Ge層中,非晶性區域從與§丨層的 介面(第一介面)向上至第二介面,其介於义&層的非晶性與 結晶部分之間。SiGe層的頂部分未非晶性化,保持單晶狀 態。 圖5不意顯示藉由固相磊晶重新結晶的初始階段之斷面 圖。當結構受到退火處理時,分層結構41〇的非晶性部分收 縮。重新結晶生長(以箭頭51〇表示)從第二介面上其初始 種晶位置向下傳播,在該第二介面,Si.Ge結晶層具有第二 曰曰“數’其大於Si層的第一晶格常數。如圖5所示,部分
SiGe層110及31層1〇〇’仍為非晶性狀態。現在層的結晶 Η刀向下擴展σ在分級膜的情形中,結晶$⑷e層不 再應力鬆弛,且呈有箓-八二以n /、 —;丨面的日日格常數。因此,應變的 結晶SiGe層標注為層52〇。 圖6示意顯示重新έ士曰 _ 夏新、,,°曰曰佼之分層結構的斷面圖,其中Si層 已後得一拉伸應變。SiGe^ 曰 3的非日日性部分現受到應變,其 以才日正個層的新桿注5 9 〇 .- " 一曰於A主、0表不。在該圖中,迫使Si層符合第 應變的碎刚。至此^其已成為絕緣體上拉伸 變的方法。… 在絕緣體切層中引入拉伸應 ^ ^ ^^ 豕用凌置與電路的絕緣體上的 夕曰必須攸應變的^層 為技術中已知,通常…,層。此類移除方法 ™實現 勾勻Ge展度的SiGe應力鬆弛
vggv89466 DOC 1264061 二/、.向I擴展至SlGe/Si介面(藉由植入與退火方法形成 节及力I ?一層日守,逋常為此情形)’使用選擇性s iGe蝕刻 Μ尤為有用。封於分級SiGe緩衝層,有時最好在8丨以/5丨介 面併入—巾止㈣層或彳m如,料㈣雜(b〇r〇n delta-doping)有時用作濕式與乾式蝕刻的中止蝕刻層。 圖7示意顯示具有應變的以層之絕緣體上硬晶圓的斷面 圖。應變的3心層520已移除,使應變的以層_曝露於表 面上。Si層600黏附於絕緣體層15〇,其通常為一si〇2層。 拉伸應變的具有低缺陷密度的裝置品質,其值低於 l〇8/cm2,最好低於 i〇5/cm2。 該分層結構顯示出用離子植入200實現非晶性的效果。當 SW 100完全非晶性時’則因植入離子的自然擴散,一些離 子會滲入絕缘體層。此等離子會永久保持在絕緣體中^ 媒有害的電效應,但可顯示出在絕緣體中。有若干方式可 顯示其存在,一種方式係絕緣體(通常為S1〇2)甲存在植入種 類會略為改變其化學組成。因植入的離子,絕緣體層含有 超出-限度的至少-原子種類,職度可基於絕緣二的 已知化學組成而建立。例如,若絕緣體為Si〇2且植入的秤 類也為Sl,則根據調查,與基於以〇2化學公式所預期的^ 然S丨量相比,Si〇2中會顯示有過量的Si。 本發明iSi層發生應變而形成的應變的s〇i分層結構已 出現在初始SOI晶圓上,其並未涉及一層轉移。因此,初始 si層的結P向在整個應變程序中受到保護。若初始^層: 絕緣體下的基板有相同的結晶方向,其為已用SIM0X二序
0 A89VS9466 D0C 1264061 形成初始s〇I晶圓的情形’則最後所得應變的si層也將匹配 其下部S丨基板的結晶方向。 視情況,可在不同具體實施例令執行拉伸應變一S0I層的 方法。在此-具體實施例中,其旨在漸進調整以層與下部 絕緣體之間的匹配’至少重複—次轉化與重新結晶步驟, 但也可重複若干次。在本方法的該項具體實施例中,達到 圖6所示之分層結構的狀態後,回到圖3的離子植入,之後 進行圖5的重新結晶。其完成方式料次重複,就有更大部 分SiGe㈣為非晶性材料。以此方式,在用作固相重新結 晶之種晶表面的第二介面,第二晶格常數隨每次重複增 大’错此Si層巾的拉伸應變也隨每:欠重複增大。當^層中的 拉伸應4達到預$或所需值時,重複過程終丨,並將 應力鬆弛層移除。 在另一項具體實施例中,其旨在增大應變而不必形成過 厚的SlGe層,也係出於一般可撓性的緣故,至少重複一次 形成、轉化、重新結晶及移除步驟,但也可重複若干次。 每一移除步驟都會重新得到一 S0I晶圓,並準備再次進行處 理。在本方法的該項具體實施例中,達到圖7所示之分層結 構的狀態後,回到形成siGe應力鬆弛層(如圖2所示),之後 為通常順序的圖3之離子植入,藉由圖5的重新結晶,並如 圖7再次移除SiGe層。在每一此等重複循環中,在應變越來 越大的Si層上形成^^層,且在SiGe應力鬆弛層附近或頂 部可達到較尚的Ge濃度,致使晶格常數較大。因此,在第 二介面,第二晶格常數隨每次重複增大,藉此以層中的拉
〇 \89\89466 DOC 1264061 伸應k:也隨母-人重複增大。當S丨層中的拉伸應變達到預定 或所需值時’重複過程終止,無新的SiGe應力鬆弛層在應 變的S i層之頂部上形成。。 圖8示意顯示含有絕緣體上拉伸應變的Sl層作為其組件 的黾子系統。在圖中,電子系統一般顯示為一球形8 〇 〇,其 包括絕緣體上應變的矽層600。絕緣體上應變的♦層6〇0主 要用於各種高性能裝置與電路。可利用絕緣體上應變的si 所提供的高性能裝置之電子系統有許多種。當此類電子系 統為一數位處理器時,如電腦的中央電子複合體(central electronic complex ; CEC),會特別令人感興趣。 拉伸應憂一絶緣體上S i層的方法步驟,一般可用於更改 任何結晶層的應變狀態,或置於一支撐平臺上具有第一晶 格常數的第一結晶層之應變狀態。支撐平臺最好為非晶性 狀態,藉此其不會影響第一結晶層的晶格常數。必須在第 一結晶層的頂部上,形成一磊晶應力鬆弛單晶第二結晶 層’其方式使得其頂表面附近的第二結晶層具有與第一晶 格¥數不同的第二晶格常數。藉由離子植入,第一層及與 第一層形成介面的第二層之底部分,再次變為非晶性狀 怨。藉由固相磊晶第一結晶層而重新結晶之後,其迫使該 層符合第二晶格常數,使其應變狀態得以更改。該狀態更 改取決於第一晶格常數與第二晶格常數的關係。若第二晶 格常數大於第一晶格常數,如Si層與以以應力鬆弛層的情 形’則第一層的應變狀態將在拉伸方向更改。在相反情平 中’當第二晶格常數小於第一晶格常數,則第一層的應變 〇 \89\8946〇 D0C -16 - 1264061 狀態將在壓縮方向更改°移除第二層將在初始支撐結構尤 頂部上,產生更改了應變狀態的第一層。 根據上述講授内容,可對本發明進行許多修改與變化, 且對於熟悉技術人士為顯而易見。本發明的範圍由隨附的 申請專利範圍定義。 【圖式簡單說明】 從以上詳細說明與圖式可更加明瞭本發明的此等與其他 特徵,其中: 圖1示意顯示絕緣體上矽晶圓之分層結構的斷面圖; 圖2示意顯示分層結構的斷面圖,其具有形成於絕緣體上 石夕晶圓之頂部的SiGe應力鬆弛層; 圖3示意顯示植入分層結構的斷面圖; 圖4示意顯示Sl& SlGe應力鬆弛層之底部分非晶性化之 分層結構的斷面圖; 囷产示心顯示藉由固相蟲晶重新結晶的初始階段之斷面 圖; 圖6示意顯示重新結晶後之分層結構的斷面圖,其中以層 已獲得一拉伸應變; 圖7示意顯示具有應變Si層之絕緣體上矽晶圓的斷面圖; 圖8不意顯示含有絕緣體層上拉伸應變Si作為其組件的 電子系統。 /… 【圖式代表符號說明】 100 單晶Si層 10c>, 絕緣體上矽(SOI)層
0 \89\89466 D〇C 1264061 110 110, 150 160 200 410 520 600 800
SiGe應力鬆弛層 S1G e緩衝層 埋入S i〇2層 Si基板 離子植入 分層結構 應變的SiGe層 應變的S i層 電子系統 〇 \S0\89466 DOC -18- 1264061 伍、 中文發明摘要: 本發明揭示一種製造一絕緣體上應變的S i層的方法、該 絕緣體上應變的S丨層之一結構及包括此類層之電子系統。 該方法包话以下步驟:在一絕緣體上之S i層的了貝部上蠢晶 形成一 SiGe應力鬆弛層;藉由離子植入,將該結晶Si層與 該結晶SiGe應力鬆弛層的該下部分轉換為一非晶性材料狀 態;及從該SiGe層的該結晶頂部分重新結晶該非晶性材 料。該SiGe種晶層的較大晶格常數迫使該Si層中產生一拉 伸應變。 陸、 英文發明摘要: A method for fabricating a strained Si layer on insulator, a structure of the strained Si layer on insulator, and electronic systems comprising such layers are disclosed. The method comprises the steps of forming epitaxially a relaxed SiGe layer on top of a Si layer on insulator; transforming the crystalline Si layer and the lower portion of the crystalline relaxed SiGe layer into an amorphous material state by ion implantation; and re-crystallizing the amorphous material from the crystalline top portion of the SiGe layer. The larger lattice constant of the SiGe seed layer forces a tensile strain in the Si layer. 1264061 拾壹、圖式: 矽絕緣體 •100 基板____ ___ —- 一〜〜一〆〆二〆^^一〜:: —一〆 \150 \l60 圖
SiGe應力鬆弛緩衝層 __石夕絕緣體基板 、----〆
/110 -100 \150 \l60
Claims (1)
1264061 c:
200 SiGe應力鬆弛緩衝層 .110 矽 •100 絕緣體 '基板 \150 、 --> \160 罱 .110·1264061 410 SiGe應力鬆弛緩衝層 絕緣體 基板 ^100, \150 \l60
4
量5 1264061 SiGe /^520 應變的矽 -^600 絕緣體 、Μ50 基板 二二一二^::、〜一一〆二二二一二之 、--一, \l60 量6 應變的矽 絕緣體 基板 =、----二二〆 、 罱
、 600 、150 \l60 1264061 電子系統 600
1264061 柒、指定代表圖: (一) 本案指定代表圖為:第(6 )圖。 (二) 本代表圖之元件代表符號簡單說明: 150 埋入^〇2層 160 Si基板 520 應變的SiGe層 600 應變的Si層 捌、本案若有化學式時,請揭示最能顯示發明特徵的化學式: 〇 \S9\89466 DOC
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