ATE459098T1 - Verspannungs-silizium-auf-isolator (ssoi) und herstellungsverfahren dafür - Google Patents

Verspannungs-silizium-auf-isolator (ssoi) und herstellungsverfahren dafür

Info

Publication number
ATE459098T1
ATE459098T1 AT03814644T AT03814644T ATE459098T1 AT E459098 T1 ATE459098 T1 AT E459098T1 AT 03814644 T AT03814644 T AT 03814644T AT 03814644 T AT03814644 T AT 03814644T AT E459098 T1 ATE459098 T1 AT E459098T1
Authority
AT
Austria
Prior art keywords
layer
insulator
crystalline
ssoi
production method
Prior art date
Application number
AT03814644T
Other languages
English (en)
Inventor
Guy Cohen
Silke Christiansen
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE459098T1 publication Critical patent/ATE459098T1/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT03814644T 2002-12-19 2003-12-02 Verspannungs-silizium-auf-isolator (ssoi) und herstellungsverfahren dafür ATE459098T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/326,437 US6774015B1 (en) 2002-12-19 2002-12-19 Strained silicon-on-insulator (SSOI) and method to form the same
PCT/US2003/038334 WO2004061921A2 (en) 2002-12-19 2003-12-02 Strained silicon-on-insulator (ssoi) and method to form the same

Publications (1)

Publication Number Publication Date
ATE459098T1 true ATE459098T1 (de) 2010-03-15

Family

ID=32710790

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03814644T ATE459098T1 (de) 2002-12-19 2003-12-02 Verspannungs-silizium-auf-isolator (ssoi) und herstellungsverfahren dafür

Country Status (11)

Country Link
US (1) US6774015B1 (de)
EP (1) EP1573791B1 (de)
JP (1) JP4716733B2 (de)
KR (1) KR100773007B1 (de)
CN (1) CN100470724C (de)
AT (1) ATE459098T1 (de)
AU (1) AU2003297627A1 (de)
DE (1) DE60331473D1 (de)
IL (1) IL169141A (de)
TW (2) TWI283895B (de)
WO (1) WO2004061921A2 (de)

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US6963078B2 (en) * 2003-03-15 2005-11-08 International Business Machines Corporation Dual strain-state SiGe layers for microelectronics
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US7026249B2 (en) * 2003-05-30 2006-04-11 International Business Machines Corporation SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
US7029995B2 (en) * 2003-06-13 2006-04-18 Asm America, Inc. Methods for depositing amorphous materials and using them as templates for epitaxial films by solid phase epitaxy
WO2005010946A2 (en) * 2003-07-23 2005-02-03 Asm America, Inc. DEPOSITION OF SiGe ON SILICON-ON-INSULATOR STRUCTURES AND BULK SUBSTRATES
US20050070070A1 (en) * 2003-09-29 2005-03-31 International Business Machines Method of forming strained silicon on insulator
US6972247B2 (en) * 2003-12-05 2005-12-06 International Business Machines Corporation Method of fabricating strained Si SOI wafers
CN100459042C (zh) * 2003-12-16 2009-02-04 Nxp股份有限公司 在MOSFET结构中形成应变Si-沟道的方法
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US7202124B2 (en) * 2004-10-01 2007-04-10 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
DE602004011353T2 (de) * 2004-10-19 2008-05-15 S.O.I. Tec Silicon On Insulator Technologies S.A. Verfahren zur Herstellung einer verspannten Silizium-Schicht auf einem Substrat und Zwischenprodukt
US7273800B2 (en) * 2004-11-01 2007-09-25 International Business Machines Corporation Hetero-integrated strained silicon n- and p-MOSFETs
KR100601976B1 (ko) * 2004-12-08 2006-07-18 삼성전자주식회사 스트레인 실리콘 온 인슐레이터 구조체 및 그 제조방법
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US20070158743A1 (en) * 2006-01-11 2007-07-12 International Business Machines Corporation Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners
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FR2902233B1 (fr) * 2006-06-09 2008-10-17 Soitec Silicon On Insulator Procede de limitation de diffusion en mode lacunaire dans une heterostructure
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Also Published As

Publication number Publication date
JP2007521628A (ja) 2007-08-02
WO2004061921A8 (en) 2004-11-25
WO2004061921A3 (en) 2004-10-14
AU2003297627A1 (en) 2004-07-29
CN1726581A (zh) 2006-01-25
IL169141A (en) 2010-04-29
CN100470724C (zh) 2009-03-18
AU2003297627A8 (en) 2004-07-29
US6774015B1 (en) 2004-08-10
US20040142541A1 (en) 2004-07-22
TWI283895B (en) 2007-07-11
KR100773007B1 (ko) 2007-11-05
TWI264061B (en) 2006-10-11
IL169141A0 (en) 2007-07-04
TW200425281A (en) 2004-11-16
TW200625414A (en) 2006-07-16
WO2004061921A2 (en) 2004-07-22
DE60331473D1 (de) 2010-04-08
JP4716733B2 (ja) 2011-07-06
EP1573791A2 (de) 2005-09-14
KR20050083925A (ko) 2005-08-26
EP1573791B1 (de) 2010-02-24

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