TWI251332B - High temperature annealing of spin coated Pr1-xCaxMnO3 thin film for RRAM application - Google Patents
High temperature annealing of spin coated Pr1-xCaxMnO3 thin film for RRAM application Download PDFInfo
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- TWI251332B TWI251332B TW093124064A TW93124064A TWI251332B TW I251332 B TWI251332 B TW I251332B TW 093124064 A TW093124064 A TW 093124064A TW 93124064 A TW93124064 A TW 93124064A TW I251332 B TWI251332 B TW I251332B
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- baking
- film
- temperature
- annealing
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- 238000000137 annealing Methods 0.000 title claims abstract description 49
- 239000010409 thin film Substances 0.000 title abstract 7
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000004528 spin coating Methods 0.000 claims abstract description 13
- 239000002243 precursor Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052741 iridium Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229910000510 noble metal Inorganic materials 0.000 claims description 5
- 239000002904 solvent Substances 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 claims description 2
- MMIPFLVOWGHZQD-UHFFFAOYSA-N manganese(3+) Chemical compound [Mn+3] MMIPFLVOWGHZQD-UHFFFAOYSA-N 0.000 claims description 2
- 239000007772 electrode material Substances 0.000 claims 9
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims 4
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 239000010970 precious metal Substances 0.000 claims 2
- 229940119177 germanium dioxide Drugs 0.000 claims 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000001228 spectrum Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Battery Electrode And Active Subsutance (AREA)
Description
1251332 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於PCMO薄膜之旋塗,且特別是關於一種 可在RR AM應用中增強?〇^/[〇薄膜的雙極轉換性質之退 火處理。 【先前技術】 使用旋塗於P t基板上的p C Μ 0薄膜,在室溫中運算 之電子可程式電阻非揮發性記憶體器件係由Zhuang等在 2002年9月26日提出申請的美國專利申請序號第 10/256,380 號,名稱爲 “ Method Resistance Memory M e t a ] O x i d e T h i n F i 1 m D e p o s i t i ο η ” 中證實,且其中述及 —種於RAM器件中形成一 CMR層之技術。該PCMO薄膜 係成長在鉑層上且,於低溫熱處理之後,展現出非晶形或 多晶形的結構。此電阻器可用具有不同脈衝寬度之單極電 子脈衝逆向程式化到一高或低電阻狀態。不過,爲了要在 RRAM應用中使用CMR,更佳者爲使用雙極電脈衝轉換 性質。此等轉換性質需要一種結晶良好的PCM〇薄膜。 【發明內容】 一種在一 RRAM器件中形成一 PCMO薄膜之方法, 其係包括準備一基板;在該基板上沈積一金屬屏障層;在 該屏障層上形成一底部電極;使用一由Pr(CH3C02)3 · H2〇、Ca(CH3C02)2 · H2〇、和 Mn(ni)(CH3C02)3 · 2H2〇 (2) 1251332 在醋酸溶劑中組成的PCMO前驅物旋塗一層 P 1.1 _ x C a χ Μ η〇3 (P C Μ 0 )於該底部電極上;及於至少一烘烤步 驟中烘烤該P C Μ 0薄膜,其中該烘烤步驟可包括5例如’ 一第一烘烤步驟,在約5 0 °C至1 5 0 °C的溫度烘烤約1 〇秒 至1小時;一第二烘烤步驟,在約1 〇 〇 °C至2 0 0 °C的溫度 烘烤約]0秒至1小時;和一第三烘烤步驟’在約1 5 0 °C 至3 0 0 °C的溫度烘烤約1 〇秒至1小時。另外,可用單一 烘烤步驟,在約5 0 °C至3 0 (TC的溫度烘烤約1 〇秒至1小 時。在每一旋塗步驟之後,該(等)烘烤步驟之後係進行 該PCMO薄膜的退火,於一第一退火步驟中,係在約400 °C至9 0 0 °C的溫度進行約1 〇秒至1小時;重複該旋塗步 驟,該至少一烘烤步驟和該第一退火步驟,直到該PCMO 薄膜具有合意的厚度爲止;在溫度約4 5 0 °C至1 〇 〇 (TC的一 第二退火步驟中,將該PCMO薄膜退火約1分鐘至24小 時,從而製成一 PCMO薄膜,其具有PnxCaxMn〇3(〇.2 < =X < = 0.5 )之晶格結構;沈積一頂部電極;將該頂部 電極作成圖樣;以及完成該RRAM器件。 本發明之目標係要詳細說明一種經旋塗的P C Μ 0薄膜 之高溫退火方法,以形成供 RRAM應用,具有雙極電子 脈衝轉換性質的結晶良好之P C Μ 0薄膜。 本發明此摘要與諸目標係經提供以促成對本發明本質 之快速瞭解。經由參考下面配合附圖的對本發明較佳具體 實例之詳細說明,可得到對本發明之更徹底瞭解。 (3) 1251332 【實施方式】 較佳具體實例之詳細說明 本發明方法係包括準備一基板,其可由矽、二氧化矽 、或多晶矽所形成。於該基板上沈積一 Ta、TaN、Ta2〇5 、Ti、TiN、TiAIN、TaAIN、TiSiN、TaSiN、或丁iAl 之 屏障層’且在該屏障層上形成一底部電極。該底部電極可 由pt、Ir、或IrTaO所形成。於該底部電極上旋塗一層 Pr]>xCaxMn03(PCM0)薄膜。 該等PCMO前驅物係在醋酸溶劑中的Pr(CH3C02)3 · H2O、Ca(CH3C〇2)2 · H20、Mn(III)(CH3C〇2)3 · 2H20。然 後’在一或更多道烘烤步驟中烘烤該PCMO薄膜,例如一 第一烘烤步驟可包括於約5 0 °C至1 5 0 °C的溫度烘烤約1 〇 秒至1小時;一第二烘烤步驟可包括於約1 〇 Ot至2 0 (TC 溫度烘烤約]〇秒至1小時;及一第三烘烤步驟可包括於 約]5 0 °C至3 0 0。(:溫度烘烤約1 〇秒至1小時。於需要時, 可於本發明方法中使用3道以上的烘烤步驟以達到合意的 薄膜厚度。於該等步驟中使用不同的烘烤溫度;較佳者, 由第一步驟進展至第二步驟時以及由第二步驟進展至第三 步驟時,增加溫度。另外,本發明方法可使用單一烘烤步 驟’其可包括於約5 0 °C至3 0 0 °C的溫度下烘烤約1 0秒至 ]小時。於每次塗佈之後,在該(等)烘烤步驟之後,於 第一退火步騾中,在約4 00 °C至 90 0 °C快速熱退火(RTA )或爐內預退火此薄膜約1 0秒至1小時。重複該旋塗製 程直到該PCMO薄膜具有合意的厚度爲止。將該結構快速 -7- (4) 1251332 熱’ 火或置於爐中進行退火後熱處理,在此也稱爲第二退 火步驟。退火後熱處理之溫度約爲4 5 0 °c至1 〇 〇 〇 °c,且退 火時間爲約1分鐘至24小時。該退火氣圍可爲氧、氮、 ^ '或真空、或彼等之任何組合,且係在從真空至周遭氣 s的受控制壓力下實施。此等氣圍也可用於烘烤、預退火 和後段退火中任何一步驟或所有步驟中。 然後,於該PCMO薄膜上沈積一 Pt、Ir、An、或其 他貴金屬或金屬氧化物之頂部電極且使用淺遮罩,或者濕 式或乾式蝕刻程序製作圖樣。在頂部電極沈積與蝕刻之後 ’可進行一後段退火。頂部電極沈積後之退火後熱處理之 溫度爲約4 5 0 °C至1 0 0 0 °C,且退火時間爲約1分鐘至2 4 小時。同樣地,該退火氣圍可爲在從真空至周遭氣圍的控 制壓力下之氧、氮、氬、或真空、或彼等之任何組合。晶 體 Pri-xCaxMn〇3 的組成爲 〇»2 < = X < = 0.5。 圖1繪示出成長於銥基板上,且在6 0 0 °C的0 2中後 段退火15分鐘之PCMO薄膜之典型XRD光譜。圖2繪示 出成長於鉑基板上,且在600 °C的〇2中後段退火]5分鐘 之PCMO薄膜之典型XRD光譜。 圖3繪示出沈積於鉑基板上之p r】-x C a χ Μ η〇3 ( X = 0.4 )薄膜之電阻轉換性質。每次塗覆後都將此薄膜在氧氣圍 中於5 0 0 °C中預退火5分鐘且在氮氣圍中於5 5 〇 °C進行 RTA後段退火1 5分鐘’經過3個旋塗循環,製成3層之 PCMO薄膜。此器件之50奈秒(ns )的寫入條件爲5伏 (V ),而5 0奈秒的重置條件爲-5伏。該測量係經由施 (5) 1251332 加正偏壓至頂部電極及施加接地探針於該底部電極而完成 的。寫入電阻比重置電阻較大約兩個數量級。 本發明方法也可用來製造小型電容器,例如1 〇平方 微米以下的電容器。 如此,已於上文揭示出供RRAM應用的經旋塗 Pn_xCaxMn03薄膜之高溫退火方法。應瞭解者,在由後附 申請專利範圍所界定的本發明範圍內可對其作出進一步的 變更及修改。 【圖式簡單說明】 圖1係成長於銥基板上,在 6 0 0 °C的氧氣中退火15 分鐘之PCMO薄膜之典型XRD光譜。 圖2係成長於銷基板上,在 6 0 0 °C的氧氣中退火15 分鐘之PCMO薄膜之典型XRD光譜。 圖 3繪示出經沈積於鉑基板上之 Pri_xCaxMn03 ( X = G.4 )薄膜之電阻轉換性質。 -9-
Claims (1)
1251332 ⑴ 十、申請專利範圍 ].一種在一 RRAM裝置中形成一 PCMO薄膜之方法, 其包括: 製備一基板; 在該基板上沈積一金屬屏障層; 在該金屬屏障層上形成一底部電極; 旋塗一層 Pn_xCaxMn03(PCM0)於該底部電極上,其 係使用一由 Pr(CH3C02)3.H20、Ca(CH3C〇2)2.H20、和 Μ n (I Π ) ( C H 3 C 0 2) 3 · 2 Η 2 0所組成的 P C Μ Ο前驅物於醋酸 溶劑中; 於至少一烘烤步驟中烘烤該PCMO薄膜,其中該至少 --烘烤步驟包括在約5 0 °C至3 0 0 °C的溫度烘烤約1 〇秒至 1小時; 在每一旋塗步驟之後,於一第一退火步騾中,在約 4〇〇°C至9 00 °C溫度將該PCMO薄膜退火約10秒至1小時 重複該旋塗步驟,該至少一烘烤步驟和該第一退火步 驟’直到該PCMO薄膜具有合意的厚度爲止; 在一第二退火步驟中,於約4 5 0。(:至]〇 〇 〇 °C溫度將該 P C Μ 0薄膜退火,約1分鐘至2 4小時,從而製成一具有 ρ 】·〗· X C a λ’ Μ η 0 3 ( 0.2 < = X < = 〇 . 5 )晶格結構之 P C Μ 0 薄 膜; 沈積一頂部電極; 將該頂部電極製成圖樣;及 -10- (2) 1251332 完成該RRAM裝置。 2 .根據申請專利範圍第1項之方法’其中該製備一基 板係包括製備一選自矽、二氧化矽和多晶矽基板所構成群 組中的基板。 3 .根據申請專利範圍第1項之方法,更進一步包括提 供一該至少一烘烤步驟,該第一退火步驟和該第二退火步 驟所用之氣圍,其中該退火氣圍係選自氧、氮、氬、真空 和彼等之任何組合所構成群組中者,其經控制壓力在真空 至周圍大氣壓範圍。 4 .根據申請專利範圍第1項之方法,其中該沈積一金 屬屏障層係包括沈積一金屬之金屬屏障層,該金屬係選自 Ta、 TaN、 Ta205、 Ti、 TiN、 TiAIN、 TaAIN、 TiSiN、 TaSiN、及TiAl所構成的群組之中者。 5 .根據申請專利範圍第1項之方法,其中該在該金屬 屏障層上形成一底部電極係包括沈積一電極材料之底部電 極,該電極材料係選自P t、I r和Ir T a 0所構成的群組之中 者。 6 ·根據申請專利範圍第1項之方法,其中該沈積一頂 部電極係包括沈積一電極材料之頂部電極,該電極材料選 自Pt、lx*、An、其他貴金屬和貴金屬氧化物所構成的群組 之中者。 7 .根據申請專利範圍第1項之方法,其中係在該沈積 一頂部電極之前實施該第二退火步驟。 8 .根據申請專利範圍第1項之方法,其中係在該沈積 -11 - (3) 1251332 一頂部電極之後實施該第二退火步驟。 9· 一種在一RRAM裝置中形成一 PCMO薄膜之方法, 其包括: 製備一基板,其係選自矽、二氧化矽和多晶矽基板所 構成之群組中者; 在該基板上沈積一金屬屏障層; 在該金屬屏障層上形成一底部電極; 於該底部電極上旋塗一層pri.xCaxMn03(PCM0),其 係使用一由 Pr(CH3C〇2)3 · H2〇、Ca(CH3C〇2)2 · H2〇、和 Mn(III)(CH3C02)3· 2H20所組成的PCMO前驅物於醋酸 溶劑中; 於至少一烘烤步驟中烘烤該PCMO薄膜,其中該至少 一烘烤步驟包括在約5 0 °C至3 0 0 °C的溫度烘烤約1 〇秒至 1小時; 在每一旋塗步驟之後,於一第一退火步驟中,在約 4 〇 〇 °C至9 0 0 °C溫度將該P C Μ 0薄膜退火約1 0秒至I小時 重複該旋塗步驟,該至少一烘烤步驟和該第一退火步 驟,直到該PCMO薄膜具有合意的厚度爲止; 在一第二退火步驟中,於約4 5 〇 r至1 〇 〇 〇 °c溫度將該 PCMO薄膜退火,約]分鐘至24小時,從而製成一具有 Pr].xCaxMn03 ( 0.2 < = X < = 〇.5 )晶格結構之 PCM0 薄 膜; 提供一供該至少一烘烤步驟、該第一退火步驟和該第 -12- (4) 1251332 一退火步驟所用之氣圍,其中該退火氣圍係選自氧、氮、 氬、真空和彼等之任何組合所構成群組中者,其經控制壓 力在真空至周圍大氣壓範圍; 沈積一頂部電極; 將該頂部電極製成圖樣;及 完成該RRAM裝置。 ]〇 .根據申請專利範圍第9項之方法,其中該烘烤該 PC M0薄膜係包括在至少3個分開的烘烤步驟中烘烤該 PC M0薄膜,其中該等至少3個分開的烘烤步驟係包括在 約5 0 °C至1 5 0 °C溫度約1 〇秒至1小時之第一烘烤步驟; 在約1 〇 〇 °C至2 0 0 °C溫度約1 〇秒至1小時之第二烘烤步驟 ;及在約1 5 0 °C至3 0 CTC溫度約1 〇秒至1小時之第三烘烤 步驟。 Π .根據申請專利範圍第9項之方法,其中該沈積一 金屬屏障層係包括沈積一金屬之金屬屏障層,該金屬係選 自 Ta、TaN、Ta2〇5、Ti、TiN、TiA】N、TaAIN、TiSiN、 TaSiN、及Ti A1所構成的群組之中者。 1 2 .根據申請專利範圍第9項之方法,其中該在該金 屬屏障層上形成一底部電極係包括沈積一電極材料之底部 電極,該電極材料係選自P t、I r和I r T a 0所構成的群組之 中者。 1 3 ·根據申請專利範圍第9項之方法,其中該沈積一 頂部電極係包括沈積一電極材料之頂部電極,該電極材料 選自Pt、Ir、Au、其他貴金屬和貴金屬氧化物所構成的群 -13 > (5) 1251332 組之中者。 I4·根據申請專利範圍第9項之方法,其中係在該沈 積一頂部電極之前實施該第二退火步驟。 1 5,根據申請專利範圍第9項之方法,其中係在該沈 積一頂部電極之後實施該第二退火步驟。 1 6.—種在一 RRAM裝置中形成一 PcM〇薄膜之方法 ’其包括: 製備一基板; 在該基板上沈積一金屬之金屬屏障層,該金屬係選自 Ta、TaN、Ta2〇5、Ti、丁iN、TiAIN、TaAIN、TiSiN、 T a S i N、及T i A 1所構成的群組中者; 在該金屬屏障層上形成一電極材料之底部電極,該電 極材料係選自Pt、Ir和IrTaO所構成的群組中者; 於該底部電極上旋塗一層 Pr^xCaxMnOWPCMO),其 係使用一由 P r ( C Η 3 C 0 2) 3 · Η 2 0、C a ( C Η 3 C 〇 2 ) 2 · Η 2 Ο、和 Μ η ( Π I) ( C Η 3 C Ο 2) 3 · 2 Η 2 〇所組成的Ρ C Μ Ο前驅物於醋酸 溶劑中; 在至少3個分開的烘烤步驟中烘烤該PCMO薄膜’其 中該等至少3個分開的烘烤步驟係包括在約5 0 °C至1 5 〇 C 溫度約ίο秒至1小時之第一烘烤步驟;在約100°c至200 °C溫度約1 〇秒至1小時之第二烘烤步驟,及在約1」〇 C 至3 0 0 t溫度約1〇秒至1小時之第三拱烤步驟; 在每-旋塗步驟之後,在一第—退火步驟中約 4 0 0 °C至90CTC溫度下將該PCM0薄膜退火約]〇秒至1小 -14- (6) 1251332 時; 重複該旋塗步驟、該至少3個分開的烘烤步驟和該第 一退火步驟,直到該P C Μ 0薄膜具有合意的厚度爲止; 在第二退火步驟中,於約4 5 〇 °C至1 0 0 0 °C溫度下將該 P C Μ 0薄膜退火約1分鐘至2 4小時,從而製成一具有 Pn.xCa.MnOs ( 0.2 < = X < = 〇. 5 )晶格結構之 PCMO 薄膜 沈積一電極材料之頂部電極,該電極材料選自P t、I r 、Au、其他貴金屬和貴金屬氧化物所構成的群組; 將該頂部電極作成圖樣;及 完成該RRAM裝置。 1 7 .根據申請專利範圍第1 6項之方法,其中該製備一 基板係包括製備一選自矽、二氧化矽和多晶矽基板所構成 群組中的基板。 1 8 .根據申請專利範圍第1 6項之方法,其進一步包括 提供一供該至少3個分開的烘烤步驟、該第一退火步驟和 該第二退火步驟所用之氣圍,其中該退火氣圍係選自氧、 氮、氬、真空和彼等之任何組合所構成群組中者,其經控 制壓力在真空至周圍大氣壓範圍。 1 9 .根據申請專利範圍第1 6項之方法,其中係在該沈 積一頂部電極之前實施該第二退火步驟。 2 〇 .根據申請專利範圍第1 6項之方法,其中係在該沈 積一頂部電極之後實施該第二退火步驟。 2 ].根據申請專利範圍第1 0或]6項之方法,其中於 -15- (7) 1251332 該至少3個分開的烘烤步驟之每一步驟中係使用不同的烘 烤溫度。 2 2 .根據申請專利範圍第2 ]項之方法,其中在第二烘 烤步驟中的烘烤溫度係高於在第一烘烤步驟中者,且第三 烘烤步驟中的烘烤溫度係高於第二烘烤步驟中者。
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