TWI250530B - High burst rate write data paths for integrated circuit memory devices and methods of operating same - Google Patents
High burst rate write data paths for integrated circuit memory devices and methods of operating same Download PDFInfo
- Publication number
- TWI250530B TWI250530B TW093115984A TW93115984A TWI250530B TW I250530 B TWI250530 B TW I250530B TW 093115984 A TW093115984 A TW 093115984A TW 93115984 A TW93115984 A TW 93115984A TW I250530 B TWI250530 B TW I250530B
- Authority
- TW
- Taiwan
- Prior art keywords
- data
- control signal
- cell array
- memory cell
- switches
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 25
- 239000000872 buffer Substances 0.000 claims abstract description 222
- 230000004044 response Effects 0.000 claims description 37
- 238000012163 sequencing technique Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 206010011469 Crying Diseases 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims description 2
- 235000010627 Phaseolus vulgaris Nutrition 0.000 claims 2
- 244000046052 Phaseolus vulgaris Species 0.000 claims 2
- 241000239226 Scorpiones Species 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 34
- 230000000630 rising effect Effects 0.000 description 9
- 101001074449 Crotalus durissus terrificus Phospholipase A2 inhibitor CNF Proteins 0.000 description 6
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 102000007330 LDL Lipoproteins Human genes 0.000 description 1
- 108010007622 LDL Lipoproteins Proteins 0.000 description 1
- 206010029412 Nightmare Diseases 0.000 description 1
- 241000282376 Panthera tigris Species 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20030035604 | 2003-06-03 | ||
| KR10-2003-0042840A KR100532444B1 (ko) | 2003-06-03 | 2003-06-27 | Ｎ 비트 프리패치 구조로 2ｎ 비트 프리패치 스킴을구현하는 메모리 장치 및 이 메모리 장치의 2ｎ 비트프리패치 방법 및 자동 프리차아지 방법 |
| US10/792,425 US7054202B2 (en) | 2003-06-03 | 2004-03-03 | High burst rate write data paths for integrated circuit memory devices and methods of operating same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200516595A TW200516595A (en) | 2005-05-16 |
| TWI250530B true TWI250530B (en) | 2006-03-01 |
Family
ID=33545117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW093115984A TWI250530B (en) | 2003-06-03 | 2004-06-03 | High burst rate write data paths for integrated circuit memory devices and methods of operating same |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP4819325B2 (enrdf_load_stackoverflow) |
| DE (1) | DE102004026526B4 (enrdf_load_stackoverflow) |
| GB (1) | GB2403575B (enrdf_load_stackoverflow) |
| TW (1) | TWI250530B (enrdf_load_stackoverflow) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005001894A1 (de) * | 2005-01-14 | 2006-08-03 | Infineon Technologies Ag | Synchroner Parallel-Serienwandler |
| JP5052056B2 (ja) * | 2005-09-29 | 2012-10-17 | エスケーハイニックス株式会社 | 半導体メモリ素子のデータ入力装置 |
| JP4470183B2 (ja) | 2006-08-28 | 2010-06-02 | エルピーダメモリ株式会社 | 半導体記憶装置 |
| KR20080065100A (ko) | 2007-01-08 | 2008-07-11 | 주식회사 하이닉스반도체 | 반도체 메모리 소자와 그의 구동 방법 |
| KR101094946B1 (ko) | 2010-01-29 | 2011-12-15 | 주식회사 하이닉스반도체 | 반도체 집적 회로 |
| JP2013206492A (ja) * | 2012-03-27 | 2013-10-07 | Toshiba Corp | 半導体装置およびその駆動方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59180871A (ja) * | 1983-03-31 | 1984-10-15 | Fujitsu Ltd | 半導体メモリ装置 |
| US4745577A (en) * | 1984-11-20 | 1988-05-17 | Fujitsu Limited | Semiconductor memory device with shift registers for high speed reading and writing |
| JPH0740430B2 (ja) * | 1986-07-04 | 1995-05-01 | 日本電気株式会社 | メモリ装置 |
| TW293107B (enrdf_load_stackoverflow) * | 1994-10-28 | 1996-12-11 | Matsushita Electric Ind Co Ltd | |
| JP3788867B2 (ja) * | 1997-10-28 | 2006-06-21 | 株式会社東芝 | 半導体記憶装置 |
| US6459393B1 (en) * | 1998-05-08 | 2002-10-01 | International Business Machines Corporation | Apparatus and method for optimized self-synchronizing serializer/deserializer/framer |
| JP2000163969A (ja) * | 1998-09-16 | 2000-06-16 | Fujitsu Ltd | 半導体記憶装置 |
| DE19951677B4 (de) * | 1998-10-30 | 2006-04-13 | Fujitsu Ltd., Kawasaki | Halbleiterspeichervorrichtung |
| JP3859885B2 (ja) * | 1998-11-24 | 2006-12-20 | Ｎｅｃエレクトロニクス株式会社 | 半導体記憶装置 |
| JP4083944B2 (ja) * | 1999-12-13 | 2008-04-30 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
-
2004
- 2004-05-25 DE DE102004026526A patent/DE102004026526B4/de not_active Expired - Fee Related
- 2004-05-31 JP JP2004161460A patent/JP4819325B2/ja not_active Expired - Fee Related
- 2004-06-03 GB GB0412446A patent/GB2403575B/en not_active Expired - Fee Related
- 2004-06-03 TW TW093115984A patent/TWI250530B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| GB0412446D0 (en) | 2004-07-07 |
| GB2403575A (en) | 2005-01-05 |
| DE102004026526B4 (de) | 2010-09-23 |
| JP2004362756A (ja) | 2004-12-24 |
| GB2403575B (en) | 2007-05-16 |
| JP4819325B2 (ja) | 2011-11-24 |
| TW200516595A (en) | 2005-05-16 |
| DE102004026526A1 (de) | 2005-01-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |