JP4470183B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP4470183B2 JP4470183B2 JP2006231211A JP2006231211A JP4470183B2 JP 4470183 B2 JP4470183 B2 JP 4470183B2 JP 2006231211 A JP2006231211 A JP 2006231211A JP 2006231211 A JP2006231211 A JP 2006231211A JP 4470183 B2 JP4470183 B2 JP 4470183B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- bits
- burst
- memory device
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Description
N=1+{AL+CWL+(BL/2)+tCCD}/tCCd
となる。一例として、
AL=10
CWL=8
BL=4
tCCD=2
とすると、
N=12となり、12台のアドレスカウンタ121が必要である。
101A,101B コマンドデコーダ
102A,102B アドレスラッチ回路
103A,103B プリデコーダ
104A,104B Yデコーダ
105A,105B カラムスイッチ
106A,106B メインアンプ
107A,107B 時分割転送回路
121 アドレスカウンタ
122 モードレジスタ
123 FIFO回路群
130,211A〜214A,211B〜214B マルチプレクサ
131〜134 FIFO回路
221A〜228A,241A〜244A,221B〜228B,241B〜244B スイッチ
ADD アドレス端子
CMD コマンド端子
DQ データ入出力端子
GA,GB グループ
RWBS データバス
Claims (5)
- mビット又はnビットのデータをラッチし該データをデータ入出力端子からバースト出力するパラレル−シリアル変換のFIFO回路群と、
複数のグループに分割されたメモリアレイと、
前記データ入出力端子を介してバースト入力され又はバースト出力するn(>m)ビットのデータを前記メモリアレイとの間で並列に入出力する転送回路と、
前記転送回路と前記FIFO回路群との間でデータ転送を行うm本のデータバスと、
バースト長を設定するためのモードレジスタと、
前記メモリアレイの前記複数のグループからそれぞれnビットのデータを出力するメインアンプと、を備え、
前記モードレジスタに設定可能な最小バースト長がmであり、
nとmは、n=2のk乗×mの関係を有し、
前記転送回路は、前記バースト長にかかわらず前記データバスを用いたデータの転送をmビット単位で行い、
前記転送回路は、前記モードレジスタに設定されたバースト長がnである場合には、同一グループに属する前記メモリアレイから読み出された前記nビットのデータをmビットずつ、2のk乗回前記データバスを介して順次前記FIFO回路群に供給し、
前記転送回路は、前記モードレジスタに設定されたバースト長がmである場合には、異なるグループに属する前記メモリアレイから読み出された前記nビットの中からmビットのデータを選択して、前記データバスを介して順次前記FIFO回路群に供給することを特徴とする半導体記憶装置。 - 前記データバスを用いたデータの転送は、リードコマンドによってmビット単位で行うことを特徴とする請求項1に記載の半導体記憶装置。
- 隣接するデータバス間にシールド配線が設けられていることを特徴とする請求項1又は2に記載の半導体記憶装置。
- 前記シールド配線のラインアンドスペースは、前記データバスのラインアンドスペースよりも小さいことを特徴とする請求項3に記載の半導体記憶装置。
- 前記シールド配線が電源配線であることを特徴とする請求項3又は4に記載の半導体記憶装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006231211A JP4470183B2 (ja) | 2006-08-28 | 2006-08-28 | 半導体記憶装置 |
TW096131331A TWI376693B (en) | 2006-08-28 | 2007-08-24 | Semiconductor memory device |
US11/895,695 US7755953B2 (en) | 2006-08-28 | 2007-08-27 | Semiconductor memory device with minimum burst length bit transfer in parallel to and from a FIFO block |
CN2007101481615A CN101136245B (zh) | 2006-08-28 | 2007-08-28 | 半导体存储器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006231211A JP4470183B2 (ja) | 2006-08-28 | 2006-08-28 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008052878A JP2008052878A (ja) | 2008-03-06 |
JP4470183B2 true JP4470183B2 (ja) | 2010-06-02 |
Family
ID=39113259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006231211A Expired - Fee Related JP4470183B2 (ja) | 2006-08-28 | 2006-08-28 | 半導体記憶装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7755953B2 (ja) |
JP (1) | JP4470183B2 (ja) |
CN (1) | CN101136245B (ja) |
TW (1) | TWI376693B (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8595459B2 (en) * | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
KR100886629B1 (ko) * | 2006-09-28 | 2009-03-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
JP5420827B2 (ja) * | 2007-07-04 | 2014-02-19 | ピーエスフォー ルクスコ エスエイアールエル | アドレスカウンタ及びこれを有する半導体記憶装置、並びに、データ処理システム |
JP5666077B2 (ja) * | 2007-07-04 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | アドレスカウンタ及びこれを有する半導体記憶装置、並びに、データ処理システム |
US8046559B2 (en) * | 2008-03-27 | 2011-10-25 | Intel Corporation | Memory rank burst scheduling |
US8634245B2 (en) | 2008-08-08 | 2014-01-21 | Hynix Semiconductor Inc. | Control circuit of read operation for semiconductor memory apparatus |
KR100915832B1 (ko) * | 2008-08-08 | 2009-09-07 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 리드 동작 제어 회로 |
JP5393405B2 (ja) * | 2009-11-05 | 2014-01-22 | キヤノン株式会社 | メモリ制御回路 |
KR20120098105A (ko) | 2011-02-28 | 2012-09-05 | 에스케이하이닉스 주식회사 | 데이터 전송 회로 및 이를 포함하는 메모리 장치 |
US9009570B2 (en) * | 2012-06-07 | 2015-04-14 | Micron Technology, Inc. | Integrity of an address bus |
US10318457B2 (en) * | 2015-06-01 | 2019-06-11 | Microchip Technology Incorporated | Method and apparatus for split burst bandwidth arbitration |
KR102412609B1 (ko) * | 2017-11-03 | 2022-06-23 | 삼성전자주식회사 | 내부 커맨드에 따른 어드레스에 대한 저장 및 출력 제어를 수행하는 메모리 장치 및 그 동작방법 |
US20220328078A1 (en) * | 2019-08-23 | 2022-10-13 | Rambus Inc. | Hierarchical bank group timing |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3914151B2 (ja) | 1997-06-03 | 2007-05-16 | 富士通株式会社 | データ変換回路 |
JP4198271B2 (ja) | 1998-06-30 | 2008-12-17 | 富士通マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
JP2001023374A (ja) | 1999-07-12 | 2001-01-26 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
KR100372247B1 (ko) | 2000-05-22 | 2003-02-17 | 삼성전자주식회사 | 프리페치 동작모드를 가지는 반도체 메모리 장치 및 메인데이터 라인수를 줄이기 위한 데이터 전송방법 |
US7032066B2 (en) * | 2001-09-20 | 2006-04-18 | Renesas Technology Corp. | Semiconductor memory unit |
JP2003249077A (ja) | 2002-02-21 | 2003-09-05 | Elpida Memory Inc | 半導体記憶装置及びその制御方法 |
JP2003272382A (ja) | 2002-03-20 | 2003-09-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP4068427B2 (ja) | 2002-10-08 | 2008-03-26 | エルピーダメモリ株式会社 | データインバージョン回路及び半導体装置 |
JP2004164769A (ja) | 2002-11-14 | 2004-06-10 | Renesas Technology Corp | 半導体記憶装置 |
KR100498466B1 (ko) | 2002-11-30 | 2005-07-01 | 삼성전자주식회사 | 개선된 데이터 기입 제어 회로를 가지는 4비트 프리페치방식 fcram 및 이에 대한 데이터 마스킹 방법 |
DE10309919B4 (de) * | 2003-03-07 | 2008-09-25 | Qimonda Ag | Pufferbaustein und Speichermodule |
JP4400081B2 (ja) | 2003-04-08 | 2010-01-20 | エルピーダメモリ株式会社 | 半導体記憶装置 |
DE102004026526B4 (de) | 2003-06-03 | 2010-09-23 | Samsung Electronics Co., Ltd., Suwon | Integrierter Schaltungsbaustein und Betriebsverfahren |
US7054202B2 (en) | 2003-06-03 | 2006-05-30 | Samsung Electronics Co., Ltd. | High burst rate write data paths for integrated circuit memory devices and methods of operating same |
JP4370507B2 (ja) | 2003-11-27 | 2009-11-25 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
JP4600825B2 (ja) | 2005-09-16 | 2010-12-22 | エルピーダメモリ株式会社 | 半導体記憶装置 |
-
2006
- 2006-08-28 JP JP2006231211A patent/JP4470183B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-24 TW TW096131331A patent/TWI376693B/zh active
- 2007-08-27 US US11/895,695 patent/US7755953B2/en not_active Expired - Fee Related
- 2007-08-28 CN CN2007101481615A patent/CN101136245B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101136245A (zh) | 2008-03-05 |
JP2008052878A (ja) | 2008-03-06 |
US20080049541A1 (en) | 2008-02-28 |
TWI376693B (en) | 2012-11-11 |
TW200830316A (en) | 2008-07-16 |
CN101136245B (zh) | 2012-07-04 |
US7755953B2 (en) | 2010-07-13 |
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