TWI249786B - System, method and apparatus for improved global dual-damascene planarization - Google Patents

System, method and apparatus for improved global dual-damascene planarization Download PDF

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Publication number
TWI249786B
TWI249786B TW093106649A TW93106649A TWI249786B TW I249786 B TWI249786 B TW I249786B TW 093106649 A TW093106649 A TW 093106649A TW 93106649 A TW93106649 A TW 93106649A TW I249786 B TWI249786 B TW I249786B
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Taiwan
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layer
surface layer
semiconductor substrate
flattening
item
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TW093106649A
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TW200501260A (en
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Shrikant P Lohokare
Andrew D Bailey Iii
David Hemker
Joel M Cook
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Lam Res Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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1249786 九、發明說明： 一、【發明所屬之技術領域】 種半轉狀魏.，尤關於一 本案與西元2003 i 3 坦化方法與系統。 10/390520缺年月 曰申請之美國專利申請案第 備右，Μ二y_ u良之局部雙道金屬鑲嵌平坦化系統、方法與設 備」有關，故在此將細容弱參考資料。 —、【先前技術】 雙程在半導體製造巾越來鱗遍。在典型的 已r荦=介r、或沉積於形 多=====表層部。導電 屬職細赠產生金 ㈣導,ΐ材料的表層部通常利用化學機械研磨（C·)盎電化學 刻）製程舆CMP及ECP製程敝合= ECP的.二t ’’’? i上述各製程皆有其从。舉例而言’ 材 ^ 差的均勻度且無法有效地去除非導電性 姓、導電性殘餘物、或造成各種材料之腐 蝕或引起不均勻的移除量之物質接觸製程 化互連層與_的介電層_之頂表面。 的破壞(例如’内層的分離、剝離)造成剩:==關 CMP所引起的應力破壞更因為近年來所使用的材‘間的^籌 :ί力:Ϊί,降低CMP製程之實際作用力而減小 j應力如a成無法接受的產鮮足及其它極差的 翏數。 匕 1249786 三、【發明内容】 概括而言，本發明之圖案化的半導體基^ ^ 以 =足上述要求。吾人應清楚理解：藉由各種 本發明’包括製程、設備、系統、電腦可讀=貝加 下將藉由數種創新的實施例朗本發明。 、次衣置< n-實，係提供一種圖案化的半導體基板之平坦化 料步驟· ―®案化的半導體基板之接收步驟，且右措 ίΐίϊϊ表層部之映射步驟，俾較—總體“#實ί上ί 貝上局部平坦化的表層部之侧步驟 ，及-實 圖案係在雙道金屬鑲嵌過程中形成在』 1之平坦化步 該平坦化步驟實質上完全去除該額外層、。 較佳地，該表層部的主體部之去除步 :之^額外層1成步驟；及_額;層驟與表有;^步驟：一表層 又，該表層部的主體部之去除步 姆::=:13:額外層與至少局部的表， 蝕刻步驟，俾實質地平扫化兮矣日：：土乂句邵的表層部之 層。 化絲層部，而實質上完全去除該額外 較佳地，用以確定該總體不均勻产併 層部之映射步_包_ —料流^ 6 1249786 化的表層部予以映射。 較佳地，用以確定該總體不均勻度之該實質上平 '包括現場地映_實質上局部平坦^的表^ 化的上鎌魏财均自度之該實f上局部平坦 刻ίϋ 係包括為補償該總體不均勻度而調整一姓 夺声上消除該總體不均勻度之該實質上局部平括化的 的表ΐίίΓϋίΐί?總體不均句度之該實質上局部平坦化 部之二一=r?”括進_而使形成在該圖案化的特徵 該實質最小化該複數之特徵部^ ΛΑ車乂佳地’更包含一最終钱刻步驟，俾實質去险擗士卢兮回在y 的特f卩之上的_。圖案化 導電ί互連材料含銅及/或元素銅除遮罩材科。 :數-瞧的=基，反 :數== 部之_步驟，俾平」；辦J:性，2度;-表層部的主體 =映射步驟，俾確定一 Ϊ體句度層 另層部俾實質上消除該總體不ί= 含以下/驟鑲嵌互連結構的形成方法，包 1249786 表層部，包括：-表層部之上的額外㊉〗牛_ t平坦化5亥 層，-實質上局部平坦化的表層部之映=除_外 =總二=局部平坦化二 含以下步驟:丄3金屬包 ί冗性:勻度ϋ層部的主體部之去除步驟 =變該表層部之; 層;一實質上^^^ =列不均勻度；及—實質上局部平坦化的 衣層。步驟’俾實f上消除該總體稍皱。 板的i體本不具ϋ、。化機械性應力、啊實質上耻整個基 么么將參照附隨的圖式，以今明太恭日日/- ra jb 1 符號指示類似的元件 兄明柄明。在圖式中，相似的參考 四、【實施方式】 項技與方 = 具編例。熟悉本 有細節，仍可據以ί施所說明之某些或所 個二㈣方法之—實_係可使轉體基板的整 <局㈣域/、有改良之局部平坦化均勻度。改良之局部平坦化均 畜部之侧步驟，俾實質地平坦化該表層 !249786 了由覆蓋層之特徵部與沉積製程的變異所引起的 iir係提供整個基板之改良的總體平坦 化均勾度（例如，相較於中心均勻度的邊緣均句
2顯示依本發明一實施例的雙道金屬鎮J 請具嫩。ί 層孔等等），盘較小、箪齡♦夕㈣1 Ρ102 (例如，渠溝、介 !00 ^ΐ1ΐΐ；^ 銅合金或其它導電材料。 互連材料120為銅或 觸互表層部112係涵蓋住特徵_、腦、 叫、丨16則，如厚2度=局部性變異 部104而言，係具有表層部112之厚产ϋϋ目較於較小特徵 而較小的特徵部104則具有表層部‘，父大^減小， 靠的=部廳具有表層部112的某種程^大的^異。緊 輸生互連材_之表層部112 上侧 106的阻障層i 10露出之前， 1特徵部 係形額外物 材料(例如’旋塗玻璃（S0G)、多 ' =貝平坦的填充 UV或熱硬化的材料、或曰夕^合物光阻、雙重層、 當，特性之材料)。;額外層 一選用之極薄的（例如，約25至！ mHP112之間亦可具有 204為—啡層或-轉層。可作 1249786 可作為額外層202的材料種類。 ㈣額^層202與表層部112具有實質為一比一（1. η心 擇性，俾能使後續_製程（例如 （jj)的餘刻選 夠的速 =刻額外層202與表層製程）能 ^〇〇 ^ no ^ Π2 ^ 202 勻地敍刻整個區域之上的額外層202盘表層程能夠均 實質局部性平坦’而實質上消除“之局部二=層 _，且表層部112為銅時，則峨牛額以 ΪΓ二質匕可，適?於S0G與銅兩者的蝕刻速率控制量:俾3 應性函素根的電漿饋人氣體，但典型上使用了^任巧以產生反 可調整各種製程參數而控制侧速率 4 及HG。 f呈變數之變異所引起的雜，例如基二$，= 多之添加物（例如，Ar、H2、α、。 ；；、? 3之一個或更 CH2F2、與 ch4)。 2 卿（Χ=Ρ、α、ΒΓ、υ、 並使用其它添加物而提供對額外層2〇2 ^ 、主要_劑’ 剩歉銅112的頂表面。其它添加化 上述每-個製㈣操作溫度侧在75t*伽/或⑺° 平坦r:r除= 或更多之後續蝴製程將去除主體歧部^^刻衣知° 一個 在罐程之後對終點施以修_的_: 點:接 ^49786 已從阻障1〗〇丰W主 餘刻製程。在修潤用':二1:後製程亦可包括修潤用的 的穩定度。在丄ΐ=11= 牟防止腐钱且提供進-步製程所需 任何材料，而僅用於鈍 作並不用於實質地去除 供進:步製程所需的穩定度。、…'才料120 ’俾能防止腐似提 100圖第ϋ發明一實施例的已進<亍過第二蝕刻製程的基板 障層110實^時之後進行’俾能使所有位置上ί阻 料）之局部。 3钔的合金與其組合物、及其它導電材 與覆蓋層、1G4、1G6之位置、尺寸 第一蝕刻製程中a )表層部112的局部性平坦度。在 之下，第二伽制ίί整個額外層202與局部的表層部112。相較 平坦的表層擇性的姓刻製程，用以去除剩餘且 圖4B顧_ "卩伤而達到終點（即到達阻障層110露出時）。 板。去除局已=過阻障去除製程的基 110具有較、高的率^除主體之表層112 ’且較佳地對阻障層 基的化學物質7^。舉例而言，若表層部112為銅時，則鹵素 於第二勉刻製^=Cl2方=、HC1、、BCl3)可有效地用 製程，例如，可利用由物理性所決定的钱刻 調整各種f程&if/貝4氣體或惰性氣體）的濺鍍製程。可 -個或i多it t如基板之反應性物質的溫度平衡，與所含之 〆 之外、加物（例如，H2、02、Ar、He、Xe、Ne、Kr等 11 1249786 等）。 圖5為本發明之一實施例的進行 流程圖500。在操作505中，在導電表層匕，作方法之 202。在操作51〇巾，施以第一餘刻製程附設額外層 2〇2與導電表層部112。在操作515 f $除的額外層 除剩餘的表層部112,而至終點。 _弟-钱刻製程，俾去 在又一實施例中，操作515亦包括 修潤用的侧之後的後續製減包括選^職程。在 2導電材料12〇，俾防止舰並提供進;製^剩餘 6潤用的餘刻之後的額外操作並不用於、二、思疋度。在 餘的導電材料120’俾能防止腐製: 了實施例的施於基板_而提高局部的均明之 Γ^ί Γ〇Γ606 § =下參賴6Β及圖7，在操作7〇5中 2 亦可沉_成在表 =卜;:0:。若表層部602為銅或銅合金時，則控制二= Θ :二it形成銅反應物層6G4。—種實例是可形 I内，ΐίΐΓ體。銅反應物層604係擴散到銅表層602的表面 已為五人所j成銅表層602的頂部。銅的化學變化所需之製程 ^晃、知，例如納格爾.S.考卡尼與勞勃.T.迪霍夫於西元 'rLTTtmi 5149 (11) G62〇-G632 ^ m j6蝕刻、與銅的平坦所需的揮發性圖表之應用」。 在另一實例中，可將額外層604沉積在表層部602之上。沉積 12 1249786 層，係ί括f合物層或沉積在表層部602之上的氧化層。 604。喿作710與圖6C，即施以回姓製程，俾去除額外層 邱602°二ί層部6〇2亦加以去除。絲額外層604將導致表層 』實質敕—步軟化（即平坦化）喊為輪廓_，。鹵化 竇所二μ匕表層邛602的外形。A鹵化銅與銅表層部602亦維持 盥i作^710 (I ·-0❾回蝕選擇性。可重覆進行多次的操作705 皁貫f平坦化表層部而成為接_輪磨_，與 ，如圖6D所示，直到最終的輪廓呈實質平坦為止。 形與成分配方的相依性所產生的銅表層部602之化學 ，^通吊可藉由使銅反應性物質界面處的銅發生氧化而達成。 =情^_氧化係包括元素·學變化油化合物與正氧化維 主銅。牛例而言，可在較低溫之氟電漿（例如，小於2〇(rc = 表面的銅氧化成氯化銅或二氯化銅（CuCl或CuCl2)。 、 =製程係涉及此種銅化合物還原成另一化學化合物，其 因而_在岐板溫度下殘留摘餘的表層602,之表 。牛例而言，在存在有反應性氫物質（例如，H2電漿） :而：會有CuCl2還原綱H生的Cu3Cl3。隨著轉變之局部：回 來的與外形相依之轉換的轉變將導致銅表層部002的主體去 除’且同時平坦化銅表層602的外觀（例如，輪廓 ^操作715巾，若表層部602呈實質平坦時，則此方法的 。又，若在操作中715，表層部6〇2未呈實質平坦時，則 上述操作705之後進行此方法的操作。在一實施例中，操作、7仍 至715係在單-侧室之内現場地產生。在又一實施例中 71〇係離線產生且包括ECD或低下作用力CMp製程，二/ 圖6D所示之實質平坦的表層部6〇2,。 成ϋ 圖6Α至圖7所述之方法操作係當作平坦主體的去除製 用，其進行不平坦的表層部602之平坦化與去除主體的表層^ 兩者。 基板100、600的局部性平坦化可藉由熟知的數種層厚映射技 13 1249786 映射更多種加以禮定。舉例而言，渦電流感測器能夠 23 ^1 12’的厚度，如高提斯等人於西元細年12月 膜Α拓二利申請案第腦28,912號的「使用渦電流之薄 车t Η 系統/方法與設備」，及高提斯等人於西元2002 順疼夕Λ从曰人申^睛之美國專利申請案第10/251，033號的「在多步驟 料之去除速率的變之目的句板度之邊緣處的材 體不均皱之操作方法議 中，夢由CMP、pH徵°卩_相依之不均勻度。在操作810 已知^任何其它方至圖7所示的方法與系統、或 部性的不均勻度係“二，局雜的不均勻度。實質去除局 所示之平坦化的表層局部性平坦化的表料，例如圖3 的表層部， 表層部902可為厚度僅為數百埃之極薄 量化出具有平坦化之表層部的基板，俾確認且 映射L的 個 。使用數種已知的層厚 射。現場的映射製;在目前巧之外)進行映 動態地調整後續製程。、〜'、于且允s午隨著後續製程的進行而 在“作820中’如操作815所確定之總體不均勻度的位置與大 1249786 2於邊緣的不均勻度而能夠同時使整個^表，賞t 110 邱川？、1W 1Λ^丄 ；且此夠使任何凹陷（例如，特徵 修潤用的蝕刻ί剩之的銅 ===且 有極慢的餘刻速率’俾能使任何特徵部ω2 :〜層兩J白具 =:ί:=ί二陷成為最小，= ILD損失的情況下具有實二上 基 ==fSHF:== ^體，包括4素反應性物質（例如，cf4、（¾、 其4‘添加“革控制的添加物係包括&、。2、卿2，且亦包括 右正個基板上的總體銅凹陷及/或遮罩/ild損失於修潤用 1249786 數就總想不均勻度 ;或，=速上率所引起的“’不=況= =;利】適當的均勻度與選擇=二最 較失 刻遮罩材料而造成與特徵部1〇2、刚、廳之^ 二 以補償。此製程之中 ί度乂擇性的變異係包括反應性4素物質 圖5、圖7、及円h f/Lf之間的㈣。吾人應必須清楚理解： H:;、及圖8所述之操作亦可藉由儲存於議广譲又或 任一個或其組合之中的軟“序控制糸統）之中的硬碟等 清楚^猎各實施例說明本發明，但熟悉本項技藝之人士應 化型式據以二ΐΐί脫離本發明之精神的情況下，可藉由任一變 其施本剌。故本發狀範_包括上述各實施例及 16 1249786 五、【圖式簡單說明】 =實施例的圖案化的半導體基板。 °颁不依本發明一實施例所附加的額外層。 圖3係顯示依本發明一實施 舰基板。 ra 5 本發實施规行過轉去_程之基板。 ΐ 6AHi—實施織行局种坦化賴作綠之流程圖。 ί之本發明一實施例施加於基板以提高局部均句 度t、運串的化學變化與回蝕製程。 明—貫施例施加於基板哺高局部均皱之化學變 化/、回蝕製程的操作方法之流程圖。 y為依本發明-實__正_不_度_作方法之流程 圖9顯示依本發明-實施_實質上已去除並平坦化的表層部。 元件符號說明： 100、600 基板 102、104、106 特徵部 110 阻障層 112、112’、602、602,、9〇2 表層部 114、116、118局部性變異（或局部性不平坦度） 120 導電性互連材料 202、604 額外層 204 保形層 402 遮罩層 500、800 操作方法 505、510、515、705、710、715、805、810、815、820 操作 606、606’、606’ ’ 輪靡 17

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  1. Ϊ249786 十、申請專利範圍·· 圖案化的半導體基板之平坦化方法， 妾收-圖案化的半導體基板之步 & 圖案之中的複數之特徵部的一導雷性互^縣板具有填滿5亥 材料么有;，部，而該 主體部，俾平坦化該表層部之步驟Γ 驟；及只貝局科坦化的表層部，俾確定—總體不均勾度之步 不均ίΓϋΐ部平坦化的表層部予以師俾實質上消除該總體 ❿ 在表層部之上形成額外層之步驟；及 上完表層部加以平坦化之步驟，此平坦化步驟實質 3中項之圖案化的半導體基板之平坦化方法，其 干°亥5層领主體部之去除步驟包含以下步驟： 藉由以解方式轉變該表層部之 層部之上形成-額外層之步驟；及㈣’而於该表 表气部的至少局部與該額外層之步驟，俾實質地平括化 錢層部，而實質上完全去除該額外層。 貝貝针l化 4中如範圍第2項之瞧―轉縣板之平坦化方法，1 Γΐίί杨部之相化步㈣含如下之反㈣步ί 名虫刻该額外廣的步驟； 形成一第二額外層的步驟；及 名虫刻该弟二額外層的步驟。 5中第1項之難化的半導縣板之平坦化方法，t 中用以確U總體不均勻度之該實質上局部平坦化的表層部之映、 18 1249786 括利用一渦電流感測器將該實質上局部平坦化的表層 平坦化，，其 包括現場地映射該實f上局部平坦部之映 中用化方法，其 情況下實質上消除職體不數之特徵箱賴械性應力的 ^如申請專利範圍第丨項之圖案化 中用以實質上猶該總體不㈣度之#坦化方法，其 部之_，係包括進行層 上的一阻障層露出。 X圖案化的特徵部之 其 10. 如申請專利範圍第9項之圖案 中刻步驟對雜障層具有選擇 =¥體基板之平坦化方法， 11. 如申請專利範圍第9項之圖案化的半導 中用以實質上耻該_不均皱t 平坦化方法’其 部之钮刻步驟係包括實質最小化數特坦化的表層 互連材料的任何凹陷。 讀数之特试部之中的該導電性 更 19 1249786 1 二第1項之圖案化的半導體基板之平坦化方法，其 中该導電性互連材料含元素銅。 一 1 士專利範圍第1項之圖案化的半導體基板之平坦化方法，复 中该圖案躲—雙道金屬鑲嵌過財形成在刻案制半導體基、 板之上。 17·-種半導體裝置_成方法，包含以下步驟： 囝索化的半導體基板之步驟’該半導體基板具有填滿該 Ξϋ的ΐί之特徵部的—導電性互連材料，且該導電性互連 材枓具有-表層部’而該表層侧具有—局雜不均勻度； 去，該^層部的-主體部，俾平坦化該表層部之步驟； * /Γίΐ質上局部平坦化的表層部進行映射，俾確定一總體不均 习度之步驟，及 對该貫質上局部平坦化的表層部断_ 體不均勻度之步驟。 ^ 18. -種雙道金屬做互連結構的形成方法，包含町步驟·· 板且嵌圖案化的半導體基板之步驟，該半導體基 =材料，且該導電性互連材料具有—表 ^ 有一局部性不均勻度； 具 去除該表層部的-主體部，俾平坦化該表層部之步驟，包括： 於该表層部之上形成一額外層之步驟；及 七將該額外層與該表層部平坦化之步驟，該平坦化步驟 上完全去除該額外層； 、、 勻度Ιίΐ質i局部平坦化的表層部進行映射，俾確定一總體不均 體不平坦化的表層部進行侧，俾實質上消除該總 19. -種雙道金屬鑲嵌互連結構的形成方法，包含以下步驟： 20 1249786 接收一雙道金屬鑲嵌圖 =有填滿該雙道金屬鑲嵌圖案驟’該半物基 有性互•料料—表層部 •驟，包括 變 去= 表層層 表:之步 _二層頂部 勾度平坦化的表層部進行映射，料定-總體不均 體不之：糊州物渴】，俾實質上消除該總
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US6939796B2 (en) 2005-09-06
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WO2004084266A2 (en) 2004-09-30
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EP1604393A2 (en) 2005-12-14
CN1788340A (zh) 2006-06-14
CN1788340B (zh) 2011-08-31
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KR20110101222A (ko) 2011-09-15
IL170852A (en) 2010-06-30

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