TWI237315B - Memory and access device - Google Patents

Memory and access device Download PDF

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TWI237315B
TWI237315B TW092114451A TW92114451A TWI237315B TW I237315 B TWI237315 B TW I237315B TW 092114451 A TW092114451 A TW 092114451A TW 92114451 A TW92114451 A TW 92114451A TW I237315 B TWI237315 B TW I237315B
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memory
access
chalcogenide
access device
item
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TW092114451A
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TW200410327A (en
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Ward D Parkinson
Tyler Lowrey
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Ovonyx Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode

Description

1237315 玖、發明說明： I：發明戶斤屬之技術領域】 本發明係有關於記憶體及存取元件。 【先前技術】 5 發明背景 10 〜肢儿什优用和雙式柯料用於電子記憶體用 途，相變式材料亦即可介於概略非晶態與概略結晶態間電 性切換之材料。一類型記憶體組件利用相變式材料，該相 2式材料於-項應用中’介於概略為非晶之結構態與概略 之局㈣相電㈣換，鱗完全非㈣與完全結 ::、二整個砣圍介於局部順序之不同可偵測態間電性切 態:二=料為非依電性’換言之當設定於結晶 有至由另_程切_/ ^表不電阻值，該值保 15 或物理態⑽域晶或非晶）。 4表吨料之位相 之 料。電晶體或二極體__二二=存取相變式材 基材頂面上。電日@±^ 、夕早日日基材内或矽單晶 20 可加大記憶體晶胞尺寸，因而對⑽大部分，因此 片之成本/位元產生不良影響。〜體各賴及記憶體晶 Γ發明内容】 簡3之，根據本發明之一星^ 體。記憶體包括-記憶體组細及Γ例提供一種記憶 弟一存取元件其係耦 1237315 合至該記憶體組件，其中該第一存取元件包含第一硫族化 物材料。記憶體進一步包括一第二存取元件其係耦合至該 第一存取元件，其中該第二存取元件包含一種第二硫族化 物材料。 5 圖式簡單說明 第1圖為示意圖顯示根據本發明之一具體實施例之記 憶體；以及 第2圖為根據本發明之具體實施例於第1圖所示記憶體 部分之剖面圖； 10 第3圖為線圖顯示一記憶體晶胞之電流-電壓特性；以及 第4圖為線圖顯示一選擇元件之電流-電壓特性。 【實施方式3 較佳實施例之詳細說明 選擇元件120可用於記憶體組件130之程式規劃或讀取 15 期間存取記憶體組件130。選擇元件120可呈開關操作，該 開關依據跨記憶體晶胞施加之電壓量決定而為「關」或 「開」。關態為實質非導電態，開態為實質導電態。例如選 擇元件120具有臨限值電壓，若低於選擇元件120之臨限值 電壓之電壓電位跨選擇元件120施加，則選擇元件120可維 20 持「關」，或於相對高電阻態，故極少或無任何電流流經記 憶體晶胞。另外，若大於選擇元件120之臨限值電壓之電壓 位準跨選擇元件120施加，則選擇元件120可被「開」，換言 之於相對低電阻態操作，讓電流流經記憶體晶胞。換言之， 若低於預定電壓位準例如低於臨限值電壓係跨選擇元件 1237315 120施加，則選擇元件12〇可於 —Φ茂/ 、隹 貝上非導電怨。若高於預 疋電反位準係跨選擇元 ^ ^ ^ At w則選擇凡件120係於眚 質導電態。選擇元件m 係於具 開關。 冉乍為存取疋件、隔離元件、或 5 10 15 化物施例中，選擇元件12G包含開_料例如硫族 μ 4材料’可稱作為硫族臨限 關。選擇元件12。之開關材料可為位於二電 貝非4料’崎料可重複且可逆地介於較高電阻「關 細如大於約10百萬歐姆)與相對低電阻「開」態(例如約〇 歐姆）間切換’該切換係藉施加預定電流或電壓位準切換。 本具體實施例中，選擇元件™可為二端子元件，其具有電 /瓜電[(ι-ν)特性係類似呈非晶態之相變式記憶體組件之 特性、。但不似相變式記《組件，元件120之切換材料 可月b並非相變式。換言之選擇元件1觀切換材料可能並非 可程式規劃材料，結果元件⑽可能鱗可儲存資訊之 記憶體元件。例如選擇元件12 G之切換材料維持持久為非曰 形，^特性於整個操作壽命漏維持相同。為非日曰 第1圖為不意圖顯示記憶體100之具體實施例。本具體 實施例中，記憶體晶胞ΠΜ19各自包括選擇元件12〇、一選 20擇το件125以及記憶體组件13〇。總急變彈回減少，俾允許 使用較低臨限值記憶冑組件。例如若該對硫族開關之總Vth 為約2伏特，則各開關之個別Vth經由適當選擇切換材料厚 度為約1伏特。若VH各自例如為約0.8伏特，則若使用單一 凡件，急變彈回由約丨.2伏特降至約〇·4伏特。此種堆疊之開 1237315 關組件串列組可降低於讀取期間干擾位元之傾向。此種堆 疊係由—開關、二開關或多個開關與記憶體組件串聯組 成，全部皆位於列線及行線間而輔助可靠之記憶體選擇與 操作。 5 ★〜文&明’ &憶體組件13G及選擇元件12G及125係於 串聯配置連結。-具體實施例巾，選擇元件㈣及⑵可為 硫族開關，記憶體組件130可為硫族記憶體。 參照第2圖，顯示根據本發明之另—具體實施例，記憶 體100之記憶體晶胞(例如115)之一具體實施例。記憶體晶胞 10 U5包含基材240，絕緣材料26〇覆於基材24〇之上，傳導材 料270覆於絕緣材料26〇之上。傳導材料27〇可為位址線(例 如列線152)。於傳導材料27〇上方，電極34〇可形成於部分 絕緣材料280間。於電極340上方，可沉積循序各層記憶體 材料350、電極材料360、切換材料920、電極材料930、切 15換材料940、電極材料950及傳導材料980而形成立式記憶體 晶胞結構。傳導材料980可為位址線(例如行線142)。 第2圖所示具體實施例中，選擇元件125及12〇形成於記 憶體組件130上方，而形成串聯耦合之薄膜立式結構或立式 堆。其它具體實施例中，記憶體組件13〇可形成於選擇元件 20 120及125上方，或記憶體組件130可形成於選擇元件120與 125間來形成串聯耦合之薄膜立式結構。於第2圖所示具體 實施例中，選擇組件120及125以及記憶體組件130可使用薄 膜材料製成，立式堆稱作為薄膜立式堆。 第2圖所示具體實施例中，記憶體材料350及電極34〇 1237315 及360可形成記憶體組件130。記憶體材料35〇為硫族材料或 硫紅化物材料，而可稱作為硫族記憶體。切換材料920及電 極360及930可形成選擇組件125。切換材料92〇可使用用來 製成此處所述切換材料22〇之類似材料及類似製造技術製 5 成。切換材料940及電極930及950可形成選擇元件12〇。切 換材料940可使用類似此處所述用於製成切換材料22〇之類 似材料及類似製造技術製成。另一具體實施例中，切換材 料920及940可由相同材料或不同材料製成。例如一具體實 施例中，切換材料920係由硫族化物材料製成，切換材料94〇 10 係由另一種不同的硫族化物材料製成。 一具體實施例中，選擇組件120及125可為硫族開關， 記憶體組件130可為硫族記憶體，記憶體晶胞115可稱作為 硫族記憶體晶胞。如前文討論，選擇組件120之I-V特性範 例顯示於第4圖。選擇組件125具有類似第4圖所示之仁¥特 15 性。 回頭參照第3圖，顯示記憶體晶胞115之i-v特性範例， 本具體實施例中，記憶體晶胞115可包括記憶體組件13〇及 選擇組件120及125。記憶體晶胞115之維持電壓（標示為vh) 係得自選擇組件120及125以及記憶體組件13〇之維持電 20壓。記憶體晶胞115之臨限值電壓等於記憶體組件13〇之選 擇元件120及125之組合臨限值電壓。 由此處討論可知，選擇元件或硫族開關之臨限值電壓 可由硫族開關之切換材料之厚度或合金組成決定；硫族開 關之維持電壓可由接觸硫族開關之切換材料之電極組成決 1237315 定。如此，一具體實施例中，急變彈回電壓，亦即硫族開 關之臨限值電壓與維持電壓間之電壓差，可經由縮小切換 材料厚度以及使用特定類型電極予以減低。 例如參照第2圖所示之選擇元件120，若電極93〇及950 5為碳層，且若切換材料940之厚度為約200埃，則選擇元件 120之維持電壓約為丨伏特，以及選擇元件12〇之臨限值電壓 約為1.2伏特。本實施例中，急變彈回電壓約〇·2伏特，該電 壓為選擇元件120之維持電壓與臨限值電壓間之電壓差。 第2圖所示具體實施例中，記憶體晶胞115包括兩個硫 10族開關串聯耦合至一硫族記憶體，來於需要較高切換電壓 以及維持電壓時，降低記憶體之維持電壓與臨限值電壓間 之電壓差。換言之，替代使用一個硫族開關，兩個硫族開 關可串聯耦合至一硫族記憶體來於需要較高切換電壓及維 持電壓時，減少記憶體晶胞之「急變彈回」，換言之降低硫 15族記憶體晶胞之臨限值電壓與維持電壓間之電壓差。 一具體實施例中，電極360、930及950為碳，切換材料 920厚度約為200埃，切換材料94〇厚度約為2〇〇埃。本具體 實施例中，選擇元件120之臨限值電壓約為L2伏特，選擇 元件120之維持電壓約為丨伏特。選擇元件125之臨限值電壓 20約為丨·2伏特，選擇元件125之臨限值電壓約為1伏特。若復 置/設定記憶體組件130之臨限值電壓約為〇·8/〇·〇伏特，則對 分別於復置態以及設定態之記憶體晶胞115而言，記憶體晶 胞115之fe限值電壓約為3.2/2.4伏特，亦即記憶體組件丨3〇 與遥擇元件120及125之組合£}?»限值電壓。換言之，高於約 I237315 3.2伏特之電壓位準可跨記憶體晶胞U5施加來「開」選擇元 件120及125且導引電流流經記憶體晶胞U5。經由施加大於 約3.2伏特之電壓位準至行線142、以及施加約〇伏特之電壓 位準至列線152，跨記憶體晶胞115可施加大於約3·2伏特之 5 電壓。 本例中’為了程式規劃選定之記憶體晶胞例如記憶體 曰曰胞115’約1.8伏特之電壓可施加至未經選定行線及未經選 定之列線，例如線141、143、151及153。大於約3.2伏特電 壓可施加至一選定行線例如142，〇伏特可施加至一選定列 線例如列線152。本例中，於選擇元件120及125「開」之後， 因急變彈回故，跨記憶體晶胞115之電壓降可由約3.2伏特降 至約2.0_2.8伏特，依據晶胞之記憶態以及行提供之電流決 定。然後經由迫使電流流經記憶體晶胞115，同時確保選定 之行線維持於未經選定之列線(偏差約1·8伏特）之約2·4伏特 15範圍内，讓未被選定之記憶體晶胞不受干擾，資訊可儲存 於記憶體組件130。換言之程式規劃期間，不允許行電壓高 於約4·2伏特。 第3圖以線圖舉例說明本例，其中對完整記憶體晶胞 (王°卩3個組成元件結合），對復置態及設定態VTH分別為 2〇 3·2/2.4伏特，以及VH為2.8伏特。流經記憶體晶胞115之電 流接近〇安培直到臨限值電壓VTH例如超過約3·2或2·4伏特 為止，此數值分別係依據記憶體晶胞為復置態或設定態決 定。然後隨著電流的升高，跨記憶體晶胞115之電壓降至（對 復置位元而言）或爬升至（對設定位元而言）維持電壓Vh，例 11 1237315 如約2.8伏特。 本例中’為了讀取儲存於選定之記憶體晶胞之資訊 值，跨記憶體晶胞115可施加約2·8伏特電壓。記憶體組件13〇 之電阻可經感測來判定記憶體組件130是否於低電阻結晶 5 之「設定」態（例如低於約1〇,〇〇〇歐姆）、或記憶體組件130 是否於南電阻非晶之「復置」態（例如大於約1〇,〇〇〇歐姆）。 另一具體實施例中，為了讀取儲存於選定之記憶體晶 胞之資訊值，經由施加2.8伏特至選定之行、以及〇伏特至 選定之列、以及1.4伏特至全部其它未經選定之列及行，跨 10記憶體晶胞U5可施加約2.8伏特電壓。可感測由選定行至選 定列之電阻，來判定記憶體組件13〇是否於低電阻之結晶 「設定」態，或記憶體組件130是否於高電阻非晶之「復置」 態。本具體貫施例中，對復置態案例而言，串聯選定元件 可能未「開」，如此介於選定行與選定列間也提供高電阻。 15 須了解前述實施例絕非囿限本發明。經由變更切換材 料920及940厚度以及變更電極36〇、93〇及95〇組成，可達成 其它維持電壓及臨限值電壓來變更記憶體晶胞之急變彈 回減低5己憶體晶胞之急變彈回之一項優勢為流經記憶體 晶胞之電容異位電流減少，士口此減低讀㈣干擾一位元成 20 為不同態之傾向。 其它具體實施例中，第2圖所示記憶體晶胞115<以不 同方式配置，且包括其它層及其它結構。例如可能希望形 成隔離結構、喊層、周邊電路(例如定址電路）等。記憶體 晶胞另外可為鐵電材料或鐵磁材料，具有藉不同電流或極 12 1237315 性程式規劃之不同位相，結果當規劃成不同態時獲得不同 阻抗。另外，記憶體晶胞可為任何其它可由小型存取獲益 之材料或。須了解不存在有此等組件並非囿限本發明之範 圍。 5 雖然於此處已經舉例說明本發明之若干特色，但熟諳 技藝人士顯然易知多種修改、取代、變化及相當例。因此 須了解隨附之申請專利範圍意圖涵蓋落入本發明之真諦範 圍内之全部此等修改與變化。 【圖式簡單說明】 10 第1圖為示意圖顯示根據本發明之一具體實施例之記 憶體；以及 第2圖為根據本發明之具體實施例於第1圖所示記憶體 部分之剖面圖； 15 第3圖為線圖顯示一記憶體晶胞之電流-電壓特性；以及 第4圖為線圖顯示一選擇元件之電流-電壓特性。 【圖式之主要元件代表符號表】 152.. .列線 240.. .基材 270.. .傳導性材料 280.. .絕緣材料 340.. .電極 350.. .記憶體材料 360.. .電極材料 920，940...切換材料 100…記憶體 111-119...記憶體晶胞 120…選擇元件 125…選擇 130...記憶體組件 141，143，151，153·.·未經選 定的行線和列線 142…行線 13 1237315 930，950…電極材料

Claims (1)

1237315 拾、申請專利範圍： I 一種記憶及存取裝置，包含： 一記憶體組件； 一第一存取元件’其_合至該記憶體組件，其中 該第-存取元件包含-種第一硫族化物材料；以及 -第二存取元件’其_合至該第—存取元件，复 中該第二存取元件包含-種第二魏化物材料。、 2·如申請專利範圍第i項之記憶及存取裝置，進一步包含 -立式結構於—基材上，其中該立式結構包含該第—存 取疋件、該第二存取元件、以及彼此串_合之記憶體 3.如申請專利範圍第1項之記憶及存取裝置，其中該第— 存取7G件、該第二麵元件及記龍組件係制 料製成。 τ .如申4專利㈣第1項之記憶及存取裝置，其中該第二 存取元件係於第-存取元件上，以城第—存取元件: 於記憶體組件上。 I如申請專利範圍第1項之記憶及存取裝置，其中該第一 選擇：件包括一種切換材料，其係呈實質非晶態，及其 適:藉她加預定電壓或預定電流，而重複且可逆地介於 幸又阿電阻悲與相對較低電阻態間切換。 6·:广專利範圍第i項之記憶及存取裝置，Μ該記憶 、,π ^ 種相變式材料，經由施加電流至相變式材 ^羑更相變式材料之相介於實質結晶態與實質非晶態 15 1237315 間改變，該相變式材料經程式規劃呈至少兩種記憶體態 之一’其中呈貫質非晶態之相變式材料之電阻係南於呈 實質結晶態之相變式材料之電阻。 7. 如申請專利範圍第1項之記憶及存取裝置，其中該記憶 5 體組件包含一種記憶體材料於一基材上；以及其中該第 一硫族化物材料係於記憶體材料上，以及該第二硫族化 物之材料係於第一硫族化物材料上。 8. 如申請專利範圍第7項之記憶及存取裝置，進一步包含： 一第一電極介於該記憶體材料與該第一硫族化物 10 材料間；以及 一第二電極介於該第一硫族化物材料與該第二硫 族化物材料間。 9. 如申請專利範圍第8項之記憶及存取裝置，其中該第一 電極及該第二電極為碳薄膜。 15 10.如申請專利範圍第7項之記憶及存取裝置，其中該第一 硫族化物、第二硫族化物及記憶體材料各自包含碲。 11.如申請專利範圍第7項之記憶及存取裝置，其中該第一 硫族化物材料為一種選自矽、碲、砷、鍺、及其組合組 成的組群之材料。 20 12.如申請專利範圍第7項之記憶及存取裝置，其中該記憶 體材料為一種碲、銻、鍺合金。 13. —種記憶及存取裝置，包含： 一第一硫族開關； 一第二硫族開關，其係I馬合至該第一硫族開關；以 16 1237315 及 一記憶體組件，其係耦合至該硫族開關。 14. 如申請專利範圍第13項之記憶及存取裝置，其中該記憶 體組件、該第一硫族開關及該第二硫族開關係使用薄膜 5 材料製成。 15. 如申請專利範圍第13項之記憶及存取裝置，進一步包含 一立式結構於一基材上，其中該立式結構包含該第一硫 族開關、第二硫族開關及記憶體組件彼此串聯耦合。 16. —種記憶及存取裝置，包含： 10 一記憶體材料於一基材上； 一第一電極於該記憶體材料上； 一第一硫族化物材料於該第一電極上； 一第二電極於該第一硫族化物材料上；以及 一第二硫族化物材料於該第二電極上。 15 17.如申請專利範圍第16項之記憶及存取裝置，其中該記憶 體材料、第一電極、第一硫族化物材料、第二電極及第 二硫族化物材料形成於該基材上之一立式堆疊之一部 分。 18. 如申請專利範圍第16項之記憶及存取裝置，其中該記憶 20 體材料、第一電極、第一硫族化物材料、第二電極及第 二硫族化物材料各自為薄膜材料。 19. 一種記憶及存取裝置，包含： 一記憶體晶胞，其具有維持電壓，其中該記憶體晶 胞包含： 17 1237315 一記憶體組件；以及 至少二串聯耦合存取元件，其係耦合至該記憶體組 件俾提高記憶體晶胞之維持電壓。 20. 如申請專利範圍第19項之記憶及存取裝置， 5 其中該記憶體組件包含一種相變式材料；以及 其中該二串聯耦合存取元件中之一第一存取元件 包括第一硫族化物材料；以及其中該二串聯耦合存取元 件中之第二存取元件包含第二硫族化物材料。 21. 如申請專利範圍第20項之記憶及存取裝置，其中該第一 10 硫族化物材料係與該第二硫族化物材料不同。 22. 如申請專利範圍第19項之記憶及存取裝置，其中該至少 二串聯耦合存取元件中之一第一存取元件、該至少二串 聯耦合存取元件中之一第二存取元件以及該記憶體組 件係使用薄膜材料製成。 15 23. —種記憶及存取系統，包含： 一處理器； 一無線介面，其係耦合至該處理器；以及 一記憶體，其係耦合至該處理器，該記憶體包括： 一記憶體組件； 20 —第一存取元件，其係耦合至該記憶體組件，其中 該第一存取元件包含一種第一硫族化物材料；以及 一第二存取元件，其係耦合至該第一存取元件，其 中該第二存取元件包含一種第二硫族化物材料。 24.如申請專利範圍第23項之記憶及存取系統，其中該記憶 18 1237315 體組件包含一種記憶體材料於一基材上；以及其中該第 一硫族化物材料係於記憶體材料上，以及該第二硫族化 物之材料係於第一硫族化物材料上。 25.如申請專利範圍第23項之記憶及存取系統，其中該記憶 5 體進一步包含一立式結構於一基材上，其中該立式結構 包含該第一存取元件、該第二存取元件及該記憶體組件 彼此串聯耦合。 19
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