TWI234290B - Capacitor in semiconductor device and method for fabricating the same - Google Patents

Capacitor in semiconductor device and method for fabricating the same Download PDF

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TWI234290B
TWI234290B TW091137967A TW91137967A TWI234290B TW I234290 B TWI234290 B TW I234290B TW 091137967 A TW091137967 A TW 091137967A TW 91137967 A TW91137967 A TW 91137967A TW I234290 B TWI234290 B TW I234290B
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layer
capacitor
item
silicon nitride
silicon
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TW091137967A
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TW200403863A (en
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Cheol-Hwan Park
Dong-Su Park
Tae-Hyeok Lee
Sang-Ho Woo
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Description

1234290 I 1、驶明說明（】） 【本發明所屬之技術領域】 更特：二關於一種半導體元件之電容器及其形成方法， 性ΐϊΐ。： 一種具有：Ϊ之漏茂電流和絕緣破壞電壓特 『件之電容器及其形成方法。 几士在一般所知的技藝中’半導體々橫雕-从丄 化時，其晶胞大小（cell Slze)減姐丨5己隐/广件當其高度積體 的減小會伴隨著電容器面積的成小。口此，由於晶胞大小 所要求的維持-定所需要的電ί:，故確保記憶元件特性如 一舉例來說，就64 M DRAM等里，有其困難性。 :，晶胞大小伴隨積體化 、，及之上的高度積體化元件而 此，以習見的電容器構造，^升高而被嚴重地縮小。因 為不可能的。 呆晶胞動作所需要的電容量， 因此，近來之高度積體 ;種2構造，以確保獲，電荷儲存電極乃 限的薄厚度被薄沈積。|電層材料，或者介電層係以最： 這是因為電容器之電 層之介電，，反比於-上部匕於電容器之表面積和介f 錐，也就是，實質上為介恭】σ和下部電極間之間隔距 因此，例如，下部電:層之大約厚度。 (concave)構造、或栓（pi^破形成為圓柱構造、凹入 而藉此增加電容器之電容1構，，以增加電極之表面面積， 被使用為介電材料，以抛f ,向介電比材料例如Ta2〇5或 _ 電容器之電容量；而且-由N/0 1234290 五'、發明說明（2^ ~一' ---- 物/氧化物）多層體（multlple layers)構成之 已错由減少介電層之厚度而被利用來六_ 得玲’ ^ 电合詻之雷交黑 、然而，就使用高介電比材料而增加電容器之+二合量。 言’由於減少介電層厚度之限制’如下招致數個；ςι而 特別是，就使用Ν/0多層體或使用高介雷 ?m5鑛而言，近來之技術遭遇在下::；匕：材料例如 r 口丨包極和介電a μ人 =的限制。因此，電容器可經由使用Ν/〇多層體口二 電材料例如Ta205或BST為介電層材肖，而減小介電層之；二 ，而使其電容量增加。然而，由於在 曰 ^ ΚΙ:而使得漏繼和絕緣破壞電壓等等特性；， 此k成可靠程度和生產良率的降低。 4化 結果，在使用N/0多層體或高介電材料例如Ta 為"電層材料之此發展階段，如此材料 二5 一 良傘夕it夂& α * 刊丁十仏成可菲程度和生產 民+之降低，所以為了要增加半導體座 很難去採用它們。 仟w益之電容量’ 人乃之半導體元件之電容器有上述之缺點，發明 遠些缺f研究改進之道’終於有本發明的產生。 L本發明之内容】 仏工 題，發明乃旨在解決發生在習見技藝中之上述問 或古明之-目的乃是提供-種藉由使用N/0多層體 :二电材枓例如Ta2〇5或BST為介電層材料， 緣破壞電壓特性之劣化之半導體元件的電容器及其 為了要達成此目的，本發明乃提供一種半導體元件之電
m 1111
«I _圓__ 第8頁 1234290
五、發明說明（3) 谷器’其包含：一形成在半導體基板上’捧雜石夕 、 ’ <衬料所fj 成之下部電極；一形成在}^部電極上之薄氮化；ς夕展· / /曰 ， 一* 以^ 氣 化矽層之氧化作用，形成在氮化矽層表面上之氮氧化砂 ^ 一形成在氮氧化矽層上之介電層；以及一形成在介電屏 ’ 上部電極。 ^㈢上之 、 在上述之電容器中，下部電極被形成從一平板構造、_ 圓枉構造、一凹入構造、和一插銷構造所構成之群中，所、 擇之一種構造，並且被形成在其表面上，具有半球型石夕顆粒 (hemispherica1 si1icon graiη)者。 , 而且，氮化矽層係形成至一 5到3 0 A的厚度，氮氧化石夕 則形成從氮化；ε夕的表面有一在1 5 A以下的厚度者。 再者，介電層以N/0或Ta205所製成。 為了要達成此目的，本發明也提供了一種半導 電”的形成方法，其步驟包含：在一半導體基板上= ，：：：之材料所製成之下部電極；在下部電 =心：氣：妙層之表面上上，以氮…之氧^ 層1形成一：部=…層上沈積-介電層；並且… 柱構ί以士：：二：：下部：：形成由從-平板構造、-圓 之-種構造，並構造所構成之群中，所選擇 (hemisPhericai sili=在其表面/ ’具有半球型石夕顆粒 丄1 con graiη)者。 同樣地，沈積薄务^u 程序、一 _气化^化石夕層之步驟是由從一電細3氮化 3鼠化以、以及一LPCVD程序所構成之群中，
第9頁 1234290 五、發明說明（4) 選擇之一種程序進行，並且氮化矽層沈積5到3 0 A之厚度。 根據本發明之實施例，矽氮化層之氧化作用是進行從_ 電漿強化氧化作用（plasma enhanced oxidation)、一低壓 氧化作用（low pressure oxidation)、常壓氧化作用 (atmosphere pressure oxidation)、和一在氧氣環境中之 自然空氣冷卻程序之群中，所選擇之一種程序，以形成厚度 低於1 5 A之氮氧化矽層。 再者，在以上之方法中，介電層以N/0或TaJ5所製成， 並且以一使用A、I、或N/0之熱處理，進行介電層之後處 理。 同樣地，在上述之方法中，使用從I、\、和叩之群中 ，所選擇之任一種氣體所沈積之介電層，其後處理在形成 部電極前和沈積介電層之後進行。 依照本發明之形成方法，沈積氮化矽層、氧化氮化石夕 層、沈積介電層、和進行介電層之後處理等步驟，以一種在 原處（in-situ)或無延時（no time delay)之方式被完成。 【本發明之實施方式】 ° 至於本發明之詳細構造、應用原理、作用與功效，則夾 照下列依附圖所作之說明即可得到完全的了解。 > 第1 A圖到第1 E圖為說明根據本發明之實施例中之一種 導體元件之形成方法之截面圖。 參照第1 A圖，-摻雜矽層被沈積在裝備了預期之下部基 層（圖未示）之半導體基板i，經由對摻雜矽層刻晝圖樣以 形成-下部電極2。在這情況中，雖然下部電極2被描述為平
1234290 五、發明說明（5) 板形式，為了要增加電容器之電容量，其可被形成一圓柱構 造、一凹入構造、或一插銷構造，並且可在其表面上形成一 半球型矽顆粒（HSG : hemispherical silicon grain)者。 參照第1 B圖，一清潔程序在下部電極2被形 ;二所得構造上被進行。然後，一薄氣化康\積在中下之部 ^極2之表面上，以改進在介電層間之介面特性。在這 :田=氮化石夕層3可由使用N-LPCVD之氮化石夕層之沈積程序、 程序；m處f之氮化程序、或使用-細3處理之氮化 矛砰，寻而被沈積，更好地是5到3 0 A之厚度。 面^照㈣圖，進行一氧化處理，以氧化又氮化石夕層之表 sUi “匕在虱化矽層3之表面上形成-氮氧化矽（SiOxN : 面層4。當進行氧化處理時，氮化♦層 址（^ ? 微地氧化，而除去在層中之缺陷例如栓孔和陷 ^ ^ ^ #L ^ Ϊ^ ^ ^ ^ ^ ^ ，特別是阻止了: Λ 了下部電極和介電層間之介面特性 ⑶Hent),而葬此之矽氮化層中之電洞流（h〇k 壞電壓，也就η ’〆在電容器中之漏洩電流並增加絕緣破 再者，i;化：壞電容器絕緣之電壓。 比氮化矽層3更好片虱化夕層，也就是氮氧化矽層4，具有 在、介電層沈積之、之氧化龟阻（oxidation —resistance)時， 理之後，Ta2〇5電=二也就是在⑽〇電容器中之熱氧化或10處 此阻止氧氣擴散=為中之後處理變得比傳統例中的好，藉 月 入構成下部電極之摻雜矽層，造成防止介
第11頁 1234290
1234290 五、 矽 而 被 減 其 同 半 之 1] 圆 器 統 電 化 發明說明（7) "~ ----- ，根據本發明之半導體元件之電容器製造方法，一薄氮化 ^ t次積在構成下部電極並氧化其表面之摻雜石夕層之上， 然後 -入. 、 電層被沈積，藉此減輕介面應力並阻止在介面中 限制之電荷。 〜 特別地，矽氮氧化層在沈積介電層時充當緩衝層，藉此 輕微痛1 、 ‘力（nucro —stress)並阻止氧氣擴散進入摻雜矽層， 漏成作為好的氧化電阻生成物之下部電極，從而完成在相 :洩電流和絕緣破壞電壓之情況下，具有比傳統例更高的 V體元件之電容器產物。 …、第2 A圖和第2 B圖為說明根據本發明之電容器之電子特性 兒月圖’其中第2A圖為表示施加電壓和電流密度間之關係 〇且第2 B圖為表不施加電壓和電容器之電容量間之關係 ，參照第2A圖和第2B圖，本發明之具有一〇N〇構造之電容 锒Ϊ中應用被氧化之氮化矽層，I示了-種低漏洩電流和 雷二破壞電壓特性，和一種相較於具有一般〇N〇構造之傳 龟谷器，增加之電容器電容量。 和表2表! 了具有咖構造和Ta2〇5構造之電容器，』 今里和絕緣破壞電壓之測讀姓 矽思办… j ΰ式結果，個別地和應用氧化的 矽層之案例和不使用氧化的氮 ㈣ 1化矽層之案例相符合。 1234290 五、發明說明（8) 第1表
塊狀元件之測試値 電容量 絕緣破壞電壓(V) 一^般0N0電容器 33.14 fF/cell ^〜—-- 改進値 2.37 Ff/cell 3.41V 改進値 0.11V 應用氧化之氮化矽層之 0Ν0構造 35.51 fF/cell 3.52V (第2表）
量 絕緣破壞電壓(V) 改進値 3.7V 1.6 改進値 fF/cell 4.IV 0.4V -—-—-—--—__^ 平板電容器之測試値 電容i 進行NH3預處理之Ta2〇5 電容器 10.9 fF/ βπ\2 應用氧化之氮化矽層之 Ta205電容器 12.5 fF/μιη2 如第2 A圖和第2 B圖所 不 * 並如 用一氧化之氮化矽層 之本發明 U 乳π及虱化矽層之本發明雷办π主a々 哭萝姑的：昆％命谷器表現了比傳統電容 為更好的漏洩笔流和絕緣破壞電壓特性，藉此能夠阻止介電 比的減少，並在相同漏洩電流和絕緣破壞電壓的情況下，提 供比傳統電容器更高的電容量。 如上所述，依照本發明所形成之半導體元件電容器由於
1234290 五、發明說明（9) 一氮化矽層的沈積和其表面之氧化而改進了下部 層間的介面特性，藉此阻止了在施加一偏壓到電 致漏洩電流減少、絕緣破壞電壓增加、以及可靠 良率二者之改進之空洞電流。 同樣地，本發明在進行介電層的後處理時， 擴散到下部電極，藉此防止介電層整體介電比之 致電容器電容量增加。 需陳明者/以上所述者乃是本發明較佳具體 若依本發明之構想所作之改變，其產生之功能作 出說明書與圖示所涵蓋之精神時，均應在本發明 合予陳明。 電極和介電 容器時，導 程度和生產 可防止氧氣 劣化，而導 的實施例， 用，仍未超 之範圖内，
1234290 圖式簡單說明 第1 A圖到第1 E圖為說明根據本發明之實施例中之一種半 導體元件之形成方法之截面圖； 第2 A圖和第2 B圖為說明根據本發明之電容器之電子特性 之說明圖。 【圖示中元件編號與名稱對照】 1 :半導體基板 、 2 :下部電極 3 :氮化矽層
4 :氮氧化矽層 5 :介電層 6 :上部電極 10 :電容器
第16頁

Claims (1)

1234290
六/'申請專利範圍 1 . 一種半導體元件之電容 元件之電容器，其包& , ° ”特徵在於，是種半 . 形成在半導妒其说卜 部電極； 1 土而由摻雜矽之材料所製成 —形成在下部電極上之薄氮化 一以氮化矽層之象於，4 、 化矽層； 破形成在氮化矽層表面上之 一形成在氮氧化矽層上之介電層； 一形成在介電層上之上部電極。 1中下$ t ί利範圍第1項所述之半導體元件之電容丨 [和二從一平板構造、-圓柱構造、-凹 3.如中，戶斤選擇之-種構造。 其中下部常二、利乾圍第1項所述之半導體元件之電容丨 。4由形成在其表面上，具有半球型石夕顆粒者 豆中3利範圍第1項所述之半導體元件之電容； 〃宁虱化矽層形成5到30人之厚度。 盆中I· t申請專利範圍第1項所述之半導體元件之電容！ 二虱乳化矽層被形成為具有從氮化矽層表面 1 5 A之厚度者。 ％ 6 ·如申請專利範圍第丨項所述之電容器，1中 N/0或Ta2〇5所製成。 /、 弘^ 種半導體元件之電容器形成方法，其特徵在於 種半導體元件之電容器之製造方法，其包含下列步驟： 在 半導體基板上形成一以摻雜石夕之材料所製成之 導體 之下 氮氧 巻， 入構 音， 〇 f， i， 於 I以 ，是 下部 1234290
電極； 在下部電極上沈積一薄氮化矽層； 在氮化矽層之表面上，以氮化矽層之氧化形成一 石夕層； 从孔化 在氮氧化矽層上沈積一介電層；以及 、 在介電層上形成一上部電極。 8 ·如申凊專利範圍第7項所述之半導體元件之電容装以 成方、、-θ- _ι_ ^ _ '、，/、中下部電極被形成從一平板構造、一圓柱構造、 凹入構造、和一插銷構造所構成之群中，所選一 造。 计 < 種構 9 ·如 成方法， 粒者。 申請專利範圍第7項所述之半導體元件之電容器带 其中下部電極被形成在其表面上，具有半球型石夕^
10 ·如申請專利範圍第7項所述之半導體元件之電容器形 、方法 其中沈積一薄氮化石夕層之步驟是以從一電浆⑽/氮^ 化私序、_熱㈣3氮化程序、以及_LpcVD程序所構成之 、’所選擇之一種程序所執行。 11 ·如申請專利範圍第7項所述之半導體元件之電容器形 、方法’其中氮化矽層沈積5到3 0人之厚度。
12·如申請專利範圍第7項所述之電容器形成方法，其中 化虱化層=氧化作用是以從一電漿強化氧化作用、一低壓氧 j，用、¥壓氧化作用、和一在氧氣環境中之自然空氣冷卻 王、所構成之群中，所選擇之一種程序所執行。 士申明專利範圍第7項所述之半導體元件之電容器形
第18頁 1234290 六、申請專利範圍 成方法，其中矽氮化層之氧化作用被執行而形成為從氮化矽 層表面算起厚度低於1 5人之氮氧化矽層。 1 4.如申請專利範圍第7項所述之半導體元件之電容器形 成方法，其中介電層以N/0或Ta2 05所製成。 ' 1 5,如申請專利範圍第7項所述之半導體元件之電容器形 成方法，更進一步包含一種執行沈積介電層之後處理的步 驟，其在形成上部電極前和沈積介電層之後，使用從〇2、n2 、和NO所構成之群中，所選擇之任一種氣體而被執行。
1 6.如申請專利範圍第7項所述之電容器形成方法，其中 沈積氮化矽層、氧化氮化矽層、沈積介電層、以及執行介電 層之後處理等步驟，以一種在原處（in-situ)或無延時（no time delay)之方式被完成。
第19頁
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