CN1280909C - 半导体装置的电容器及其制备方法 - Google Patents

半导体装置的电容器及其制备方法 Download PDF

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CN1280909C
CN1280909C CNB031035639A CN03103563A CN1280909C CN 1280909 C CN1280909 C CN 1280909C CN B031035639 A CNB031035639 A CN B031035639A CN 03103563 A CN03103563 A CN 03103563A CN 1280909 C CN1280909 C CN 1280909C
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capacitor
silicon nitride
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semiconductor device
nitride layer
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CN1479377A (zh
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朴哲焕
朴东洙
李泰赫
禹相浩
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SK Hynix Inc
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Abstract

本发明提供一种半导体装置的电容器及其制备方法，本发明的电容器的制备方法包含下列步骤：在半导体基板上形成由掺杂硅的材料(dopedsilicon materials)制成的下部电极；在下部电极上沉积薄氮化硅层；在氮化硅层表面上，通过氮化硅层的氧化形成氧氮化硅层(silicon oxynitride layer)；在氧氮化硅层上沉积介电层；并且在介电层上形成上部电极；依据此方法，在氮化硅层沉积在介电层上之后，对所得的构造进行氧化处理，并且介电层在已被氧化的氮化硅层上形成，藉此改进在下部电极和介电层间的界面特性，并可导致半导体装置电容器的漏泄电流减少和击穿电压增加。

Description

半导体装置的电容器及其制备方法
技术领域
本发明涉及一种半导体装置的电容器及其制备方法，更特别地是涉及一种具有改进的漏泄电流和击穿电压特性的半导体装置的电容器及其制备方法。
背景技术
由本领域常识可知，半导体内存装置高度集成化时，其晶胞大小(cellsize)减小。因此，由于晶胞大小的减小会伴随着电容器面积的减少，故确保存储元件特性如所要求的维持一定所需要的电容量，有其困难性。
例如，就64M DRAM等级之上的高度集成化装置而言，晶胞大小伴随集成化等级的升高而被严重地缩小。因此，不可能以常规电容器构造来确保晶胞活化(activation)所需要的电容量。
所以，最新的高度集成化装置，电荷储存电极被制成各种三维构造，以确保获得上述所预期的电容器电容量，或者使用高介电比材料为介电层材料，或者介电层是以最大限度的薄厚度被沉积。
这是因为电容器的电容量正比于电容器的表面积和介电层的介电比，反比于上部电极和下部电极间的间隔距离，也就是，实质上为介电层的大约厚度。
因此，例如，下部电极被形成为圆柱构造、凹入(concave)构造、或插销(pin)构造，以增加电极的表面面积，而藉此增加电容器的电容量；高介电比材料例如Ta2O5或BST被使用为介电材料，以增加电容器的电容量；而且由N/O(氮化物/氧化物)多层体(multiple layers)构成的薄层，通过降低介电层的厚度来增加电容器的电容量。
然而，就使用高介电比材料而增加电容器的电容量而言，由于降低介电层厚度的限制，带来如下几个问题。
特别是，就将N/O多层体或高介电比例材料例如Ta2O5或BST用作介电层材料而言，最新的技术受到在下部电极和介电层间界面处理的限制。因此，电容器可经由使用N/O多层体或高介电材料例如Ta2O5或BST为介电材料，而减小介电层的厚度，而使其电容量增加。然而，由于在下部电极和介电层间界面的不良，而使得漏泄电流和击穿电压等等特性劣化，此造成可靠程度和生产效率的降低。
如上所述，在使用N/O多层体或高介电材料例如Ta2O5或BST为介电层材料的此发展阶段，这样的材料会造成可靠程度和生产效率的降低，所以为了要增加半导体装置电容器的电容量，很难去采用它们。
由于常见的半导体装置的电容器有上述的缺点，所以发明人针对这些缺点研究改进之道，从而得出本发明。
发明内容
因此，本发明旨在解决现有技术中所存在的上述问题，并且本发明的目的是提供一种藉由使用N/O多层体或高介电材料例如Ta2O5或BST为介电层材料，而能防止漏泄电流和击穿电压特性劣化的半导体装置的电容器及其制造方法。
为了要达到此目的，本发明提供一种半导体装置的电容器，其包含：在半导体基板上形成的，由掺杂硅的材料所制成的下部电极；在下部电极上形成的薄氮化硅层；由氮化硅层的氧化作用，而在氮化硅层表面上形成的氧氮化硅层；在氧氮化硅层上形成的介电层；以及在介电层上形成的上部电极。
在上述的电容器中，所形成的下部电极为选自平板构造、圆柱构造、凹入构造、和插销构造所构成中的一种构造，并且在其表面上形成具有半球型硅颗粒(hemispherical silicon grain)。
而且，氮化硅层所形成的厚度为5到30，所形成的氧氮化硅层的厚度从氮化硅的表面低于15。
再者，介电层以N/O或Ta2O5所制成。
为了要达到此目的，本发明也提供了一种半导体装置的电容器的制备方法，其步骤包含：在半导体基板上形成以掺杂硅的材料所制成的下部电极；在下部电极上沉积(depositing)薄氮化硅层；在氮化硅层的表面上，以氮化硅层的氧化形成氧氮化硅层；在氧氮化硅层上沉积介电层；并且在介电层上形成上部电极。
在以上的方法中，所形成的下部电极选自平板构造、圆柱构造、凹入构造、插销构造所构成之中的一种构造，并且在其表面上形成具有半球型硅颗粒(hemispherical silicon grain)。
同样地，沉积薄氮化硅层的步骤选自等离子体NH3氮化方法、热NH3氮化方法、以及LPCVD方法组成中的一种方法进行，并且氮化硅层沉积5到30的厚度。
根据本发明的实施方案，氮化硅层的氧化作用是选自等离子体强化氧化作用(plasma enhanced oxidation)、低压氧化作用(low pressure oxidation)、常压氧化作用(atmosphere pressure oxidation)、和在氧气环境中的自然空气冷却方法中的一种方法，形成氧氮化硅层的厚度低于15。
此外，在以上的方法中，介电层由N/O或Ta2O5所制成，并且以使用O2、N2、或N/O的热处理，进行介电层的后处理。
同样地，在上述的方法中，选自O2、N2、和NO的中的任一种气体所沉积的介电层，其后处理在形成上部电极前和沉积介电层之后进行。
依照本发明的制备方法，沉积氮化硅层、氧化氮化硅层、沉积介电层、和进行介电层之后处理等步骤，是以一种在原位(in-situ)或无延时(no timedelay)的方式被完成。
附图说明
由下面详细的说明结合附图可以更清楚地了解本发明上述的以及其它的目的，特征和优点。
图1A到图1E说明本发明实施方案中的一种半导体装置的电容器制备方法的截面图；
图2A和图2B为本发明电容器的电特性的说明图。
具体实施方式
至于本发明的详细构造、应用原理、作用与功效以及优选的实施方案，则参照下列依附图所作的说明即可得到完全的了解。
图1A到图1E说明本发明的实施方案中的一种半导体装置的电容器制备方法的截面图；
参照图1A，掺杂硅层被沉积在装备了所需的下部基层(图中未示)的半导体基板1，经由对掺杂硅层刻画图样以形成下部电极2。在该情况中，虽然下部电极2被制成为平板形式，为了要增加电容器的电容量，其可被形成圆柱构造、凹入构造、或插销构造，并且可在其表面上形成半球型硅颗粒(HSG：hemispherical silicon grain)。
参照图1B，清洁方法在基板所得构造上进行，其中基板中形成了下部电极2。薄氮化硅层被沉积在下部电极2的表面上，以改进在介电层间的界面特性。在这情况中，薄氮化硅层3可由使用N-LPCVD的氮化硅层的沉积方法、使用等离子体NH3处理的氮化方法、或使用热NH3处理的氮化方法等等而被沉积，优选地是5到30的厚度。
参照图1C，对氮化硅层3进行氧化处理，以氧化氮化硅层的表面，藉此在氮化硅层3的表面上形成氧氮化硅(SiOxNy：silicon oxynitride)层4。在进行氧化处理时，氮化硅层3的表面被稍微地氧化，而除去在层中的缺陷例如插销孔和陷址(trap sites)并且不减少氮化硅层3的整体介电比。
因此，当介电层以下述的方法被沉积在氧氮化硅层4上时，氧氮化硅层4改进了下部电极和介电层间的界面特性，特别是阻止了在氧化的氮化硅层中的空穴流(hole current)，而藉此减少在电容器中的漏泄电流并增加击穿电压，也就是，破坏电容器绝缘的电压。
再者，在氧化的氮化硅层，也就是氧氮化硅层4，由于具有比氮化硅层3更好的抗氧化性(oxidation-resistance)，在介电层沉积之后，也就是在ONO电容器中的热氧化或N2O处理之后，Ta2O5电容器中后处理的抗氧化性变得比传统例中的好，藉此阻止氧气扩散进入构成下部电极的掺杂硅层，造成防止介电特性减少。
根据本发明的上述实施方案，氮化硅层3的氧化可由下述方法进行，等离子体强化氧化作用、低压氧化作用、常压氧化作用、或在大气中的自然空气冷却，也就是一种在沉积氮化硅层之后，有意地在氧气环境中实施的冷却方法，并且其形成从氮化硅层3的表面算起，厚度在15之下的氧氮化硅层。
参照第1D图，以N/O或Ta2O5制成的薄介电层5被沉积在氧氮化硅层4之上。然后，后处理，也就是一种使用O2、N2、NO或O2的热处理，在沉积的介电层5之上被进行，以在此层中将插销孔、氧气室等等除去并结晶化，藉此改进介电层5的介电特性。
在这情况中，就使用NO层为用于介电层5的材料而言，介电层5达成具有一和在氮化硅层3上的氧氮化硅层4形成有关的NONO或ONONO结构。
参照图1E，用于上部电极的导电层，也就是掺杂硅层或铝材料层等，被沉积在介电层5之上。然后，上部电极6藉由对导电层刻画图样而被形成，生成本发明的电容器，其由以下部电极2、氧氮化硅层4、介电层5和上部电极6制成的迭层结构所构成。
同时，根据本发明的上述实施方案，形成下部电极的硅层的杂质掺杂、氮化硅层的沉积、氮化硅层表面的氧化作用、介电层的沉积和对介电层的随后热处理能以在原位(in-situ)或无延时方式更好地进行。
根据本发明的半导体装置的电容器制造方法，薄氮化硅层被沉积在构成下部电极并氧化其表面的掺杂硅层的上，而然后介电层被沉积，藉此减轻界面应力并阻止在界面中被捕获的电荷。
特别地，氧化氮化硅层在沉积介电层时充当缓冲层，藉此减轻微应力(micro-stress)并阻止氧气扩散进入掺杂硅层，其构成好的抗氧化性的下部电极，从而制备在相同漏泄电流和击穿电压的情况下，具有比传统例更高的电容的半导体装置的电容器。
图2A和图2B为本发明的电容器的电特性的说明图，其中图2A为表示施加电压和电流密度间的关系图，而且图2B为表示施加电压和电容器的电容量间的关系图。
参照图2A和图2B，本发明的具有ONO构造的电容器，其中应用被氧化的氮化硅层，表示了一种低漏泄电流和高击穿电压特性，和一种与具有一般ONO构造的传统电容器相比，具有升高的电容器电容。
表1和表2表示了具有ONO构造和Ta2O5构造的电容器，其电容量和击穿电压的测试结果，分别对应施用氧化的氮化硅层的情况和不使用氧化的氮化硅层的情况。
(表1)
  块状(produced in bulk)装置的测试值   电容量  击穿电压(V)
  一般ONO电容器   33.14fF/晶胞 改进值2.37Ff/cell   3.41V 改进值0.11V
  施用氧化的氮化硅层的ONO构造 35.51fF/晶胞 3.52V
(表2)
  平板电容器的测试值  电容量   击穿电压(V)
  进行NH3预处理的Ta2O5电容器  10.9fF/μm2 改进值1.6fF/晶胞 3.7V 改进值0.4V
  施用氧化的氮化硅层的Ta2O5电容器  12.5fF/μm2 4.1V
如图2A和图2B所示，并如表1和表2所显示，其中施用氧化的氮化硅层的本发明电容器表现了比传统电容器更好的漏泄电流和击穿电压特性，藉此能够阻止介电比的减少，并在相同漏泄电流和击穿电压的情况下，提供比传统电容器更高的电容量。
如上所述，依照本发明所制成的半导体装置电容器由于氮化硅层的沉积和其表面的氧化而改进了下部电极和介电层间的界面特性，藉此在施加偏压到电容器时，抑止了空穴电流，导致漏泄电流减少、击穿电压增加、以及可靠程度和生产效率二者的改进。
同样地，本发明在进行介电层的后处理时，可防止氧气扩散到下部电极，藉此防止介电层整体介电比的劣化，而导致电容器电容量增加。
需要注意的是，以上所述是本发明优选具体的实施方案，若依本发明的构想所作的改变，添加，替换，其产生的功能作用，仍未超出说明书，权利要求书和与图示所涵盖的精神时，均应在本发明的范图内，于此说明。

Claims (16)

1.一种半导体装置的电容器，其包含：
在半导体基板上形成由掺杂硅的材料所制成的下部电极；
在下部电极上形成的薄氮化硅层；
通过氮化硅层的氧化而在氮化硅层表面上形成的氧氮化硅层；
在氧氮化硅层上形成的介电层；以及
在介电层上形成的上部电极。
2.权利要求1中所述的半导体装置的电容器，其中下部电极的形成构造选自平板构造、圆柱构造、凹入构造、和插销构造中的任一种构造。
3.权利要求1中所述的半导体装置的电容器，其中在所形成的下部电极表面上具有半球型硅颗粒。
4.权利要求1中所述的半导体装置的电容器，其中氮化硅层形成5到30的厚度。
5.权利要求1中所述的半导体装置的电容器，其中所形成的氧氮化硅层具有从氮化硅层表面算起，低于15的厚度。
6.权利要求1中所述的电容器，其中介电层由氮化物/氧化物或Ta2O5所制成。
7.一种半导体装置的电容器制备方法，其包含下列步骤：
在半导体基板上形成以掺杂硅的材料所制成的下部电极；
在下部电极上沉积薄氮化硅层；
在氮化硅层的表面上，以氮化硅层的氧化形成氧氮化硅层；
在氧氮化硅层上沉积介电层；以及
在介电层上形成上部电极。
8.权利要求7中所述的半导体装置的电容器制备方法，其中所形成的下部电极选自平板构造、圆柱构造、凹入构造、和插销构造中的一种构造。
9.权利要求7中所述的半导体装置的电容器制备方法，其中在所形成的下部电极表面上具有半球型硅颗粒。
10.权利要求7中所述的半导体装置的电容器制备方法，其中沉积薄氮化硅层的步骤是通过选自等离子体NH3氮化方法、热NH3氮化方法、以及LPCVD方法中的任一种方法进行。
11.权利要求7中所述的半导体装置的电容器制备方法，其中氮化硅层沉积5到30的厚度。
12.权利要求7中所述的电容器制备方法，其中氮化硅层的氧化作用是选自等离子体强化氧化作用、低压氧化作用、常压氧化作用、和在氧气环境中的自然空气冷却方法中的任一种方法进行。
13.权利要求7中所述的半导体装置的电容器制备方法，其中氧化氮化硅层而形成从氮化硅层表面算起厚度低于15的氧氮化硅层。
14.权利要求7中所述的半导体装置的电容器制备方法，其中介电层由氮化物/氧化物或Ta2O5所制成。
15.权利要求7中所述的半导体装置的电容器制备方法，还包含一种实施沉积介电层的后处理的步骤，其在形成上部电极前和沉积介电层之后，使用选自O2、N2、和NO中的任一种气体进行的。
16.权利要求7中所述的电容器制备方法，其中沉积氮化硅层、氧化氮化硅层、沉积介电层、以及实施介电层的后处理步骤，以在原位或无延时的方式进行的。
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