CN1172361C - 半导体装置的电容器的制造方法 - Google Patents
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Abstract
本发明提供一种既能制成确保优良电特性和高电容量并除去了杂质的优良电介质膜,又能简化制造工序并节省了生产成本的半导体装置的电容器的制造方法。该方法由以下工序组成:在半导体晶片的下部构造物上形成下部电极;在上述下部电极的上部蒸镀非晶质TaON薄膜后,在NH3气氛中至少进行1次以上的退火工序,形成多层构造的TaON电介质膜;在上述多层构造的TaON电介质膜的上部形成上部电极。
Description
技术领域
本发明涉及半导体装置的电容器的制造方法,具体地说,本发明是涉及既能充分确保半导体装置要求的充电电容又能改善膜质的电特性的半导体装置的电容器的制造方法。
背景技术
现在,为了达到半导体装置的高度集成化,而正在积极进行有关单元面积的减少和工作电压的低电压化的研究开发。
随着高度集成化的提高,电容器的面积迅速减少,然而,虽然存储元件工作的必要充电容的单元面积减少了,但必须增加存储元件工作的必要电荷,即单位面积上可以确保的电容量。因而,最近为了确保DRAM用电容器的足够电容量,而提出了一种通过圆柱体构造改变来增加电容器面积或减少电介质膜的厚度,从而确保足够的电容量的方法。
另外,最近还正在进行把原有的作为硅氧化膜使用的电介质膜形成为NO(Nitride-Oxide)或ONO(Oxide-Nitride-Oxide)的结构,或者打算用能够确保高的电容量(介电常数:20~50)的Ta2O5或BST(BaSrTiO3)等代替的研究。
另一方面,最近,由于具有NO电介质的电容器显示出能确保256M以上的下一代存储器的必要的电容量的极限,所以对于下一代电介质例如Ta2O5电介质的研究开发也在进行中。
发明内容
然而,由于上述Ta2O5薄膜具有不稳定的化学计量(Stoichiometry),所以起因于Ta和O的组成比的差别的置换型Ta原子只存在于薄膜内。
并且,在Ta2O5电介质膜形成时,由于作为Ta2O5的前体的Ta(OC2H5)5的有机物与O2(或N2O)气体的反应,生成作为杂质碳原子和碳化合物(C、CH4、C2H4等)以及水(H2O)。
结果,因存在于Ta2O5薄膜内的氧空位和作为杂质存在的碳原子、离子和游离基而使电容器的漏电流增加和介电特性变坏。
为了除去Ta2O5薄膜内的杂质,而进行二次、三次低温热处理(例如等离子体N2O或UV-O3),但制造过程复杂,并使Ta2O5薄膜的抗氧化性能下降,所以存在发生下部电极氧化的缺点。
本发明是为解决上述已有技术的各种问题而提出的,本发明的目的是提供一种具有优良电特性并可确保高电容量的半导体装置的电容器的制造方法。
本发明的另一个目的是提供一种通过除去作为电介质膜内漏电流原因的杂质来得到优良电介质膜的半导体装置的电容器的制造方法。
本发明的还有一个目的是通过省略为了确保电容器的高电容量而增加下部电极的横断面积的制造工序来减少单位工序数和缩短工序时间,从而提供了一种能够节省生产成本的半导体装置的电容器的制造方法。
用于达到上述目的的本发明的半导体装置的电容器的制造方法,其特征是包含:在半导体晶片的下部构造物上形成下部电极的步骤;在上述下部电极的上部蒸镀非晶质TaON薄膜后,在含有氮或氧的气体气氛中至少进行1次退火工序,形成多层构造的TaON电介质膜的步骤;在上述TaON电介质膜的上部形成上部电极的步骤。
用于达到上述目的的本发明的半导体装置的电容器的制造方法,其特征是包含:在半导体晶片的下部构造物上形成下部电极的步骤;在上述下部电极的上部蒸镀非晶质TaON薄膜后,在NH3气氛中进行至少1次以上退火工序,以便形成多层构造的TaON电介质膜的步骤;在上述多层构造的TaON电介质膜的上部形成上部电极的步骤。
本发明的半导体装置的电容器的制造方法,其特征是包含:在半导体晶片的下部构造物上形成下部电极的步骤;在上述下部电极的上部蒸镀非晶质TaON薄膜后,在NH3气氛中进行2次退火工序,以便形成多层构造的TaON电介质膜的步骤;在上述TaON电介质膜的上部形成上部电极的步骤。
本发明的半导体装置的电容器的制造方法,其特征是包含:在半导体晶片的下部构造物上形成下部电极的步骤;进行氮化处理的步骤;在上述下部电极的上部蒸镀非晶质TaON薄膜后,在NH3气氛中进行2次退火工序,以便形成多层构造的TaON电介质膜的步骤;在上述TaON电介质膜的上部形成上部电极的步骤。
附图说明
图1是说明具有本发明的多层TaON薄膜的半导体装置的电容器制造方法的工序图。
图2是说明具有本发明的多层TaON薄膜的半导体装置的电容器制造方法的工序图。
图3是说明具有本发明的多层TaON薄膜的半导体装置的电容器制造方法的工序图。
图4是说明具有本发明的多层TaON薄膜的半导体装置的电容器制造方法的工序图。
图5是表示在本发明的半导体装置的电容器制造方法中,通过在蒸镀TaON薄膜后进行的退火工序,除去残留在TaON薄膜内的氧空位和碳化合物过程的图。
具体实施方式
以下根据附图详细说明本发明的半导体装置的电容器的制造方法。
图1至图4是说明本发明的半导体装置的电容器制造方法的工序断面图。
按照本发明的半导体装置的电容器的制造方法,虽然图中未示出,但首先在作为半导体晶片的硅晶片10的活性区域上部面形成具有栅极、源极/漏极等的半导体元件(未图示)等下部构造物。
然后,也可以如图1所示,在整个硅晶片10的表面蒸镀USG(UndopedSilicate Glass)、BPSG(Boro Phospho Silicate Glass)、SiON等物质,用化学机械研磨(Chemical Mechanical Polishing)工序等对其表面进行研磨,形成层间绝缘膜20。对层间绝缘膜的膜厚没有特别的限制,但通常为300~700,最好是400~500。
接着,为了与上述硅晶片10的活性区域相连接以及确保电容器的横断面积,也可以通过采用光石印技术、蚀刻技术等的曝光、显影工序等,选择地除去上述层间绝缘膜20,形成接触孔(未图示)等。
此后,在上述接触孔内蒸镀掺杂的多晶硅或非晶质掺杂的多晶硅等导电性物质,通过采用光石印技术、蚀刻技术等的曝光、显影工序等,选择地除去该导电性物质,在含有上述接触孔的层间绝缘膜20上形成下部电极30。
这时,上述下部电极和上部电极可分别单独使用掺杂的多晶硅和金属物质,或者将它们层叠使用。
对下部电极和上部电极的厚度没有特别的限制。下部电极的厚度通常为300~800,最好是300~600。上部电极的厚度通常为300~2000,最好是300~1000。
作为上述金属物质可以选择使用TiN、Ti、TaN、W、WN、WSi、Ru、RuO2、Ir、Pt等中的任一种。
作为上述下部电极30的结构可以例示出堆叠(Stack)、圆柱体(Cylinder)、翼片(fin)、堆叠圆柱体(Stack Cylinder)结构等。
为了增加上述下部电极30的单位表面积,可使上述下部电极30的表面形成为凹凸构造的HSG(Hemi Spherical Grain),即半球形凸凹构造。
然后,如图2和图3所示,在下部电极30的表面蒸镀非晶质TaON膜后,至少反复进行1次以上退火处理工序,即至少反复进行1次以上蒸镀和退火处理,形成多层构造的TaON电介质膜32。
对多层构造的TaON电介质膜的膜厚没有特别的限制,通常为300~500,最好是400~450。TaON电介质膜的各层的膜厚可以按照多层膜整体膜厚的所希望值适当设定。多层构造的TaON电介质膜的层数,即反复进行蒸镀和退火处理的次数也可以按照多层膜整体膜厚的所希望值适当设定,通常为1~4次,最好是1~2次,理想是2次。
这时,上述非晶质TaON薄膜在约600℃以下的300~600℃,最好是400~450℃的低压化学气相蒸镀室中,在气相反应(gas phase reaction)被抑制的晶片上,诱导形成表面化学反应(Surface chemical reaction)。对蒸镀室内的压力没有特别的限制,通常为0.1~10torr,最好是0.1~1torr。退火时间也没有特别的限制,通常为650~950℃,最好是750~850℃。
在蒸镀上述非晶质第1 TaON膜32a前,可以就地(in-situ)或在外面(ex-situ),通过采用HF、SiF6、NF6等任何一种蒸气的干式洗净工序、采用HF溶液的湿式洗净工序,除去上述下部电极30表面的自然氧化膜和微粒。
在进行上述洗净工序的前/后,通过用NH4OH或H2SO4溶液的化合物洗净晶片的界面等,可以除去在洗净工序的前/后产生的夹杂物,并可以提高膜的均匀性。
另外,在进行非晶质TaON薄膜的蒸镀和热处理工序时,为了防止在构成上述下部电极30的多晶硅和上述第1非晶质TaON 32a之间形成界面氧化膜,而最好根据需要在上述洗净工序中洗净上述下部电极30,然而最好是在上述TaON薄膜的蒸镀初期,在NH3气氛中就地用等离子体(in-situ plasma)等对上述下部电极30的表面进行氮化处理1~10分钟(最好是1~5分钟)。温度、压力等的氮化处理条件没有特别的限制。处理温度通常为300~600℃,最好是400~450℃。处理压力通常为100~760torr,最好是700~760torr。对由氮化处理生成的氮化膜的厚度没有特别的限制,通常为5~15A,最好是5~10A。
并且,为了防止在上述下部电极30的表面形成不均匀的自然氧化膜以及防止向下部电极的漏电流,而在蒸镀室(例如群组化(cluster)的低压导入金属化学气相蒸镀室(low-pressure induced metal-chemical vapordeposition chamber等)等)中用在压(例如0.1~10torr,最好是0.1~1.0torr)移送晶片后,就地在N2O气氛中用等离子体对下部电极的表面进行均匀的氧化处理,即可形成约10以下(最好是5~10)的氧化膜(图中未示出)。温度、时间等的氧化膜形成条件没有特别的限制。温度通常为300~600℃,最好是400~450℃。时间通常为1~10分钟,最好是1~3分钟。
如图2所示,在300~600℃(最好是350~450℃)温度1次蒸镀非晶质第1 TaON膜32a后,即可在NH3或N2O气氛中进行等离子体退火工序。对等离子体退火工序的温度、压力、时间等条件没有特别的限制。压力通常为100~760torr,最好是700~760torr。时间通常为1~10分钟,最好是1~3分钟。
接着,如图3所示,连续蒸镀非晶质的第2 TaON膜32b,即可在NH3或N2O气氛中进行等离子体退火工序。在NH3或N2O气氛中等离子体退火工序的处理条件没有特别的限制。退火温度通常为750~950℃,最好是800~850℃。等离子体退火时间通常为1~10分钟,最好是1~3分钟。压力通常为100~760torr,最好是700~760torr。
这时,至少反复进行1次以上非晶质TaON膜的蒸镀和退火工序,由于有效地氧化除去了存在于上述第1和第2非晶质TaON膜内的Ta原子和碳成分,而可得到具有所希望范围例如30~100(最好是25~40)介电常数的电容器。
另外,通过质量流量控制器(Mass Flow Controller)等,在150~200℃(最好是150~180℃)温度范围用维持在低温的蒸发器、蒸发管等,按照约300mg/min以下(最好是100~300mg/min)的速度定量供给作为Ta成分化学蒸气的99.99%以上的Ta(OC2H5)5的Ta化合物,蒸镀上述非晶质TaON薄膜。
这时,为了防止Ta蒸气的冷凝,而最好使包含节流装置或喷管的蒸发器和构成Ta蒸气通路的供给管经常保持在150~200℃温度范围。
按照这种方法,将Ta(OC2H5)5等的Ta化合物的化学蒸气与NH3反应气体(10~500sccm,最好是50~100sccm)一起分别按一定量供给低压化学气相蒸镀室内以后,它们在约100torr以下(最好是0.1~1torr)压力的低压化学气相蒸镀室内进行表面反应,即可诱导生成非晶质TaON薄膜。
例如,可以采用通过安装在低压化学气相蒸镀室上部的喷射头(shower-head)等将含有化学蒸气的反应气体垂直均匀地喷射到晶片上的方法,也可以采用通过安装在上述蒸镀室上部或侧面的喷射器(injector)等按抛物线形状或逆流(Counter flow)方式等使上述反应气体在晶片上均匀喷射的方法,即可在上述下部电极30上面蒸镀上述非晶质TaON薄膜。
在上述非晶质TaON蒸镀工序中,为了改善膜质,将根据低压化学气相蒸镀室的温度、压力以及Ta化学蒸气的注入量,在5~500sccm最好是50~100sccm范围内定量供给O2气体。例如,当O2气体的供给量为5sccm时,可使蒸镀室温度为350~450℃、压力为0.1~1.0torr、Ta蒸气的注入量为100mg/min~300mg/mim。
上述第1和第2 TaON膜32a、32b,可在NH3或N2O气氛中进行等离子体处理,也可在UV-O3气氛中进行低温退火工序。所谓UV-O3气体介质就是在O3气体介质下进行UV照射。在UV-O3气氛的低温退火工序中的温度、压力、时间等处理条件没有特别的限制。温度通常为300~600℃,最好是400~500℃。O3压力通常为100~760torr,最好是700~760torr。
上述退火工序最好采用电炉、快速热处理方式(RTP:Rapid ThermalProcess)等,在650~950℃最好是800~850℃温度下,在N2O、O2和N2等气氛中进行退火。这时的压力是100~760torr,最好是700~760torr。退火时间是1~10分钟,最好是1~3分钟。
此后,如图4所示,在上述多层构造的TaON电介质膜32上部蒸镀导电性的掺杂多晶硅,通过使其选择地形成图形,从而形成上部电极34,即可完成SIS(Silicon-Insulator-Silicon)构造的电容器的制造工序。
图5是在具有本发明的多层构造的TaON薄膜的电容器制造方法中,表示除去在蒸镀TaON薄膜后进行退火工序时残留在TaON薄膜内的氧空位和碳化合物的过程图。
如图5所示,为了使本发明的多层构造的TaON薄膜密度提高,而在蒸镀非晶质的第1 TaON膜32a以后,在NH3或N2O气氛中进行退火,除去在蒸镀非晶质TaON薄膜过程中生成的碳化合物杂质或水(H2O)和存在于薄膜内的氧空位,并诱导了膜的结晶。
而且,还抑制了在非晶质TaON薄膜内未完全氧化的残留Ta化学物质的生成。
这样,由于除去了残留在上述非晶质第1 TaON薄膜32a内的挥发性碳化合物(例如CO、CO2、CH4、C2H4等),并诱导了膜的结晶,从而可防止产生漏电流。
同样,如在上述非晶质第1TaON薄膜32a上蒸镀第2 TaON薄膜32b,再在电炉中在600~900℃(最好是700~800℃)下进行5~60分钟(最好是5~20分钟),或者在650~950℃(最好是800~850℃)下在NH3或N2O气氛中(100~760torr,最好是700~760torr)进行1~10分钟(最好是1~3分钟)的快速热处理工序(RTP),则与上述非晶质第1 TaON薄膜32a的蒸镀时一样,由于除去了残留在上述第2TaON薄膜32b内的挥发性碳化合物和水,并诱导膜质的结晶,而可防止产生漏电流。
这样,非晶质TaON薄膜32a、32b通过非晶质的结晶诱导和除去碳化合物的退火工序,可使电介质膜的膜质良好。
也就是说,上述非晶质TaON薄膜32a、32b的蒸镀和热处理工序,弥补了界面的微细裂纹(micro crack)、针孔(pin hole)等结构缺陷,可以提高膜的均匀度(homogeniety)。
如上所述,本发明的半导体装置的电容器制造方法具有以下效果。
在本发明的半导体装置的电容器制造方法中,通过至少反复进行1次以上的TaON薄膜的蒸镀和退火工序形成电介质膜,因此与已有的电介质膜比较,可以确保介电常数高而且稳定的电介质膜。
并且,本发明的TaON电介质膜可以解决下述问题:由于已有的Ta2O5电介质膜的不稳定的化学计量产生的氧空位和碳杂质引起的漏电流问题;在Ta2O5薄膜的蒸镀工序和后续热处理过程中,由于在下部电极的多晶硅Ta2O5薄膜界面的不均匀氧化反应而引起的漏电流问题。
也就是说,本发明的TaON电介质膜与已有的MIS(Metal-Insulater-silicon)结构的Ta2O5电介质膜比较,由于可将电介质膜的等效氧化膜的厚度控制在不足25,因此可得到工作在256M级以上的DRAM所必须的高容量电容器。
另外,由于本发明的电介质膜的形成是在低压金属有机化学气相蒸镀室的内就地进行TaON薄膜的蒸镀和等离子体处理,所以可以省略已有的在电介质膜蒸镀前进行的在氮气氛中的快速热处理工序和蒸镀后的低温及高温热处理工序。
由于在本发明中使用了高介电常数的电介质膜,所以就不需要为了得到高介电常数而增加下部电极表面积的其它工序,从而可以缩短单位工序和工序时间,提高制造成本和生产率。
Claims (20)
1.一种半导体装置的电容器的制造方法,其特征是包含:
在半导体晶片的下部构造物上形成下部电极的步骤;
在上述下部电极的上部蒸镀非晶质TaON薄膜后,在含有氮或氧的气体气氛中至少进行1次退火工序,形成多层构造的TaON电介质膜的步骤;
在上述TaON电介质膜的上部形成上部电极的步骤。
2.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述下部电极和上部电极分别单独使用掺杂的多晶硅和金属物质,或者将它们层叠使用。
3.如权利要求2记载的半导体装置的电容器的制造方法,其特征是:上述金属物质选择使用TiN、Ti、TaN、W、WN、WSi、Ru、RuO2、Ir以及Pt中的任何1种。
4.如权利要求2记载的半导体装置的电容器的制造方法,其特征是:在使用掺杂的多晶硅作为上述下部电极时,还包含在上述下部电极的表面生长半球形凹凸构造的多晶硅的工序。
5.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:在蒸镀上述非晶质TaON前,还包含就地或在外面通过使用HF、SiF6以及NF3中任何一种的干式洗净工序或者使用HF溶液的湿式洗净工序,除去下部电极表面的自然氧化膜和微粒的步骤。
6.如权利要求5记载的半导体装置的电容器的制造方法,其特征是:在进行上述洗净工序的前/后,使用NH4OH或H2SO4溶液的化合物洗净界面。
7.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述非晶质TaON膜的蒸镀在600℃以下的低压化学气相蒸镀室中完成。
8.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述非晶质TaON膜的蒸镀由为了得到Ta成分的化学蒸气而维持在150~200℃温度的蒸发器蒸发Ta(OC2H5)5以后,使该Ta成分的化学蒸气通过150℃以上的供给管注入到低压化学气相蒸镀室(LP-CVD)内进行。
9.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述非晶质TaON膜,在通过流量调节器将Ta化学蒸气和作为反应气体的NH3气体供给300~600℃的低压化学气相蒸镀室内以后,在100torr以下气氛中通过诱导表面化学反应进行蒸镀。
10.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:在上述非晶质TaON膜的蒸镀工序时,为了改善膜质,而根据低压化学气相蒸镀室的温度、压力和Ta化学蒸气注入量,在5~500sccm范围定量供给O2气体。
11.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述非晶质TaON膜,通过安装在低压化学气相蒸镀室上部的喷射头,将含有Ta化学蒸气的反应气体垂直均匀喷射到晶片上进行蒸镀。
12.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述非晶质TaON膜,通过安装在低压化学气相蒸镀室上部或侧面的喷射器,将含有Ta化学蒸气的反应气体按抛物线状均匀喷射到晶片上进行蒸镀。
13.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述非晶质TaON膜,通过安装在低压化学气相蒸镀室上部的喷射器,将含有Ta化学蒸气的反应气体按逆流方式均匀喷射到晶片上进行蒸镀。
14.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述退火工序由在NH3或N2O气氛中的等离子体处理来完成。
15.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述退火工序由在UV-O3气氛中的低温退火工序来完成。
16.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:上述退火工序,使用电炉或快速热处理方式,在650~950℃温度下,在N2O、O2和N2的任一种气氛中进行。
17.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:在上述非晶质TaON膜蒸镀前,还包含在NH3气氛中用原位等离子体对下部电极的表面进行1~5分钟氮化处理的步骤。
18.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:在上述非晶质TaON膜蒸镀前,还包含在低压下将晶片移送到蒸镀室中以后,在原位N2O气氛中用等离子体对下部电极的表面进行均匀氧化处理的步骤。
19.如权利要求1记载的半导体装置的电容器的制造方法,其特征是:
在上述下部电极的上部蒸镀非晶质TaON薄膜以后,在含有氮或氧的气体气氛中至少进行1次退火工序,形成多层构造的TaON电介质膜的步骤,在上述下部电极的上部蒸镀非晶质TaON薄膜以后,在NH3气氛中实施2次退火工序,形成多层构造的TaON电介质膜的步骤。
20.如权利要求19记载的半导体装置的电容器的制造方法,其特征是:
在半导体晶片的下部构造物上形成下部电极的步骤之后,还有,对上述下部电极进行氮化处理形成氮化膜的步骤。
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1999
- 1999-12-31 KR KR10-1999-0068094A patent/KR100367404B1/ko not_active IP Right Cessation
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2000
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- 2000-12-27 TW TW089127925A patent/TW543139B/zh not_active IP Right Cessation
- 2000-12-27 JP JP2000397923A patent/JP4196148B2/ja not_active Expired - Fee Related
- 2000-12-28 GB GB0031743A patent/GB2365213B/en not_active Expired - Fee Related
- 2000-12-31 CN CNB001376470A patent/CN1172361C/zh not_active Expired - Fee Related
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2001
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GB0031743D0 (en) | 2001-02-07 |
JP2001210799A (ja) | 2001-08-03 |
KR100367404B1 (ko) | 2003-01-10 |
JP4196148B2 (ja) | 2008-12-17 |
CN1306304A (zh) | 2001-08-01 |
TW543139B (en) | 2003-07-21 |
DE10065224B4 (de) | 2009-04-02 |
US20020019110A1 (en) | 2002-02-14 |
US6770525B2 (en) | 2004-08-03 |
DE10065224A1 (de) | 2001-07-26 |
GB2365213B (en) | 2004-04-07 |
GB2365213A (en) | 2002-02-13 |
KR20010066385A (ko) | 2001-07-11 |
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