TWI226691B - Selective C4 connection in IC packaging - Google Patents
Selective C4 connection in IC packaging Download PDFInfo
- Publication number
- TWI226691B TWI226691B TW092120017A TW92120017A TWI226691B TW I226691 B TWI226691 B TW I226691B TW 092120017 A TW092120017 A TW 092120017A TW 92120017 A TW92120017 A TW 92120017A TW I226691 B TWI226691 B TW I226691B
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- Taiwan
- Prior art keywords
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- substrate
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- Prior art date
Links
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000003491 array Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 239000010977 jade Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 41
- 239000002184 metal Substances 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 31
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0256—Electrical insulation details, e.g. around high voltage areas
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
- Control And Other Processes For Unpacking Of Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
1226691 玖、發明說明: 【發明所屬之技術領域】 本發明係有關於封裝積體電路,更明確地說,有關於 被稱為”覆晶接合”或C 4之連接技術。 【先前技術】 於製造用以連接積體電路(IC)組之基材的製程中,製 造者有時在積體電路的底部上,完成與銲錫凸塊連接點之 選擇接觸。例如,λ中可能有—組類似產品,其具有與標 準晶片不同之連接點,使得在晶片上之第k個凸塊在部份 封裝中被使用,而在其他封裝中則不被使用。 刀 於過去,如第3圖之剖面圖所示,一具有銲錫凸塊接 觸30之錫球陣列的晶片1〇(稱為,,覆晶接合,,技術或以技 術)將全部被銲接至在基材頂表面135上之對應接觸陣列 中之金屬接觸* 11 〇。於此時,該晶片將必須只針對所用 之接觸加以设計及製造。美國專利第6,229,21 9號案例示 具有不規則組之接觸在底部之不同晶#。所有在每一晶片 上^接觸係被黏結至在封I上之對應接觸。該封裝藉由令 在阳片上有空位’即晶片上之第k槽有一空位,而容許兩 不同曰日片’因此’在第k位置之接觸與在該晶片上之空位 槽間並未形成黏結。 或者’一晶片將被黏結至在封裝上之一接觸,但未被 使用之接觸將為”浮置”,即未連接至封裝的其他層。這表 丁、接觸t* 110有電位,以短路至其他接觸。另外,在基 3 1226691 材上之金屬代表可能影響晶片操作的電容值。對於形成 片接觸之不同掩模,去除在晶片底部上之接觸將很浪費 本。在晶片成形後去除接觸將需要額外之處理,並可能 損及該晶片。去除在該位置之接觸墊1 1 0為一可能,但 可能使銲錫凸塊 3 0流動以短路鄰近接觸,或已經製造 接觸墊11 0下之導孔,甚至以銲錫掩模1 3 0之出現,一 統介電層被沉積並以微影方式作出圖案。於此先前技藝 之銲錫掩模係如傳統被顯示為分離銲錫凸塊3 0及與銲 凸塊接觸之對應金屬墊1 1 0。 【發明内容】 本發明關係於一種絕緣開在 1C之底部上之未使用 錫凸塊的結構,藉由配合上銲錫掩模,對基材之頂面上 金屬内連線作出圖案,以隔離開未使用之銲錫凸塊。 本發明之一特性為改變在未使用晶片接觸下通過之 屬内連線之形狀,以在介電銲錫掩模中形成一下凹,以 低在選定位置之銲錫掩模之高度。 本發明之另一特性為將銲錫掩模作出圖案,以將一 電層放置於晶片上之一接觸與在封裝上之對應接觸之間 【實施方式】 再次參考第3圖,其中顯示一 1C封裝基材一部份 剖面圖,其中,晶片1 〇係經由一組C4銲錫凸塊3 0連 至該封裝,凸塊黏結至一陣列之連接墊1 1 〇。連接墊被 晶 成 會 有 於 傳 中 錫 銲 之 金 降 介 之 接 連 4 1226691 接至内連線,其向下延伸穿過基材的頂面1 3 5並連接該所 不1C至其他1C及/或外面世界。銲錫掩模130為一介電 層’其係在頂面上之導體被作出圖案後並在晶片被黏結之 月·J被放下。其藉由包圍接觸墊1 1 〇而隔離開銲錫凸塊3 0。 鲜錫掩模130在金屬層110被作出圖案後被放下,然 後藉由曝露至適當特徵之光而作出圖案,然後,在作出 圖案後顯影。可以由第3圖看出,將銲錫掩模作出圖案的 方式為在銲錫凸塊間之分割及隔離特性,在每一接觸塾 旁形成一壁。於第3圖之剖面圖中,這些銲錫球均未 為金屬110所短路。如果,有金屬110延伸於接觸間之情 形’層30將於其通過金屬11〇層上之處略高。 先前技藝之特性為IC腳位排列之修改(或至銲錫凸塊 之連接)很昂貴,成本因素之考量指示仍保有銲錫接觸ιι〇 連接。因此,接著表示附著至晶# 10之錫球係被銲接至 在該表面上之接觸110,因此,表示藉由在基材上之連接 作用’而具有電容加至晶片上的問題。熟習於本技藝者得 知-接㈣U0典型被連接至—向下延伸穿過基材的導 孔,使得有相當量之區域係與錫球30作電氣接觸。 依據本發明,在不改變IC的配置下,可容許在基材 上之不同連接,藉由一不會干擾晶片操作之圖案化介電 質,以隔離開在晶片上之未使用銲錫凸塊。 被使用。於 現參考第1圖,其中顯示依據本發明之封裝基材區域 的平面圖’其中’有一 3x7 p車列之接觸墊"0,以配人一 特定1C之標準1/0。然而,並非所有接觸均 ° 1226691 此例子中,中間列之兩接觸未使用。 一由左至右沿著陣列中間列通過的粗線i 2〇代表一導 電内連線’其係依據予以實施之系統需要(連接接觸1、3、 4、6及7)。於此例子中,該線通過七個鄰接之接觸位置。 於此例子中,兩個為編號1 2 2所表示之接觸位置未使用, 並且位在具有六角形之線120區域中。所示佈局之功能為 導電内連線件120偏移開晶片1〇上之銲錫凸塊之位置; 即,其分開,在兩側間界定一六角形開口。在晶圓黏結操 作前被放下之銲錫掩模填入該六角開口並在銲錫掩模i 2 5 之頂表面的該位置中形成一下凹。該下凹包圍在晶片1〇 上之錫球並將之與周圍之連接器隔離,使得當加熱及銲錫 迴流程序時’任何轉為炼化態導電材料被侷限。於黏結操 作中’在晶片1 0底部上之錫球3 0將會改變形狀,略微降 低晶片1 0。於錫球3 0與接觸墊丨丨〇間之介電材料丨2 $防 土電氣路徑之形成。因此’在IC10之下面之連接未被干 擾,但未使用連接並未影響基材連接(例如藉由不想要之 短路)或者晶片之操作(藉由改變電容值)。 參考第2圖之側視圖,通過内連線12〇所取之面A_a , 因此,並未顯示其剖面,即當該線通過墊丨丨〇時被標示為 110’及當通過六角形122時,被標示為122。因此,於 第2圖中’兩區域135均顯示在每一側上之凸塊,其中, 銲錫掩模在内連線1 2 2上。 在第1圖之最上一列,盒子124界定在一接觸位置旁 之區域,其將密封一由銲錫掩模材料所形成之介電質墊 1226691 1 2 5者。此墊防止一路徑形成於在該位置之接觸1 1 0及在 該位置上之晶片接觸之間。此配置係有用於當在晶片上有 一接觸,其在此特定系統中並未使用,及在該基材中之接 觸並未連接或可能短路至在該基材上或之中之另一内連 線。 因此,本發明可以使用較大等級之晶片及/或基材, 因為一具有一接觸110連接至基材中之其他接線之堆疊基 材仍可以被使用,及該基材將增加於晶片中之電路上之電 容性負載(若有接觸的話)。同樣地,一短路於一系統版本 中之晶片接觸Κ及L之基材中之内連線可能封閉,使得 不具該短路之系統仍可以使用相同基材。 熟習於本技藝者可知並不需要一閉合六角形及單側結 構將用以保留線1 2 0之連續性。線1 2 0並不必要為一直線, 其可以具有一直角或其他形狀。一鑽石形、矩形、平行四 邊形或其他形狀(較佳一閉合曲線)可以使用以替代六角 形。 較佳地,銲錫掩模之厚度係足夠地厚,以防止電氣接 觸,同時,也足夠薄,以使其他銲錫凸塊不會不與所黏結 之墊11 0作接觸。因為銲錫凸塊將於黏結製程中迴流,所 以,其也可允許部份公差本發明已經針對由IBM所開發 之覆晶接合製程加以說明,但也可以使用其他技術,其中 1C底部之一組接觸係被黏結至基材頂部上之一陣列者。 雖然,本發明已經以單一實施例方式加以說明,但熟 習於本技藝可以了解到本發明也可以在不脫離以下申請專 7 1226691 利範圍之精神及範圍下加以以各種版本實施。 1 【圖式簡單說明】 第1圖為依據本發明之結構的俯視圖。 w 第2圖為第1圖之剖面圖。 % 第3圖為對應於第2圖之先前技藝之剖面圖。 · 【元件代表符號簡單說明】 φ 10 晶片 30 銲錫凸塊 110 接觸墊 120 粗線 122 接觸位置 124 盒子 125 銲錫掩模層 130 銲錫掩模 135 頂面
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Claims (1)
1226691 第f十〇。7號專f喋θ年I。月修正 拾、申請專利範圍: 其至少包含:一; κ一種用以連接積體電路的基材 面,具有至少一標準圖案陣列之接觸形成於其上,以及, 一圖案介電層,安排於該頂面上,該有圖案介電層被作 出圖案,以包圍並彼此隔離開一次組標準圖案陣列之接 觸其中,一導電接觸内連線件係安排在該頂面上並電 氣連接至少部份之該陣列接觸,該接觸内連線件係由該 至少一陣列中之接觸位置的至少一選定位置位移,及該 有圖案介電層覆蓋該至少一選擇位置,其中在頂面之選 定位置之積體電路接觸係與位在選定位置之接觸陣列之 接觸隔離開。 2. 如申請專利範圍第1項所述之基材,其中上述之接觸内 連線件係由包圍該至少一選定位置之閉合曲線中之至少 選疋位置位移開,其中,該介電層在該閉合曲線内之 該至少一選定位置處有一下凹。 3. 如申請專利範圍第1項所述之基材,其中安排在頂面及 電氣連接至一次組接觸之該導電内連線件延伸通過至少 一其所未連接之未連接接觸。 4·如申請專利範圍第3項所述之基材,其中上述之導電内 連線件形成一閉合曲線,包圍住該至少一未連接接觸。 1226691 5·如申請專利範圍第4項所述之基材,其中上述之導電内 連線件形成一六角形,包圍住該至少一未連接接觸。 6·如申請專利範圍第4項所述之基材,其中上述之導電内 連線件形成一四邊形,包圍住該至少一未連接接觸。 / 7· —種用以連接積體電路的基材,其具有一基材頂面,具 有至少一標準圖案陣列之接觸形成於其上及一圖案化介 電層安排於該頂面上,該圖案化介電層係作出圖案以包 圍並隔離開一次組之標準圖案陣列之接觸,其中該圖案 化之介電層覆蓋該至少一選定位置,其中一在該頂面之 選定位置的積體電路接觸係與位在該選定位置之陣列接 觸之一接觸隔絕。 8·如申請專利範圍第7項所述之基材,其中上述之圖案化 介電質係為一形成一閉合曲線之導電内連線件所閉合, 該曲線包圍該至少一未連接接觸。 9·如申請專利範圍第8項所述之基材,其中上述之導電内 連線件形成一六角形,包圍住該至少一未連接接觸。 1〇·如申請專利範圍第9項所述之基材,其中上述之導電内 連線件形成一四邊形,包圍住該至少一未連接接觸。 10 1226691 11. 一種製造一基材的方法,該基材用以連接具有一基材頂 面之積體電路,具有至少一標準圖案陣列之接觸形成於 其上及一圖案介電層安排於該頂面上,該方法至少包含 步驟: 提供一組内連線給一基材,該内連線連接至少部份之 標準圖案陣列之接觸,形成一導電接觸内連線件安排於 該頂面上並電氣連接該至少陣列接觸之部份,該接觸内 連線件係由在該至少一陣列中之接觸位置的至少一選定 位置位移開; 對一介電層作出圖案,以包圍並與該標準圖案陣列之 接觸的一次組分隔,並覆蓋該玉少一選定位置,其中在 一 1C之底面上之一積體電路接觸在該頂面之選定位置 處係與位在該選定位置之陣列接觸之接觸隔離。 1 2.如申請專利範圍第1 1項所述之方法,其中上述之接觸 内連線件係位移開在一包圍住該至少一選定位置之閉合 曲線中的該至少.一選定位置。 1 3 ·如申請專利範圍第11項所述之方法,其中上述之介電 層在該至少一選定位置之閉合曲線内具有一下凹。 11
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US10/262,753 US6650016B1 (en) | 2002-10-01 | 2002-10-01 | Selective C4 connection in IC packaging |
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EP (1) | EP1547142B1 (zh) |
JP (1) | JP4536515B2 (zh) |
KR (1) | KR100633495B1 (zh) |
CN (1) | CN1326222C (zh) |
AT (1) | ATE481734T1 (zh) |
AU (1) | AU2003263368A1 (zh) |
DE (1) | DE60334230D1 (zh) |
TW (1) | TWI226691B (zh) |
WO (1) | WO2004032222A1 (zh) |
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US20090294971A1 (en) * | 2008-06-02 | 2009-12-03 | International Business Machines Corporation | Electroless nickel leveling of lga pad sites for high performance organic lga |
KR101485105B1 (ko) * | 2008-07-15 | 2015-01-23 | 삼성전자주식회사 | 반도체 패키지 |
US9059106B2 (en) | 2012-10-31 | 2015-06-16 | International Business Machines Corporation | Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip |
US9773724B2 (en) * | 2013-01-29 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and semiconductor device packages |
JP6032070B2 (ja) * | 2013-03-13 | 2016-11-24 | ソニー株式会社 | 半導体装置、半導体装置の製造方法 |
KR102207273B1 (ko) * | 2014-01-29 | 2021-01-25 | 삼성전기주식회사 | 패키지 기판 |
KR102214512B1 (ko) * | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
US10244632B2 (en) * | 2017-03-02 | 2019-03-26 | Intel Corporation | Solder resist layer structures for terminating de-featured components and methods of making the same |
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2002
- 2002-10-01 US US10/262,753 patent/US6650016B1/en not_active Expired - Lifetime
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2003
- 2003-07-22 TW TW092120017A patent/TWI226691B/zh not_active IP Right Cessation
- 2003-09-15 EP EP03798966A patent/EP1547142B1/en not_active Expired - Lifetime
- 2003-09-15 KR KR1020057003753A patent/KR100633495B1/ko not_active IP Right Cessation
- 2003-09-15 AT AT03798966T patent/ATE481734T1/de not_active IP Right Cessation
- 2003-09-15 DE DE60334230T patent/DE60334230D1/de not_active Expired - Lifetime
- 2003-09-15 AU AU2003263368A patent/AU2003263368A1/en not_active Abandoned
- 2003-09-15 JP JP2004540920A patent/JP4536515B2/ja not_active Expired - Fee Related
- 2003-09-15 CN CNB038165783A patent/CN1326222C/zh not_active Expired - Fee Related
- 2003-09-15 WO PCT/GB2003/003995 patent/WO2004032222A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
KR20050037599A (ko) | 2005-04-22 |
TW200406050A (en) | 2004-04-16 |
DE60334230D1 (de) | 2010-10-28 |
EP1547142B1 (en) | 2010-09-15 |
CN1326222C (zh) | 2007-07-11 |
AU2003263368A1 (en) | 2004-04-23 |
KR100633495B1 (ko) | 2006-10-16 |
JP4536515B2 (ja) | 2010-09-01 |
CN1669134A (zh) | 2005-09-14 |
ATE481734T1 (de) | 2010-10-15 |
US6650016B1 (en) | 2003-11-18 |
EP1547142A1 (en) | 2005-06-29 |
WO2004032222A1 (en) | 2004-04-15 |
JP2006501661A (ja) | 2006-01-12 |
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