CN1669134A - Ic封装中的选择性连接 - Google Patents

Ic封装中的选择性连接 Download PDF

Info

Publication number
CN1669134A
CN1669134A CNA038165783A CN03816578A CN1669134A CN 1669134 A CN1669134 A CN 1669134A CN A038165783 A CNA038165783 A CN A038165783A CN 03816578 A CN03816578 A CN 03816578A CN 1669134 A CN1669134 A CN 1669134A
Authority
CN
China
Prior art keywords
contact
substrate
chip
select location
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA038165783A
Other languages
English (en)
Other versions
CN1326222C (zh
Inventor
S·W·麦夸里
I·梅米斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ultratech Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1669134A publication Critical patent/CN1669134A/zh
Application granted granted Critical
Publication of CN1326222C publication Critical patent/CN1326222C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0256—Electrical insulation details, e.g. around high voltage areas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

在采用焊料凸起技术的集成电路封装中，在接合焊盘阵列下设置在衬底表面上的金属布线在选定位置处分裂，并偏离它的轴，以保持电连续，并降低所述位置处绝缘焊料掩膜层的高度。

Description

IC封装中的选择性连接
技术领域
本发明涉及集成电路封装，尤其涉及称为“倒装芯片”或C4的连接技术。
背景技术
在制造用于连接几组集成电路的衬底的过程中，(ICs)制造商有时需要形成与集成电路底部上的焊料凸起连接的选择性接触。例如，对于一组具有与标准芯片的不同连接的相似产品，芯片上的第k个凸起用于一些封装而不用于其它封装。
过去，如图3的截面图所示，具有焊料凸起(或球)接触30(称为“倒装芯片”技术或C4技术)的球栅阵列的芯片10将被全部焊接到衬底的顶部表面135上的对应接触阵列中的金属接触焊盘110上。在这种情况下，则必须将芯片设计和制造为只具有使用的那些接触。美国专利6,229,219说明了在底部具有不规则接触组的不同芯片。每个芯片上的所有接触接合到封装上的对应接触上。通过在芯片上提供空位置，即芯片在芯片上的第k个槽(slot)中具有空位置从而在第k个位置处的接触和芯片上的空槽之间没有形成接合，从而封装可以适合两个不同的芯片。
可选地，芯片被接合到封装上的接触上，但是没有使用的接触将浮置，即不连接封装的其它层。这意味着这些接触焊盘110具有短路(short out)到其它接触的可能。此外，衬底上的金属上出现电容量，可能会影响芯片工作。
在形成芯片接触时，除去芯片底部上的接触将增加成本，因为需要不同的掩膜。在形成芯片之后除去接触将需要附加的操作，可能损坏芯片。除去所述位置处的接触焊盘110是可能的，但是即使在具有焊料掩膜130的情况下，焊料凸起30可能流动而短路相邻的接触或在接触焊盘110下制造的过孔，所述焊料掩模130是通过沉积和光刻构图形成的常规介质层。在该现有技术中所示的焊料掩膜用来分离焊料凸起30和与焊料凸起如常规地接触的对应金属接触焊盘110。
发明内容
本发明提供了如权利要求1所述的衬底。在从属权利要求中给出了优选特征。
优选地，本发明通过构图衬底顶部表面上的金属互连，隔离IC底部上的未使用的焊料凸起，并使用焊料掩膜来隔离未使用的焊料凸起。
本发明的优选特征是改变穿过未使用芯片接触的金属互连的形状，以在介质焊料掩膜中形成凹槽(depression)，从而降低在选定位置处焊料掩膜的高度。
本发明的另一个优选特征是构图焊料掩膜，以在芯片上的接触和封装上的对应接触之间设置一层介质。
附图说明
图1示出了根据本发明的结构的俯视图；
图2示出了通过图1的截面图；以及
图3示出了现有技术的与图2对应的截面图。
具体实施方式
再次参考图3，示出了部分IC封装衬底的截面图，其中通过与金属接触焊盘110的阵列接合的一组C4焊料凸起或球30，将芯片10连接到封装上。接触焊盘被连接到向下延伸穿过衬底的顶部表面135、并将芯片10连接到其它芯片和/或外部的互连上。焊料掩膜130是介质层，其在构图顶部表面上的导体之后并在接合芯片之前设置。通过围绕接触焊盘110，焊料掩膜将焊料凸起30隔离。
在构图接触焊盘110的金属层之后设置光敏液体或膜的焊料掩膜130，然后通过暴露于合适特性的光构图焊料掩膜130，并在构图之后显影。如图3所示，构图焊料掩膜的标准方法形成在焊料凸起之间的分离或隔离特征，围绕每个接触焊盘110形成墙壁。在图3的截面图中，没有一个焊料球被金属110短路在一起。如果有短路，即如果金属110在接触之间延伸，层30将在跨过(pass over)金属层110的地方略微高一些。
现有技术的特征是IC引出线(或与焊料凸起的连接)的改造成本很高，因而成本考虑要求保留焊料凸起接触110连接。反过来这意味着连接到芯片10的焊料球被焊接到表面上的接触焊盘110，并因此存在由衬底上连接的影响引起附加到芯片上的电容量的问题。本领域的技术人员应该知道接触焊盘110通常这样连接到向下延伸穿过衬底的过孔，使其很大的区域与焊料球30电接触。
根据本发明，没有改变IC的布置，但是通过不影响芯片工作的构图的介质隔离芯片上未使用的焊料凸起，来适应与衬底的不同连接。
现在参考图1，示出了根据本发明的封装衬底区域的平面图，其中接触焊盘110的3x7阵列符合特定IC的标准I/O。然而，没有使用所有的接触。在该实例中，没有使用中间行中的两个接触。
沿阵列的中间行从左到右穿过的粗线120表示根据将要实现的系统需要的导电互连(连接接触1、3、4、6和7)。在该实例中，所述线穿过七个连续的接触位置。然而，在该实例中没有使用的两个接触位置都用标号122表示，并位于线120的六边形的区域中。所示布局的作用是将导电互连部分120偏离芯片10上焊料凸起的位置；即，所述导电互连部分120分裂，限定了在两侧之间的六边形开口。利用将在芯片接合操作之前设置的焊料掩膜填充六边形开口，并在所述位置处在焊料掩膜层125的顶部表面中形成凹槽。所述凹槽包围芯片10上的焊料球并将焊料球与周围的连接器隔离，从而限制了在加热和焊料回流工艺期间转变成熔融态的任何导电材料。在接合操作中，芯片10底部上的焊料球30将改变形状，使芯片10略微降低。位于球30和接触焊盘110之间的介质材料125阻止了电路径的形成。这样，IC 10底部上的连接没有变化，但是未使用的连接不会影响衬底连接(例如通过引起不需要的短路)或芯片工作(通过改变电容量)。
参考图2的侧视图，沿互连120截取截面2-2，所以在截面图中未示出互连120，即所述线在通过焊盘110的地方表示为120，在通过六边形122的地方表示为122。六边形122的两条细线在横截面的平面中。这样，在图2中，两个区域125示出了每侧上的凸起，其中焊料掩膜跨过互连122。
在图1的最上一行，盒子124限定了包围将装入介质垫125的接触位置的区域，介质垫125由焊料掩膜材料形成。该垫防止在所述位置的接触110和所述位置上的芯片接触之间形成路径。这种布置对于这样的情况有用，其中芯片上具有在该特定系统中没有使用的接触，而在衬底中具有恰好连接或可能短路到另一个互连上或衬底中的接触。
这样，利用本发明可以使用更多种的芯片和/或衬底，因为还可以使用具有连接到衬底中的其它布线的接触110的原有(stock)衬底，它将增加芯片中的电路上负载的电容量(如果形成接触)。同样地，可以断开衬底中的在一种系统中短路芯片接触K和L的互连，从而没有所述短路的系统也可以使用相同的衬底。
本领域的技术人员应该知道，具有封闭的六边形不是必需的，也可以使用单侧结构来保持线120的连续性。线120不必是直线，其可以是直角或其它形状。可以使用菱形、矩形、平行四边形或其它形状(优选封闭的曲线)代替六边形。
优选，焊料掩膜的厚度足够厚以防止电接触，并足够薄以不妨碍其它焊料凸起与接合其的焊盘110的接触。允许留一些余地，因为焊料凸起将在接合工艺期间流动。已经在IBM开发的倒装芯片工艺情境下说明了本发明，但是也可以使用将IC底部上的一组接触接合到衬底顶部上的阵列上的其它技术。

Claims (5)

1.一种用于连接集成电路(10)的衬底，该衬底具有衬底顶部表面(135)，在所述顶部表面上形成接触(110)的标准图形阵列，并在所述顶部表面(135)上设置构图的介质层(130)，所述构图的介质层(130)被构图以包围部分所述接触阵列并使它们彼此隔离，其中导电接触互连部分(120)设置在所述顶部表面上并电连接至少一些所述接触阵列，所述接触互连部分(120)偏离在所述阵列中的接触位置的选定位置，以及所述构图的介质层覆盖所述选定位置，其中在所述顶部表面上的所述选定位置处的集成电路接触与所述接触阵列的位于所述选定位置处的接触隔离。
2.根据权利要求1的衬底，其中所述接触互连部分(120)偏离在围绕所述选定位置的封闭曲线(122)中的所述选定位置，其中所述介质层在所述选定位置的所述封闭曲线中具有凹槽。
3.根据权利要求1的衬底，其中所述导电互连部分(120)延伸经过至少一个未连接的接触而不与其连接。
4.根据权利要求3的衬底，其中所述导电互连部分形成包围所述至少一个未连接的接触的封闭曲线。
5.根据权利要求4的衬底，其中所述导电互连部分形成包围所述至少一个未连接的接触的六边形。
CNB038165783A 2002-10-01 2003-09-15 Ic封装中的选择性连接 Expired - Fee Related CN1326222C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/262,753 2002-10-01
US10/262,753 US6650016B1 (en) 2002-10-01 2002-10-01 Selective C4 connection in IC packaging

Publications (2)

Publication Number Publication Date
CN1669134A true CN1669134A (zh) 2005-09-14
CN1326222C CN1326222C (zh) 2007-07-11

Family

ID=29420145

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038165783A Expired - Fee Related CN1326222C (zh) 2002-10-01 2003-09-15 Ic封装中的选择性连接

Country Status (10)

Country Link
US (1) US6650016B1 (zh)
EP (1) EP1547142B1 (zh)
JP (1) JP4536515B2 (zh)
KR (1) KR100633495B1 (zh)
CN (1) CN1326222C (zh)
AT (1) ATE481734T1 (zh)
AU (1) AU2003263368A1 (zh)
DE (1) DE60334230D1 (zh)
TW (1) TWI226691B (zh)
WO (1) WO2004032222A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
FR2918212B1 (fr) * 2007-06-27 2009-09-25 Fr De Detecteurs Infrarouges S Procede pour la realisation d'une matrice de rayonnements electromagnetiques et procede pour remplacer un module elementaire d'une telle matrice de detection.
US20090294971A1 (en) * 2008-06-02 2009-12-03 International Business Machines Corporation Electroless nickel leveling of lga pad sites for high performance organic lga
KR101485105B1 (ko) * 2008-07-15 2015-01-23 삼성전자주식회사 반도체 패키지
US9059106B2 (en) 2012-10-31 2015-06-16 International Business Machines Corporation Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip
US9773724B2 (en) * 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
JP6032070B2 (ja) * 2013-03-13 2016-11-24 ソニー株式会社 半導体装置、半導体装置の製造方法
KR102207273B1 (ko) * 2014-01-29 2021-01-25 삼성전기주식회사 패키지 기판
KR102214512B1 (ko) * 2014-07-04 2021-02-09 삼성전자 주식회사 인쇄회로기판 및 이를 이용한 반도체 패키지
US10244632B2 (en) 2017-03-02 2019-03-26 Intel Corporation Solder resist layer structures for terminating de-featured components and methods of making the same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4582722A (en) * 1984-10-30 1986-04-15 International Business Machines Corporation Diffusion isolation layer for maskless cladding process
JPS62194652A (ja) 1986-02-21 1987-08-27 Hitachi Ltd 半導体装置
US4663186A (en) * 1986-04-24 1987-05-05 International Business Machines Corporation Screenable paste for use as a barrier layer on a substrate during maskless cladding
JPS6473696A (en) * 1987-09-14 1989-03-17 Canon Kk Printed-circuit board
JP2810666B2 (ja) * 1988-01-21 1998-10-15 沖電気工業株式会社 フリップチップ型半導体装置及びその製造方法
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
JPH07273243A (ja) * 1994-03-30 1995-10-20 Toshiba Corp 半導体パッケージ
KR100194130B1 (ko) * 1994-03-30 1999-06-15 니시무로 타이죠 반도체 패키지
JPH07302858A (ja) * 1994-04-28 1995-11-14 Toshiba Corp 半導体パッケージ
CN1123067C (zh) * 1995-05-22 2003-10-01 日立化成工业株式会社 具有与布线基板电连接的半导体芯片的半导体器件
KR0157906B1 (ko) * 1995-10-19 1998-12-01 문정환 더미볼을 이용한 비지에이 패키지 및 그 보수방법
US5872393A (en) * 1995-10-30 1999-02-16 Matsushita Electric Industrial Co., Ltd. RF semiconductor device and a method for manufacturing the same
JPH11177225A (ja) * 1997-12-15 1999-07-02 Toshiba Corp プリント基板
KR100265563B1 (ko) * 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6242815B1 (en) * 1999-12-07 2001-06-05 Advanced Semiconductor Engineering, Inc. Flexible substrate based ball grid array (BGA) package
US6229219B1 (en) 2000-03-29 2001-05-08 Advanced Micro Devices, Inc. Flip chip package compatible with multiple die footprints and method of assembling the same

Also Published As

Publication number Publication date
AU2003263368A1 (en) 2004-04-23
US6650016B1 (en) 2003-11-18
TWI226691B (en) 2005-01-11
JP2006501661A (ja) 2006-01-12
KR100633495B1 (ko) 2006-10-16
EP1547142B1 (en) 2010-09-15
EP1547142A1 (en) 2005-06-29
TW200406050A (en) 2004-04-16
JP4536515B2 (ja) 2010-09-01
DE60334230D1 (de) 2010-10-28
KR20050037599A (ko) 2005-04-22
WO2004032222A1 (en) 2004-04-15
CN1326222C (zh) 2007-07-11
ATE481734T1 (de) 2010-10-15

Similar Documents

Publication Publication Date Title
US7960842B2 (en) Structure of high performance combo chip and processing method
US5414637A (en) Intra-module spare routing for high density electronic packages
US6825541B2 (en) Bump pad design for flip chip bumping
CN1185892A (zh) 中心密集的周边球栅阵列电路封装
CN1326222C (zh) Ic封装中的选择性连接
US7243423B2 (en) Chip package with degassing holes
US5362984A (en) Semiconductor device with jumping wire
KR20220084677A (ko) 반도체 패키지
CN1433574A (zh) 集成电路封装
US6486528B1 (en) Silicon segment programming apparatus and three terminal fuse configuration
US7524754B2 (en) Interconnect shunt used for current distribution and reliability redundancy
CN1610970A (zh) 用于支持球栅阵列的衬底中通路的排布
US11495574B2 (en) Semiconductor package
KR100725517B1 (ko) 본딩 패드와 볼 랜드가 복수 층에 형성된 다층 배선 기판및 이를 이용한 반도체 패키지 구조
KR20090044496A (ko) 스택 패키지
CN2672857Y (zh) 倒装芯片封装基板
JP2002270723A (ja) 半導体装置、半導体チップおよび実装基板
US11990441B2 (en) Semiconductor package
KR20240057102A (ko) 집적 회로 디바이스 및 이를 포함하는 반도체 패키지
KR20210158011A (ko) 패키지 기판 및 이를 포함하는 반도체 패키지
US8278769B2 (en) Compound semiconductor device and connectors
CN2681525Y (zh) 线路载板

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20170309

Address after: American California

Patentee after: Ultratech Corporation

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070711

Termination date: 20170915

CF01 Termination of patent right due to non-payment of annual fee