TWI224536B - Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing - Google Patents

Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing Download PDF

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Publication number
TWI224536B
TWI224536B TW091137886A TW91137886A TWI224536B TW I224536 B TWI224536 B TW I224536B TW 091137886 A TW091137886 A TW 091137886A TW 91137886 A TW91137886 A TW 91137886A TW I224536 B TWI224536 B TW I224536B
Authority
TW
Taiwan
Prior art keywords
insulating film
layer
wiring layer
wiring
insulating
Prior art date
Application number
TW091137886A
Other languages
English (en)
Chinese (zh)
Other versions
TW200307589A (en
Inventor
Motoshu Miyajima
Toshiyuki Karasawa
Tsutomu Hosoda
Satoshi Otsuka
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW200307589A publication Critical patent/TW200307589A/zh
Application granted granted Critical
Publication of TWI224536B publication Critical patent/TWI224536B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW091137886A 2002-06-07 2002-12-30 Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing TWI224536B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002166621A JP4076131B2 (ja) 2002-06-07 2002-06-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200307589A TW200307589A (en) 2003-12-16
TWI224536B true TWI224536B (en) 2004-12-01

Family

ID=29706730

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091137886A TWI224536B (en) 2002-06-07 2002-12-30 Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing

Country Status (5)

Country Link
US (1) US6686285B2 (https=)
JP (1) JP4076131B2 (https=)
KR (1) KR100814234B1 (https=)
CN (1) CN1225019C (https=)
TW (1) TWI224536B (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004253791A (ja) * 2003-01-29 2004-09-09 Nec Electronics Corp 絶縁膜およびそれを用いた半導体装置
US7217649B2 (en) * 2003-03-14 2007-05-15 Lam Research Corporation System and method for stress free conductor removal
JP2006165214A (ja) * 2004-12-07 2006-06-22 Sony Corp 半導体装置およびその製造方法
KR100711912B1 (ko) * 2005-12-28 2007-04-27 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
JP4231055B2 (ja) * 2006-02-06 2009-02-25 株式会社東芝 半導体装置及びその製造方法
JP2007251135A (ja) * 2006-02-18 2007-09-27 Seiko Instruments Inc 半導体装置およびその製造方法
JP2007294514A (ja) * 2006-04-21 2007-11-08 Renesas Technology Corp 半導体装置
US8193087B2 (en) * 2006-05-18 2012-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Process for improving copper line cap formation
JP2010171064A (ja) * 2009-01-20 2010-08-05 Panasonic Corp 半導体装置及びその製造方法
JP2012064713A (ja) * 2010-09-15 2012-03-29 Toshiba Corp 半導体装置の製造方法
US11862607B2 (en) * 2021-08-16 2024-01-02 Micron Technology, Inc. Composite dielectric structures for semiconductor die assemblies and associated systems and methods

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
KR100238220B1 (en) * 1996-12-17 2000-01-15 Samsung Electronics Co Ltd Plattening method of semiconductor device
US6140226A (en) * 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
US6420261B2 (en) * 1998-08-31 2002-07-16 Fujitsu Limited Semiconductor device manufacturing method
US6150272A (en) * 1998-11-16 2000-11-21 Taiwan Semiconductor Manufacturing Company Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage
KR100292409B1 (ko) * 1999-05-24 2001-06-01 윤종용 실리콘-메틸 결합을 함유하는 절연층을 포함하는 다층 구조의 절연막 및 그 형성방법
JP2001144086A (ja) * 1999-08-31 2001-05-25 Sony Corp 埋め込み配線の形成方法、及び、基体処理装置
US7041599B1 (en) * 1999-12-21 2006-05-09 Applied Materials Inc. High through-put Cu CMP with significantly reduced erosion and dishing
US6380003B1 (en) * 1999-12-22 2002-04-30 International Business Machines Corporation Damascene anti-fuse with slot via
US6503827B1 (en) * 2000-06-28 2003-01-07 International Business Machines Corporation Method of reducing planarization defects
JP3917355B2 (ja) * 2000-09-21 2007-05-23 株式会社東芝 半導体装置およびその製造方法
US20020064951A1 (en) * 2000-11-30 2002-05-30 Eissa Mona M. Treatment of low-k dielectric films to enable patterning of deep submicron features
US6432811B1 (en) * 2000-12-20 2002-08-13 Intel Corporation Method of forming structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures
US6583047B2 (en) * 2000-12-26 2003-06-24 Honeywell International, Inc. Method for eliminating reaction between photoresist and OSG
JP4160277B2 (ja) * 2001-06-29 2008-10-01 株式会社東芝 半導体装置の製造方法
US6562725B2 (en) * 2001-07-05 2003-05-13 Taiwan Semiconductor Manufacturing Co., Ltd Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers
KR100442863B1 (ko) * 2001-08-01 2004-08-02 삼성전자주식회사 금속-절연체-금속 커패시터 및 다마신 배선 구조를 갖는반도체 소자의 제조 방법
JP4131786B2 (ja) * 2001-09-03 2008-08-13 株式会社東芝 半導体装置の製造方法およびウエハ構造体
US6440840B1 (en) * 2002-01-25 2002-08-27 Taiwan Semiconductor Manufactoring Company Damascene process to eliminate copper defects during chemical-mechanical polishing (CMP) for making electrical interconnections on integrated circuits
US6531386B1 (en) * 2002-02-08 2003-03-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dish-free copper interconnects

Also Published As

Publication number Publication date
TW200307589A (en) 2003-12-16
CN1225019C (zh) 2005-10-26
JP4076131B2 (ja) 2008-04-16
US20030228765A1 (en) 2003-12-11
KR20030095189A (ko) 2003-12-18
JP2004014828A (ja) 2004-01-15
US6686285B2 (en) 2004-02-03
KR100814234B1 (ko) 2008-03-17
CN1467817A (zh) 2004-01-14

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees