TWI223452B - Ferroelectric memory transistor and method for forming the same - Google Patents

Ferroelectric memory transistor and method for forming the same Download PDF

Info

Publication number
TWI223452B
TWI223452B TW092107403A TW92107403A TWI223452B TW I223452 B TWI223452 B TW I223452B TW 092107403 A TW092107403 A TW 092107403A TW 92107403 A TW92107403 A TW 92107403A TW I223452 B TWI223452 B TW I223452B
Authority
TW
Taiwan
Prior art keywords
ferroelectric
gate
layer
cup
insulator
Prior art date
Application number
TW092107403A
Other languages
English (en)
Other versions
TW200308095A (en
Inventor
Sheng-Teng Hsu
Fengyan Zhang
Tingkai Li
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200308095A publication Critical patent/TW200308095A/zh
Application granted granted Critical
Publication of TWI223452B publication Critical patent/TWI223452B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40111Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31641Deposition of Zirconium oxides, e.g. ZrO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31645Deposition of Hafnium oxides, e.g. HfO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Description

1223452 (1) 玖、發明說明 【發明所屬之技術領域】 本發明與製造長效記憶記憶體單電晶體鐵電ram有 關,特別是與鐵電單元包封在高-k介電質中的鐵電RAM 有關。 【先前技術】
習知技術的單電晶體鐵電氧化物半導體(MF0S)閘堆 疊包含頂電極、鐵電層、及氧化物層。這類裝置在被規劃 後,從頂電極流入的電子或電洞會陷在鐵電層內。被陷住 之電荷的極性與極化電荷相反。極化電荷被這些陷住的電 荷補償,致使記憶體窗口變小。結果使得電晶體的記憶持 久性退化。 本發明的目地是提供一種非揮性的鐵電記憶體裝置, 其消除了與漏電相關的電晶體記憶持久性退化的情形。
本發明的另一目的是提供一種鐵電記憶體格,包括包 封在高-k介電質內的鐵電單元。 【發明內容】 按照本發明的鐵電記憶電晶體包含··具有源區、聞區 與汲區的基體;位於閘區上的閘堆疊,包括高-k絕緣體 單元,包括第一高-k杯與第二高-k杯;鐵電單元,其中 該鐡電單元被包封在該高-k絕緣體單元內;以及頂電極 ’位於該高-k絕緣體單元的頂部;鈍性氧化物層,位於 -6 - (2) (2)1223452 基體與聞堆疊的上方;以及,覆以金屬,形成分別到達源 區、汲區及閘堆疊的接點,藉以達到上述目的。 形成該高-k絕緣體單元的材料可選用自Hf02、Zr02 、HfZrOx 〇 該局-k絕緣體單元的厚度大約在2奈米到1 〇奈米之 間。 形成該鐵電單元的材料可選用自pg〇、ΡΖΤ、ΒΤΟ、 SBTO 及 SBTN 〇 形成該頂電極的材料可選用自銅、鋁、銥、鉑。 形成按照本發明之鐵電記憶電晶體的方法包含·· a)準 備一基體,包括形成源區、閘區、汲區及氧化物裝置隔離 區;b)在基體上沈積犧牲氧化物層;c)在犧牲氧化物層上 沈積閘位置固定層;d)遮罩位於閘區上的閘位置固定層與 犧牲氧化物層,並去除源區、汲區及氧化物裝置隔離區上 方的閘位置固定層與犧牲氧化物層;e)在步驟a)到d)所得 到的結構上沈積一層氧化物,其厚度大約是閘位置固定層 的兩倍;f)整平步驟a)到e)所得到的結構直到閘位置固定 層的平面;g)去除閘區的閘位置固定層及犧牲氧化物層以 形成閘位置固定結構;h)在步驟a)到g)所得到的結構上沈 積高-k絕緣體層以形成第一高-k杯;i)以鐵電材料塡入第 一高-k杯以形成鐡電單元;j)整平鐵電單元直到氧化物層 的上平面;k)在步驟a)到j)所得到的結構上沈積另一高-k 絕緣體層,以在鐵電單元上形成第二高-k杯;1)在第二 尚-k杯上沈積頂電極以形成聞電極與閘堆疊;m)在步驟 (3) (3)1223452 a)到1)所得到的結構上沈積一層鈍性氧化物;η)蝕刻鈍性 氧化物以形成分別到達源區、汲區及閘堆疊的接觸通道; 以及〇)在步驟a)到η)所得到的結構上覆以金屬’藉以達 成上述目的。 沈積高-k絕緣體層與沈積第一高-k杯的該步驟g)包 括在Hf〇2、Zr02、HfZrOx中選用高-k絕緣體材料。 沈積高-k絕緣體層與沈積第一高-k杯的該步驟g)包 括沈積一層厚度大約2奈米到1 0奈米的高-k材料層。 以鐵電材料塡入第一高-k杯的該步驟h)包括在PG0 、PZT、ΒΤ0、SBT0及SBTN中選用鐵電材料。 以鐵電材料塡入第一高-k杯的該步驟h)包括在第一 高-k杯內塡入厚度大約1 0 0奈米到6 0 0奈米的鐵電材料 〇 在第二高-k杯上沈積頂電極以形成閘電極及閘堆疊 的該步驟k)包括在銅、鋁、銥、鉑中選用頂電極的材料 〇 沈積閘位置固定層的該步驟C)包括沈積一層選用自氮 化矽及複矽之材料。 現已說明了本發明的槪要與目的,以便快速地理解本 發明的特性。配合附圖參考以下對本發明之較佳實施例的 詳細描述,將可更徹底瞭解本發明。 【實施方式】 相關申請案 -8- (4) (4)1223452 本申請案與Hsu等人於200 1年3月28日提出申請之 名稱爲 “MFOS memory transistor and method of fabricating same” 之 09/820,039 號申請案相關。 圖1是習知電晶體1 〇的槪圖。例如習知電晶體1 〇是 一典型先進的電晶體,諸如金屬-鐵電-氧化物半導體 (MF0S)電晶體、金屬-鐵電-絕緣體半導體(MFIS)電晶體或 類似物。 電晶體1 〇包括基體12,具有源區1 4、汲區1 6及閘 區1 8,以及在閘區1 8上的閘堆疊2 0。 閘堆疊20包括高-k絕緣體22、鐵電單元24及頂電 極26。在習知中,高-k絕緣體22包在鐵電單元24的四 周及下方。該結構被鈍性氧化物2 8覆蓋,其內形成有通 道,以分別提供源區14、閘堆疊20及汲區1 6所需的金 屬接點3 0、3 2、3 4。 閘堆疊20包括在矽基體上的金屬-鐵電薄膜-絕緣體 (MFIS)。高-k絕緣體22具有高介電常數及低漏電的特性 ,其材料可選用自諸如Hf02、Zr02、HfZrOx。鐵電單元 24 的材料可選用自鉛鍺氧化物的材料群,包括 (Pb5Ge3〇i i) (PGO) 、 P b (Z r 5 T i) Ο 3 (P Z T) 、 S r B i 2 T a2 Ο 9 (BTO)、SrBa2Ta209(SBT0)及 S rB i 2 (T a i xNb x) 2 Ο 9 ( S B T N) ,以及,頂電極可使用銅、鋁、銥或鉑形成。此類結構稱 爲鐡電電容器。 圖2描繪圖1之鐵電電容器被規劃到低臨限電壓狀態 且閘在接地狀態時之記憶保持期間電荷與場的分布。箭頭 -9- (5)1223452 元 跨 緣 鐵 on 緣 電 26 的 極 鐵 體 5 電 的 -k 36代表高-k絕緣體22的電壓,箭頭38代表鐡電單 24的電壓VFE,40代表閘堆疊20頂部的電壓V。。此爲 於高-k絕緣體22及鐵電單元24的電壓。跨於高-k絕 體22的電壓等於跨於鐵電單元24的電壓但極性相反。 電單元 24中的電壓稱爲去極化電壓(de-polarizati voltage)。
Vfe = V〇x = V〇〇 (1) V〇〇 = Qr/(C〇x + Cfe) (2) 其中,Qr是鐵電單元24上的電荷,是高-k絕 體22的電容’ Cfe是鐵電單元24的電容。 雖然此無法使電洞或電子從高-k絕緣體22流入鐵 單元(鐡電薄膜)24,但有大量的電子與電洞在頂電極 內。接下來將描述電洞從頂電極26陷入鐵電單元24中 現象。 圖3 a是解釋電荷被陷住時的槪圖。電洞會從頂電 26移入鐡電單元24,如圖3a所示。此現象稱爲金屬― 電-金屬(MFM)電容器的漏電。電涧無法流過高_k絕緣 22由於高-k絕緣體22與鐵電單元24之介面的電位障 以及高-k絕緣體2 2中的電場極性與鐵電單元2 4中的 場極性相反,故電洞無法流過高-k絕緣體22。 圖3 b是解釋電荷被陷住的另一槪圖。如參考圖3 & 描述,移入鐵電材料的電洞無法從鐵電單元24流到高 絕緣體22 ’仍被陷在鐵電單元24內,如圖3 b的說明 -10、 (6) (6)1223452 其中VFE與Vm都等於零。陷在鐵電單元24內的電洞補 償了鐡電單元24內被極化的電子。此縮小了記憶電晶體 的記憶窗口,並使裝置的記憶特性衰退。當記憶電晶體被 規劃到它的高臨限電壓狀態,電荷與電壓的極性改變,不 過,發生上述的電子流動與陷入機制。 圖4是按照本發明之鐵電記憶電晶體5 0的槪圖。在 按照本發明的鐡電記憶電晶體50中,消除了參閱圖} _3 說明之與記憶保持退化相關的漏電問題,解決之道是在鐡 電薄膜與頂電極間使用了額外的絕緣體。 電晶體5 0包括基體5 2,具有源區5 4、汲區5 6及閘 區5 8,以及閘堆疊6 0。閘堆疊6 0包括包封鐵電單元6 4 的高-k絕緣體62及頂電極66。基體52具有一氧化物隔 離區(氧化物單元隔離區)90。 高-k絕緣體62包括位於鐵電單元64與矽基體52間 ’包封住鐵電單元64側面的第一高-k杯(或簡稱爲下部 )62L,以及位於鐵電單元64與頂電極66間的第二高_k杯 (或簡稱爲上部)62U。因此,鐵電單元64被包在高_k絕緣 體62(第一高-k杯62L與第二高-k杯62U)內。此結構被 砂氧化物層96及鈍性氧化物68覆蓋,其內形成有通道, 分別供源區5 4、聞堆疊6 0及汲區5 6的金屬接點7 0、7 2 及7 6通過。閘堆疊6 0包括在矽基體上的金屬-鐵電薄膜-絕緣體(MFIS)。 高-k絕緣體62具有高介電常數與低漏電的特性,其 材料可選用自諸如Hf02、Zi*02、HfZrOx。鐵電單元64的 -11 - (7) (7)1223452 材料可選用自鉛鍺氧化物的材料群,包括(Pb5Ge30M) (PGO) 、 Pb(Zr,Ti)03 (PZT) 、 SrBi2Ta209 (BTO)、 SrBa2Ta2 09(SBT0)及 SrBidTabxNbxhC^ (SBTN),以及, 頂電極可使用銅、鋁、銥或鉑形成。 圖5描繪本發明之鐵電記憶電晶體的狀態。圖5說明 當鐵電記憶電晶體被規劃到低臨限電壓,且閘電壓回到接 地電位時的電場極性與電荷分布。跨於鐵電單元6 4的電 壓7 8(VFE)等於跨於第一高-k杯62L(箭頭76,ν0Χ1)與第 二高-k杯62U(箭頭80,ν〇χ2)的電壓和。鐵電單元64內 的電場極性與第一及第二高-k杯6 2 L及6 2 U內的相反。 在習知技術中發現與漏電相關的劣化機制在此結構中並不 存在,因爲在兩絕緣體(第一及第二高-k杯62L及62U)中 並無自由載子,且因爲電場分布能防止電流載子流入鐵電 單元64。箭頭82代表頂電極66之頂部的電壓VQ。本發 明之結構中能使記憶體劣化的唯一來源是去極化電場。 當本發明的鐡電記憶電晶體被規劃到它的高臨限電壓 狀態時,在鐵電單元64與第一及第二高-k杯6 2L及6 2U 的電荷與電場極性的方向都改變。因此,沒有與電荷陷阱 相關之漏電所造成的記憶保持劣化。 以下將參閱圖6- 1 0描繪製造本發明之鐵電記憶電晶 體的方法。 圖6描繪製造本發明之鐵電記憶電晶體之方法的步驟 。以任何先進的技術準備基體52。以井離子植入法在基 體52內形成包括源區54、汲區56及閘區58的活性區。 -12- (8) (8)1223452 裝置隔離法包括形成氧化物隔離區9 0的步驟,隔離區沿 著記憶電晶體的周邊延伸。 在源區5 4、汲區5 6、閘區5 8及氧化物隔離區9 0上 生長厚度大約2奈米到5奈米的犧牲閘氧化物層(犧牲氧 化物層)9 2,以及在犧牲閘氧化物層9 2上沈積厚度大約 1〇〇奈米到600奈米氮化矽層94。在氮化矽層94與犧牲 閘氧化物層92上製作遮罩,位在源區5 4、汲區5 6、閘區 5 8及氧化物隔離區9 0上的氮化矽層9 4及犧牲閘氧化物 層9 2被去除。因此,閘位置固定層是由仍保留在閘區5 8 上的氮化矽層94構成。氮化矽層可以使用複矽取代。 在圖6中,位在源區5 4、汲區5 6、及氧化物隔離區 9 〇上的犧牲閘氧化物層92被去除。不過,犧牲閘氧化物 層92也可以不去除,與矽氧化物層96 —同使用。 活性區(源區54及汲區56)可以使用源/汲植入法製備 ,包括LDD、Halo、以及Ν +或Ρ +離子植入。因此,得到 圖6描繪的結構。 圖7描繪製造本發明之鐵電記憶電晶體之方法的步驟 。沈積厚度大約2 0 0到1 2 0 0奈米的氧化矽層9 6。此氧化 矽層9 6的厚度大約是閘位置固定厚度的兩倍較佳。以 C MP法整平氧化矽層96以使結構平滑,整平處理停止於 氮化矽層94的平面(或閘位置固定)。因此,得到圖7描 繪的結構。 圖8描繪製造本發明之鐵電記憶電晶體之方法的步驟 。如圖8的描繪,蝕刻所得到的結構,去除氮化矽層94( -13- (9) (9)1223452 閘位置固定層)以形成閘位置固定結構8〇〇。以濕軸法氮 化砂層94(閘位置固定層)蝕刻較佳。接下來,以Bhf鈾 刻整個結構以去除閘區5 8的犧牲閘氧化物層9 2。 接著’在整個結構上沈積閘絕緣體62。如前所述, 閘絕緣體62的材料選用自Hf02、Zr02、HfZrOx。如前所 述,閘絕緣體62是由高_k絕緣體構成,其厚度大約2奈 米到1 〇奈米。閘絕緣體62與矽基體52接觸的部分對應 於聞區5 8,且覆蓋閘位置固定結構800的壁,賦予的編 號爲62L。在本文中,62L指的是第一高_k杯或高下部 〇 圖9描繪製造本發明之鐵電記憶電晶體之方法的步驟 。沈積鐵電薄膜(鐵電單元)64以塡充閘位置固定結構800 。鐵電薄膜64的材料選用自諸如pg〇、PZT、BTO、 SB TO及SB TN等材料。鐵電薄膜64塡入第一高-k杯62L 所形成的“杯”中。 接下來’整平鐵電薄膜6 4,直到氧化矽層9 6的平面 停止。可以使用化學機械拋磨法(CMP)或其它習知平面回 蝕處理使表面光滑。因此,得到圖9所描繪的結構。 圖1 〇描繪製造本發明之鐵電記憶電晶體之方法的步 驟。接著,以CVD法再在圖9描繪的結構上沈積厚度2 奈米到1 0奈米的高-k絕緣體,此爲高-k絕緣體的另一部 分6 2U,在本文中稱爲高-k上部或第二高-k杯。所選擇 的高-k絕緣體材料要具有低漏電特性。之後,在高-k絕 緣體上形成頂電極66。頂電極的材料選用自錦、銅、鉑 -14- (10) (10)1223452 、銥。 蝕刻頂電極與另一商-k絕緣體以形成圖1 0中所描繪 的頂電極66與第二高-k杯62U,致成一控制閘電極與閘 堆疊60。鐵電單元64被高-k絕緣體62(第一及第二高-k 杯6 2L及62U)包封住,以CVD沈積一層鈍性氧化物68( 圖4),蝕刻此結構以形成接點通道,並覆以金屬,致得 到圖4所描繪的結構。 至此已揭示了製造具有長記憶保持特性之鐵電記憶電 晶體的方法。須瞭解,可做其它的變化與修改,都在所附 申請專利所定義的發明範圍內。 如前所述,按照本發明的鐵電記憶電晶體包含:具有 源區、閘區與汲區的基體;位於閘區上的閘堆疊,包括 高-k絕緣體單元,包括第一高-k杯與第二高-k杯;鐵電 單元,其中該鐡電單元被包封在該高-k絕緣體單元內; 以及頂電極,位於該高-k絕緣體單元的頂部;鈍性氧化 物層,位於基體與閘堆疊的上方;以及覆以金屬,形成到 源區、汲區及閘堆疊的接點。因此,與漏電相關會致使記 憶保持特性劣化的電荷陷阱不復存在。因此,鐵電記憶電 晶體的記憶保持特性不會衰退。 【圖式簡單說明】 圖1是習知電晶體1 0的槪圖。 圖2描繪圖1之鐵電電容器被規劃到低臨限電壓狀態 且閘在接地狀態時之記憶保持期間電荷與場的分布。 -15- (11) (11)1223452 圖3 a是解釋電荷被陷住時的槪圖。 圖3 b是另一解釋電荷被陷住時的槪圖。 圖4是按照本發明之鐵電記憶電晶體5 0的槪圖。 圖5描繪本發明之鐵電記憶電晶體的狀態。 圖6- 1 0描繪製造本發明之鐵電記憶電晶體之方法的 連續步驟。 元件表 10 習知電晶體 12 基體 14 源區 16 汲區 18 閘區 2 0 閘堆疊 22 高-k絕緣體 2 4 鐡電單元 2 6 頂電極 28 鈍性氧化物 3 0 源區的金屬接點 32 閘堆疊的金屬接點 34 汲區的金屬接點 50 鐵電記憶電晶體 52 基體 54 源區 - 16- (12)1223452 5 6 汲區 58 閘區 60 閘堆疊 62 高-k絕緣體 64 鐵電單元 6 6 頂電極 62 第一局-k杯
62 第二高-k杯 9 6 砂氧化物層 68 鈍性氧化物 7 0 源區的金屬接點 72 閘堆疊的金屬接點 74 汲區的金屬接點 92 犧牲閘氧化物層 9 4 氮化砂層
80 0 閘位置固定結構 -17-

Claims (1)

  1. (1) (1)1223452 拾、申請專利範圍 1. 一種鐵電記憶電晶體,包含: 基體,具有源區、閘區與汲區; 閘堆疊,位於閘區上,包括: 尚-k絕緣體單兀,包括第一高_ k杯與第二高_ k 杯; 鐵電單元,其中該鐵電單元被包封在該高絕緣 體單元內;以及 頂電極,位於該高-k絕緣體單元的頂部; 鈍性氧化物層’位於基體與閘堆疊的上方;以及 覆以金屬,以形成分別到達源區、汲區及閘堆疊的接 點。 2 ·如申請專利範圍第1項的鐵電記憶電晶體,其中, 形成該咼-k絕緣體單元的材料可選用自Hf〇2、Zr02、 HfZrOx。 3 .如申請專利範圍第1項的鐵電記憶電晶體,其中, δ亥尚-k絕緣體單元的厚度大約在2奈米到1 〇奈米之間。 4 .如申請專利範圍第1項的鐵電記憶電晶體,其中, 形成④鐵電單兀的材料可選用自pG〇、ρζτ、BTO、SBTO 及 SBTN。 5. 如申請專利範團第1項的鐵電記憶電晶體,其中, 形成該頂電極的材料可選用自銅、鋁、銥、鉑。 6. 如申請專利範阖第1項的鐵電記憶電晶體,其中, 形成該頂電極的材料可選用自銅、鋁、銥、鉑。 -18- (2) (2)1223452 7 . —種形成鐵電記憶電晶體的方法,包含: a) 準備一基體’包括形成源區、聞區、汲區及氧化物 裝置隔離區; b) 在基體上沈積犧牲氧化物層; Ο在犧牲氧化物層上沈積閘位置固定層; d) 遮罩位於閘區上的閘位置固定層與犧牲氧化物層, 並去除源區、汲區及氧化物裝置隔離區上方的閘位置固定 層與犧牲氧化物層; e) 在步驟a)到d)所得到的結構上沈積一層氧化物,其 厚度大約是閘位置固定層的兩倍; f) 整平步驟a)到e)所得到的結構直到閘位置固定層的 平面; g) 去除聞區的閘位置固定層及犧牲氧化物層以形成閘 位置固定結構; h) :&步驟a)到g)所得到的結構上沈積高-k絕緣體層 以幵< 成桌一高4杯; 0以鐵電材料塡入第一高_k杯以形成鐵電單元; 鐵電單元直到氧化物層的上平面; k)#步*驟a)到j)所得到的結構上沈積另一高_k絕緣體 層’以在鐵電單元上形成第二高-k杯; 高4杯上沈積頂電極以形成閘電極與閘堆疊 J ^ a)到1)所得到的結構上沈積一層鈍性氧化 物; -19- (3) (3)1223452 η)蝕刻鈍性氧化物以形成分別到達源區、汲區及_堆 疊的接觸通道;以及 0)在步驟a)到η)所得到的結構上覆以金屬。 8 .如申請專利第7項的方法,其中,沈積高-k絕緣體 層與沈積第一高-k杯的該步驟g)包括在Hf〇2、Zr〇2、 HfZr〇x中選用高-k絕緣體材料。 9.如申請專利第7項的方法,其中,沈積高-k絕緣體 層與沈積第一高-k杯的該步驟g)包括沈積一層厚度大約2 奈米到1 〇奈米的高-k材料層。 1 0 ·如申請專利第7項的方法,其中,以鐵電材料塡 入第一高-k杯的該步驟h)包括在pg〇、ΡΖΤ、ΒΤ0、 SBT0及SB TN中選用鐡電材料。 1 1 .如申請專利第7項的方法,其中,以鐵電材料塡 入第一高-k杯的該步驟h)包括在第一高-k杯內塡入厚度 大約1 0 0奈米到6 0 0奈米的鐡電材料。 12. 如申請專利第7項的方法,其中,在第二高_k杯 上沈積頂電極以形成聞電極及閱堆疊的該步驟k)包括在 銅、鋁、銥、鉑中選用頂電極的材料。 13. 如申請專㈣7項的方$,其中,沈積聞位置固 定層的該步驟〇包括沈積一層選用自氮化矽及複矽之材料 -20、
TW092107403A 2002-06-04 2003-04-01 Ferroelectric memory transistor and method for forming the same TWI223452B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/164,785 US6531325B1 (en) 2002-06-04 2002-06-04 Memory transistor and method of fabricating same

Publications (2)

Publication Number Publication Date
TW200308095A TW200308095A (en) 2003-12-16
TWI223452B true TWI223452B (en) 2004-11-01

Family

ID=22596075

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092107403A TWI223452B (en) 2002-06-04 2003-04-01 Ferroelectric memory transistor and method for forming the same

Country Status (6)

Country Link
US (2) US6531325B1 (zh)
EP (1) EP1369926A3 (zh)
JP (1) JP4179900B2 (zh)
KR (1) KR20030094499A (zh)
CN (1) CN1245764C (zh)
TW (1) TWI223452B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6503763B2 (en) * 2001-03-27 2003-01-07 Sharp Laboratories Of America, Inc. Method of making MFMOS capacitors with high dielectric constant materials
US7297602B2 (en) * 2003-09-09 2007-11-20 Sharp Laboratories Of America, Inc. Conductive metal oxide gate ferroelectric memory transistor
US7008833B2 (en) * 2004-01-12 2006-03-07 Sharp Laboratories Of America, Inc. In2O3thin film resistivity control by doping metal oxide insulator for MFMox device applications
US6995025B2 (en) * 2004-06-21 2006-02-07 Sharp Laboratories Of America, Inc. Asymmetrical programming ferroelectric memory transistor
KR100642635B1 (ko) * 2004-07-06 2006-11-10 삼성전자주식회사 하이브리드 유전체막을 갖는 반도체 집적회로 소자들 및그 제조방법들
US7378286B2 (en) * 2004-08-20 2008-05-27 Sharp Laboratories Of America, Inc. Semiconductive metal oxide thin film ferroelectric memory transistor
US7339813B2 (en) * 2004-09-30 2008-03-04 Sharp Laboratories Of America, Inc. Complementary output resistive memory cell
KR100890609B1 (ko) * 2006-08-23 2009-03-27 재단법인서울대학교산학협력재단 강유전체, 그 제조방법, 및 그 강유전체를 포함하는 반도체 캐패시터와 mems 디바이스
CN101894844B (zh) * 2010-06-04 2012-05-09 清华大学 基于金属氧化物气相沉积铁电动态随机存储器及制备方法
DE102012205977B4 (de) * 2012-04-12 2017-08-17 Globalfoundries Inc. Halbleiterbauelement mit ferroelektrischen Elementen und schnellen Transistoren mit Metallgates mit großem ε sowie Herstellungsverfahren
JP6067524B2 (ja) * 2013-09-25 2017-01-25 株式会社東芝 半導体装置および誘電体膜
KR102616129B1 (ko) * 2016-02-26 2023-12-21 에스케이하이닉스 주식회사 멀티 레벨 강유전체 메모리 장치 및 그 제조방법
CN105788864B (zh) * 2016-02-29 2017-12-08 湘潭大学 一种提高pzt铁电薄膜负电容的方法
CN106898644B (zh) * 2017-01-23 2019-07-30 西安电子科技大学 高击穿电压场效应晶体管及其制作方法
US10784362B2 (en) 2017-10-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN109801977A (zh) * 2019-01-28 2019-05-24 中国科学院微电子研究所 存储器
US11569382B2 (en) * 2020-06-15 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of fabricating the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2812388B2 (ja) * 1988-01-18 1998-10-22 富士通株式会社 Soi半導体装置の製造方法
US5144390A (en) * 1988-09-02 1992-09-01 Texas Instruments Incorporated Silicon-on insulator transistor with internal body node to source node connection
EP0478799B1 (en) * 1990-04-24 1996-12-04 Ramtron International Corporation Semiconductor device having ferroelectric material and method of producing the same
US5384729A (en) * 1991-10-28 1995-01-24 Rohm Co., Ltd. Semiconductor storage device having ferroelectric film
US5499207A (en) * 1993-08-06 1996-03-12 Hitachi, Ltd. Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same
US6413883B1 (en) * 1996-03-04 2002-07-02 Symetrix Corporation Method of liquid deposition by selection of liquid viscosity and other precursor properties
US5731608A (en) * 1997-03-07 1998-03-24 Sharp Microelectronics Technology, Inc. One transistor ferroelectric memory cell and method of making the same
US5942776A (en) * 1997-03-07 1999-08-24 Sharp Laboratories Of America, Inc. Shallow junction ferroelectric memory cell and method of making the same
JP3281839B2 (ja) * 1997-06-16 2002-05-13 三洋電機株式会社 誘電体メモリおよびその製造方法
TW396454B (en) * 1997-06-24 2000-07-01 Matsushita Electrics Corporati Semiconductor device and method for fabricating the same
US6251763B1 (en) * 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
KR100269309B1 (ko) * 1997-09-29 2000-10-16 윤종용 고집적강유전체메모리장치및그제조방법
US5907762A (en) * 1997-12-04 1999-05-25 Sharp Microelectronics Technology, Inc. Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing
KR100399886B1 (ko) * 1998-07-02 2004-02-11 주식회사 하이닉스반도체 반도체 메모리 소자의 커패시터 형성 방법
US6048740A (en) * 1998-11-05 2000-04-11 Sharp Laboratories Of America, Inc. Ferroelectric nonvolatile transistor and method of making same
US6197668B1 (en) * 1998-11-06 2001-03-06 Advanced Micro Devices, Inc. Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices
JP2000252372A (ja) * 1999-02-26 2000-09-14 Sharp Corp 半導体メモリ装置及びその製造方法
US6140672A (en) * 1999-03-05 2000-10-31 Symetrix Corporation Ferroelectric field effect transistor having a gate electrode being electrically connected to the bottom electrode of a ferroelectric capacitor
KR100457121B1 (ko) * 1999-06-04 2004-11-16 세이코 엡슨 가부시키가이샤 강유전체 메모리 소자 및 그 제조 방법
DE19931125A1 (de) * 1999-07-06 2001-01-25 Infineon Technologies Ag Ferroelektrischer Transistor
DE19940381A1 (de) * 1999-08-25 2001-04-05 Infineon Technologies Ag Ferroelektrischer Transistor und Verfahren zu dessen Herstellung
US6303502B1 (en) * 2000-06-06 2001-10-16 Sharp Laboratories Of America, Inc. MOCVD metal oxide for one transistor memory
JP3627640B2 (ja) * 2000-09-22 2005-03-09 松下電器産業株式会社 半導体メモリ素子
US6392280B1 (en) * 2000-10-19 2002-05-21 Advanced Micro Devices, Inc. Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process
US6602720B2 (en) * 2001-03-28 2003-08-05 Sharp Laboratories Of America, Inc. Single transistor ferroelectric transistor structure with high-K insulator and method of fabricating same

Also Published As

Publication number Publication date
US6703655B2 (en) 2004-03-09
JP2004015047A (ja) 2004-01-15
TW200308095A (en) 2003-12-16
KR20030094499A (ko) 2003-12-12
JP4179900B2 (ja) 2008-11-12
CN1245764C (zh) 2006-03-15
US6531325B1 (en) 2003-03-11
EP1369926A3 (en) 2005-06-15
EP1369926A2 (en) 2003-12-10
CN1497735A (zh) 2004-05-19
US20030222291A1 (en) 2003-12-04

Similar Documents

Publication Publication Date Title
TWI223452B (en) Ferroelectric memory transistor and method for forming the same
US6743681B2 (en) Methods of Fabricating Gate and Storage Dielectric Stacks having Silicon-Rich-Nitride
TWI359461B (en) Recess channel flash architecture for reduced shor
US6462366B1 (en) Ferroelectric nonvolatile transistor
JP3664467B2 (ja) 化学機械的研磨を用いたシングルトランジスタ強誘電体メモリセルの製造方法
KR20030067956A (ko) 퀀텀 도트를 가지는 메모리 소자 및 그 제조방법
JP4080050B2 (ja) 強誘電体メモリセル、半導体構造およびそれらの製造方法
US6048738A (en) Method of making ferroelectric memory cell for VLSI RAM array
JP2000353790A (ja) 強誘電体アプリケーションのためのPb5Ge3O11薄膜の化学蒸着法
KR20020035616A (ko) 강유전성 트랜지스터
TW201419454A (zh) 供非揮發性記憶體裝置及方法用之電極結構
TW200939476A (en) Channel stress engineering using localized ion implantation induced gate electrode volumetric change
US5942776A (en) Shallow junction ferroelectric memory cell and method of making the same
WO2023168807A1 (zh) 半导体结构及其形成方法
KR20020066997A (ko) Mfmos/mfms 비휘발성 메모리 트랜지스터 및 그제조방법
US20050156217A1 (en) Semiconductor memory device and method for fabricating the same
US20240113222A1 (en) Threshold voltage modulation for thin film transistors
JP2004134507A (ja) 積層絶縁膜を備えた不揮発電界効果型トランジスタ
KR20230081476A (ko) 전하 트랩 사이트를 구비하는 반도체 장치 및 이의 제조 방법
Lyu et al. Characteristics of ferroelectric transistors with BaMgF4 dielectric
TWI285957B (en) Non-volatile memory device and method of operating the same
CN115701212A (zh) 半导体结构及其形成方法
Krimmel et al. Silicon Nitride Dielectrics and Masks in Capacitors
KR20050038298A (ko) 강유전 반도체를 기반으로 한 트랜지스터 구조
JPH0437171A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees