WO2023168807A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023168807A1
WO2023168807A1 PCT/CN2022/088945 CN2022088945W WO2023168807A1 WO 2023168807 A1 WO2023168807 A1 WO 2023168807A1 CN 2022088945 W CN2022088945 W CN 2022088945W WO 2023168807 A1 WO2023168807 A1 WO 2023168807A1
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layer
gate
dielectric layer
gate dielectric
semiconductor structure
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PCT/CN2022/088945
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English (en)
French (fr)
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章纬
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长鑫存储技术有限公司
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Priority to US17/861,952 priority Critical patent/US20230284453A1/en
Publication of WO2023168807A1 publication Critical patent/WO2023168807A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

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  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method of forming the same.
  • Silicon-Silicon Dioxide-Silicon Nitride-Silicon Dioxide-Silicon (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS) type flash memory and Ferroelectric Field Effect Transistor (FeFET) memory are currently the most advanced Two types of memory in the foreground.
  • SONOS memory is composed of a silicon substrate-tunneling oxide layer-charge storage layer silicon nitride-blocking oxide layer-polysilicon gate. This memory uses tunneling of electrons to compile and injection of holes to process data. Erase. SONOS memory has the advantages of simple process, low operating voltage and easy integration into standard complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process. However, as semiconductor device process nodes continue to shrink, traditional SONOS memory will suffer from poor retention and serious reliability problems when its size is reduced.
  • CMOS complementary Metal Oxide Semiconductor
  • FeFET memory is composed of metal electrodes, ferroelectric films, metal electrodes, buffer layers and semiconductor conductive channels. By applying voltage to the gate, the polarization of the electric dipoles in the ferroelectric film is adjusted, making the ferroelectric in the ferroelectric film The material has two different polarization states, thereby enabling the storage of data "0" and "1".
  • FeFET memory has the advantages of fast read and write response, low power consumption and non-destructive reading. However, the reliability of FeFET memory decreases significantly after multiple read, write, and erase operations.
  • embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.
  • embodiments of the present disclosure provide a semiconductor structure, including:
  • a gate electrode, the gate electrode is located on the surface of the gate dielectric layer
  • the gate dielectric layer includes an oxide layer, a charge trapping layer and an isolation layer stacked in sequence; the isolation layer is composed of a polarizing material capable of spontaneous polarization.
  • the polarizable material includes at least one of: ferroelectric oxides, ferroelectric fluorides, ferroelectric semiconductor materials, doped ferroelectric oxides, and polymer ferroelectric materials.
  • the isolation layer has a thickness greater than 1 nanometer.
  • the oxide layer is a high-K material layer; the material of the oxide layer includes at least one of the following: hafnium oxide and silicon oxide.
  • the charge trapping layer is made of silicon nitride.
  • the semiconductor structure further includes a spacer structure located on the gate dielectric layer and the sidewall of the gate;
  • the sidewall structure includes a first sidewall layer and a second sidewall layer located outside the first sidewall layer.
  • the material of the first spacer layer is silicon oxide or a low-K material; the material of the second spacer layer is an insulating material.
  • the semiconductor structure further includes a substrate including a plurality of well regions serving as sources or drains of transistors;
  • the gate dielectric layer is located on the upper surface of the substrate and between the source electrode and the drain electrode.
  • the semiconductor structure further includes a substrate, the substrate includes a plurality of well regions serving as sources or drains of transistors, and each of the well regions has at least one gate trench;
  • the gate is located in the gate trench, and the gate dielectric layer is located between the gate and the gate trench;
  • the thickness of the gate electrode is smaller than the thickness of the gate trench.
  • the semiconductor structure further includes a gate insulating layer located on the surface of the gate electrode and the gate dielectric layer;
  • a top surface of the gate insulating layer is flush with a top surface of the well region.
  • the semiconductor structure further includes a plurality of well regions; each of the well regions includes a plurality of mutually isolated active pillars;
  • the gate dielectric layer and the gate electrode sequentially annularly cover part of the active pillar, and the remaining part of the active pillar serves as the source or drain of the transistor.
  • the gate dielectric layer is flush with the top surface of the gate, and the top surface of the active pillar extends beyond the top surface of the gate dielectric layer.
  • embodiments of the present disclosure provide a method for forming a semiconductor structure, including:
  • the gate dielectric layer includes an oxide layer, a charge trapping layer and an isolation layer stacked in sequence, and the isolation layer is composed of a polarizing material capable of spontaneous polarization;
  • a gate electrode is formed on the surface of the isolation layer.
  • the gate is formed on the surface of the well region, and the gate dielectric layer and the gate are formed by the following steps:
  • oxidation material, charge trapping material, polarization material and gate material are deposited in sequence from bottom to top, correspondingly forming an initial oxide layer, an initial charge trapping layer, an initial isolation layer and an initial gate electrode;
  • the initial gate electrode, the initial isolation layer, the initial charge trapping layer and the initial oxide layer are sequentially etched through a mask with a preset window to form the gate electrode, the isolation layer, and the initial oxide layer. the charge trapping layer and the oxide layer.
  • the method before forming the gate dielectric layer and the gate electrode, the method further includes:
  • a sacrificial oxide layer is formed on the surface of each well region
  • the sacrificial oxide layer is removed through a wet etching process.
  • the gate is formed in a gate trench in the well region; the gate dielectric layer and the gate are formed by the following steps:
  • the initial gate dielectric layer and the initial gate electrode are etched back to expose part of the inner wall of the gate trench to form the gate dielectric layer and the gate electrode.
  • the method further includes:
  • a gate insulating layer is deposited on the surface of the gate dielectric layer and the gate electrode; wherein the top surface of the gate insulating layer is flush with the top surface of the well region.
  • the method further includes:
  • a first spacer layer and a second spacer layer are formed on the gate dielectric layer and the sidewall of the gate in sequence, and the first spacer layer and the second spacer layer form a spacer structure.
  • the gate is formed around each active pillar in the well region; the gate dielectric layer and the gate are formed by the following steps:
  • the initial gate dielectric layer and the initial gate electrode are etched back to expose part of the active pillars to form the gate dielectric layer and the gate electrode.
  • the polarizable material includes at least one of: ferroelectric oxides, ferroelectric fluorides, ferroelectric semiconductor materials, doped ferroelectric oxides, and polymer ferroelectric materials.
  • the semiconductor structure includes a gate dielectric layer and a gate located on the surface of the gate dielectric layer;
  • the gate dielectric layer includes an oxide layer, a charge trapping layer, and an isolation layer stacked in sequence.
  • the isolation layer is composed of a polarizable material capable of spontaneous polarization;
  • the gate electrode is located on the surface of the isolation layer.
  • the gate dielectric layer of the semiconductor structure provided by the embodiment of the present disclosure at least includes an isolation layer formed of a polarization material capable of spontaneous polarization, and the isolation layer can generate an additional polarization electric field, the polarization electric field can cause electrons or holes to It is easier to enter the charge trapping layer, and therefore, embodiments of the present disclosure can provide a semiconductor device with low operating voltage, low power consumption, and high reliability.
  • Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIGS 2 and 3 are schematic diagrams of the working principles of the semiconductor structure provided by embodiments of the present disclosure.
  • Figure 4 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 5a is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 5b is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 7a to 7h are schematic structural diagrams of a semiconductor formation process provided by embodiments of the present disclosure.
  • the disclosed embodiments combine SONOS memory technology and FeFET memory technology to propose a new semiconductor device with low operating voltage, low power consumption and high reliability.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure 10 includes a gate dielectric layer 101 and a gate electrode 102 located on the surface of the gate dielectric layer.
  • the gate dielectric layer 101 includes an oxide layer 101a, a charge trapping layer 101b and an isolation layer 101c stacked in sequence; the isolation layer 101c is composed of a polarizing material capable of spontaneous polarization.
  • the gate electrode 102 is located on the surface of the isolation layer 101c.
  • the oxide layer 101a may be a high-K material layer, and the high-K material layer may improve the effective oxide thickness (EOT) of the gate dielectric layer 101.
  • the material of the oxide layer 101a may include at least one of the following : Hafnium oxide (HfO 2 ) and silicon oxide.
  • the charge trapping layer 101b can be any material layer capable of capturing electrons, such as a silicon nitride layer.
  • the charge trapping layer 101b can be made of silicon nitride material.
  • Polarized materials include: ferroelectric oxides, ferroelectric fluorides, ferroelectric semiconductor materials, doped ferroelectric oxides, polymer ferroelectric materials, or any combination thereof.
  • the thickness of the isolation layer in a direction perpendicular to the plane of the substrate is greater than 1 nanometer.
  • the isolation layer is used to prevent electrons from tunneling between the gate and the charge trapping layer, assisting electrons to enter or leave the charge trapping layer, thereby reducing the operating voltage of the semiconductor structure and improving the retention characteristics and durability of the semiconductor structure.
  • the gate of the semiconductor structure may be a planar gate structure. Please continue to refer to FIG. 1 .
  • the semiconductor structure 10 further includes a substrate including an active region (only one well in the active region is shown in FIG. 1 region), wherein the gate dielectric layer 101 is located on the surface of the well region 103, and the gate dielectric layer 101 includes an oxide layer 101a, a charge trapping layer 101b and an isolation layer 101c stacked in sequence from bottom to top.
  • the well region is a region formed by N-type doping or P-type doping of a semiconductor substrate (such as a silicon substrate), and is used to form a transistor.
  • the semiconductor structure 10 further includes a spacer structure 104 ; the spacer structure 104 is located on the sidewalls of the gate dielectric layer 101 and the gate 102 , and the spacer structure 104 includes a first spacer layer 104a and a second spacer layer 104b located outside the first spacer layer 104a.
  • the material of the first spacer layer can be silicon oxide or a low-K material.
  • the low-K material can improve the coupling parasitic capacitance between the gate and the source and drain;
  • the material of the second spacer layer can be any material.
  • the insulating material can protect the gate when the source and drain are doped.
  • the material of the second spacer layer can be silicon nitride.
  • the semiconductor structure 10 further includes a lightly doped drain implantation region 105 ; the lightly doped drain implantation region 105 is located in the well region 103 at the bottom of the gate dielectric layer 101 .
  • the semiconductor structure 10 further includes a source electrode 106 and a drain electrode 107; the source electrode 106 and the drain electrode 107 are respectively located in the well region outside the lightly doped drain injection region 105, with respect to the gate.
  • the pole structure is symmetrically distributed.
  • the existence of the lightly doped drain implantation region is, on the one hand, to prevent the short channel effect caused by the continuous reduction of the gate width and the channel length corresponding to the gate, and on the other hand, for Reduce channel leakage current between source and drain.
  • the semiconductor structure 10 further includes a shallow trench isolation region 108 ; the plurality of well regions 103 are isolated from each other by the shallow trench isolation region 108 .
  • FIG. 2 and FIG. 3 are schematic diagrams of the working principle of the semiconductor structure provided by the embodiment of the present disclosure.
  • the working principle of the semiconductor structure provided by the embodiment of the present disclosure will be described below with reference to FIG. 2 and FIG. 3 .
  • the existence of the isolation layer can generate an additional polarization electric field, and the polarization electric field has the same direction as the external electric field generated by the gate voltage. Therefore, the polarization electric field can be controlled to help electrons in the well region move towards charge capture.
  • the transition in the layer that is, the existence of the polarization electric field can enhance the tunneling ability of electrons. Therefore, when the semiconductor structure includes an isolation layer, the operating voltage of the programming process is smaller and the durability is good, reducing the possible impact of high voltage on tunneling.
  • the damage caused by the layer, while the injected electrons or holes can reach the substrate farther away, making the electron or hole retention performance better, the possible leakage path becomes longer, and the leakage of one read and write is less.
  • the polarization direction of the isolation layer 101c gradually becomes consistent with the direction of the external electric field A. , thus generating a polarization electric field B.
  • the external electric field A and the polarization electric field B jointly control the electrons in the charge trapping layer 101b to escape into the well region 103, or the external electric field A and the polarization electric field B jointly control the electrons in the well region 103 to escape.
  • the holes are injected into the charge trapping layer 101b and recombine with the electrons captured in the charge trapping layer 101b.
  • the existence of the isolation layer can generate an additional polarization electric field, and the polarization electric field has the same direction as the external electric field generated by the gate voltage. Therefore, the polarization electric field can control the electrons in the charge trapping layer to move toward the well region. Escape, or control the injection of holes in the well region into the charge trapping layer, that is, the existence of the polarization electric field can enhance the tunneling ability of electrons or holes. Therefore, when the semiconductor structure includes an isolation layer, the gate only needs to apply a The erasing process can be achieved with a smaller negative voltage. In other words, the existence of the isolation layer can reduce the erasing voltage of the semiconductor structure and make the semiconductor structure have better retention.
  • the gate of the semiconductor structure may also be a buried gate structure.
  • Figure 4 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 4, the semiconductor structure 40 includes a gate dielectric layer. 401 and the gate 402 located in the gate dielectric layer 401.
  • the gate dielectric layer 401 includes an oxide layer 401a, a charge trapping layer 401b and an isolation layer 401c that are stacked in sequence; the isolation layer 401c is composed of a polarized material capable of spontaneous polarization; the gate 402 is located in the recess formed by the isolation layer 401c. inside of the trough.
  • the polarization material includes: ferroelectric oxide, ferroelectric fluoride, ferroelectric semiconductor material, doped ferroelectric oxide, polymer ferroelectric material, or any combination thereof.
  • the semiconductor structure 40 further includes a substrate including a plurality of well regions 403 (only one well region is shown in FIG. 4 ), and each well region 403 has at least one gate trench C ( 4 shows two gate trenches); the gate electrode 402 is located in the gate trench C, and the gate dielectric layer 401 is located between the gate electrode 402 and the gate trench C.
  • the thickness h1 of the gate 402 is smaller than the thickness h2 of the gate trench C in the direction perpendicular to the substrate.
  • the semiconductor structure 40 further includes a gate insulating layer 404 located on the surface of the gate electrode 402 and the gate dielectric layer 401 ; wherein, the top surface of the gate insulating layer 404 is in contact with the well region 403 The top surface is flush.
  • the gate insulation layer 404 is used to isolate the gate structure buried inside the well region 403 from other functional structures located on the surface of the well region 403 (not shown in the figure).
  • the gate of the semiconductor structure can also be a full-circuit gate structure.
  • Figure 5a is a cross-sectional view of the semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 5b is a top view of the semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 5a As shown in and 5b, the semiconductor structure 50 includes a gate dielectric layer 501 and a gate electrode 502 located inside the groove formed by the gate dielectric layer 501.
  • the gate dielectric layer 501 includes an oxide layer 501a, a charge trapping layer 501b and an isolation layer 501c stacked in sequence; the isolation layer 501c is composed of a polarized material capable of spontaneous polarization; the gate 502 is located on the surface of the isolation layer 501c.
  • the polarization material includes: ferroelectric oxide, ferroelectric fluoride, ferroelectric semiconductor material, doped ferroelectric oxide, polymer ferroelectric material, or any combination thereof.
  • the semiconductor structure 50 further includes an active region (only one well region in the active region is shown in FIG. 5a ); each well region 503 includes a plurality of mutually isolated active pillars D (in FIG. 5a 2 active pillars are shown); a gate dielectric layer 501 surrounds each active pillar D, and a gate electrode 502 fills the gap between the gate dielectric layers 501.
  • the gate dielectric layer 501 is flush with the top surface of the gate electrode 502, and the top surface of the active pillar D exceeds the top surface of the gate dielectric layer 501.
  • the portion of the active pillar D that extends beyond the gate dielectric layer 501 or the portion of the active pillar D that extends beyond the gate electrode 502 is used to form the source or drain of the semiconductor structure 50 .
  • the gate dielectric layer 501 and the gate electrode 502 sequentially annularly cover part of the active pillar D, and the remaining part of the active pillar D serves as the source or drain of the transistor.
  • the bottom of the gap between each active pillar D is filled with insulating material 504 , and the active pillars located between the insulating material 504 are used to form the drain or source of the semiconductor structure 50 .
  • the semiconductor structure further includes a buried bit line structure (not shown) at the bottom of each active pillar and a capacitor structure (not shown) at the top surface of each active pillar.
  • the gate dielectric layer at least includes an isolation layer formed of a polarization material capable of spontaneous polarization, and the isolation layer can generate an additional polarization electric field, and the polarization electric field can cause electrons or holes to It is easier to enter the charge trapping layer, so that the programming voltage and erase voltage of the semiconductor structure can be reduced, thereby providing a semiconductor device with low operating voltage, low power consumption and high reliability.
  • FIG. 6 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 6, the method for forming a semiconductor structure includes the following: step:
  • Step S601 Form a gate dielectric layer, where the gate dielectric layer includes an oxide layer, a charge trapping layer and an isolation layer stacked in sequence.
  • the isolation layer is composed of a polarizing material capable of spontaneous polarization.
  • Step S602 Form a gate electrode on the surface of the isolation layer.
  • the gate may be formed on the surface of the well region.
  • 7a to 7h are structural schematic diagrams of the semiconductor formation process provided by embodiments of the present disclosure. The detailed formation process of the semiconductor structure in the embodiment of the present disclosure will be described below with reference to FIGS. 7a to 7h.
  • the gate electrode is formed on the surface of the well region, and the well region can be formed through the following steps:
  • Step S6011 Provide a semiconductor substrate, and form a patterned photoresist layer on the surface of the semiconductor substrate.
  • a patterned photoresist layer 701 is formed on the surface of the semiconductor substrate 700.
  • the semiconductor substrate 700 provided by the embodiment of the present disclosure is a substrate doped with N-type ions or P-type ions.
  • Step S6012 Etch the semiconductor substrate through the patterned photoresist layer to form a plurality of etching trenches.
  • Step S6013 Fill each etched trench with an insulating material to form a shallow trench isolation region and a well region located between two adjacent shallow trench isolation regions.
  • the semiconductor substrate 700 is etched through the patterned photoresist layer 701 to form two etching trenches.
  • the two etching trenches are filled with insulating material to form a shallow trench isolation region 702 and
  • the well region 703 is located between two adjacent shallow trench isolation regions 702 .
  • the gate dielectric layer and the gate electrode can be formed through the following steps:
  • Step S6014 Deposit oxidation material, charge trapping material, polarization material and gate material on the surface of the well region in order from bottom to top, correspondingly forming an initial oxide layer, an initial charge trapping layer, an initial isolation layer and an initial gate electrode.
  • the oxidized material may be a high-K oxidized material, such as silicon oxide or hafnium oxide;
  • the charge trapping material may be any material with traps, such as silicon nitride;
  • the polarized material may include iron Electric oxide, ferroelectric fluoride, ferroelectric semiconductor material, doped ferroelectric oxide, polymer ferroelectric material or any combination thereof;
  • the gate material can include tungsten, cobalt, copper, aluminum, polysilicon, doped silicon , silicide, titanium nitride or any combination thereof.
  • the initial oxide layer, the initial charge trapping layer, the initial isolation layer and the initial gate can be formed through any suitable deposition process, such as chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, Atomic Layer Deposition (ALD) process, spin coating process or coating process.
  • CVD chemical vapor deposition
  • PVD Physical vapor deposition
  • ALD Atomic Layer Deposition
  • an initial oxide layer 704a, an initial charge trapping layer 705a, an initial isolation layer 706a, and an initial gate electrode 707a are sequentially formed on the surface of the well region 703.
  • Step S6015 Etch the initial gate electrode, the initial isolation layer, the initial charge trapping layer, and the initial oxide layer sequentially through a mask with a preset window to form the gate electrode, the isolation layer, the charge trapping layer, and the oxide layer.
  • the initial gate electrode 707a, the initial isolation layer 706a, the initial charge trapping layer 705a and the initial oxide layer 704a are sequentially etched through the preset mask E to form the gate electrode 707, isolation layer 706, Charge trapping layer 705 and oxide layer 704.
  • the isolation layer 706, the charge trapping layer 705 and the oxide layer 704 together constitute the gate dielectric layer 708 of the semiconductor structure.
  • the method of forming the semiconductor structure before forming the gate dielectric layer and the gate electrode, further includes: using a thermal oxidation process to form a sacrificial oxide layer on the surface of each well region to capture the surface of each well region. residual ions; and remove the sacrificial oxide layer through a wet etching process.
  • Thermal oxidation process is to place the well region in a high-temperature oxidizing atmosphere to oxidize a thin layer of silicon material on the surface of the well region into silicon dioxide.
  • Residual ions include phosphorus ions (P-) when forming an N-well or boron ions (B+) when forming a P-well.
  • the sacrificial oxide layer can improve defects on the surface of the well region, improve the formation accuracy of the initial oxide layer, and thereby improve the performance of the semiconductor structure.
  • the method of forming the semiconductor structure further includes:
  • Step S6016 Doping part of the well region with ions of a preset type to form a lightly doped drain implantation region.
  • arsenic ions or boron ions are implanted into part of the well region 703 to form a low-energy lightly doped drain implantation region 709.
  • Step S6017 Form a spacer structure on the gate dielectric layer and the sidewall of the gate; wherein a part of the spacer structure is located on the surface of the lightly doped drain implantation region.
  • the sidewall structure includes a first sidewall layer and a second sidewall layer located outside the first sidewall; step S6017 may include the following steps:
  • a first initial spacer layer and a second initial spacer layer are sequentially formed on the surface of the well region, the sidewalls of the gate dielectric layer, the sidewalls and the top of the gate.
  • the first initial spacer layer may be a silicon oxide layer or a low-K material layer, and the material of the second initial spacer layer may be an insulating material, such as silicon nitride.
  • the first initial spacer layer and the second initial spacer layer may be formed through any suitable deposition process.
  • a first initial spacer layer 710a and a second initial spacer layer 711a are sequentially formed on the surface of the well region 703, the sidewalls of the gate dielectric layer 708, the sidewalls and the top of the gate electrode 707.
  • the first initial spacer layer and the second initial spacer layer are etched respectively, and the first initial spacer layer and the second initial spacer layer located on the gate dielectric layer and the gate sidewall are correspondingly retained to form the first spacer layer. and a second spacer layer; wherein the first spacer layer is located on the surface of the lightly doped drain injection region.
  • a dry or wet etching process can be used to etch the first initial spacer layer 710a and the second initial spacer layer 711a in FIG. 7f, leaving the gate dielectric layer 708 and the gate electrode 707 correspondingly.
  • the first initial spacer layer 710a and the second initial spacer layer 711a of the sidewalls form the first spacer layer 710 and the second spacer layer 711, and the first spacer layer 710 is located in the lightly doped drain implantation region 709 surface.
  • the method of forming the semiconductor structure further includes:
  • Step S6018 Form a source electrode and a drain electrode located outside the lightly doped drain injection region.
  • ion doping is performed in the well region outside the lightly doped drain implantation region 709 to form a source electrode 712 and a drain electrode 713.
  • the method of forming the semiconductor structure further includes: forming a metal interconnection layer on the surface of the well region having the gate electrode, the source electrode and the drain electrode.
  • the process of forming the metal interconnection layer is similar to the process of forming the metal interconnection layer in the standard CMOS process, and will not be described again here.
  • the gate electrode can also be formed in the gate trench in the well region; the gate dielectric layer and the gate electrode can be formed by the following steps:
  • Step 1 Deposit oxidation material, charge trapping material and polarization material in sequence on the inner wall of the gate trench to form an initial gate dielectric layer.
  • the polarizable material may include ferroelectric oxides, ferroelectric fluorides, ferroelectric semiconductor materials, doped ferroelectric oxides, polymer ferroelectric materials, or any combination thereof.
  • Step 2 Deposit gate material in the gate trench with the gate dielectric layer to form an initial gate.
  • Step 3 Carry back the initial gate dielectric layer and the initial gate electrode to expose part of the inner wall of the gate trench to form the gate dielectric layer and gate electrode.
  • the method of forming the semiconductor structure further includes:
  • Step 4 Deposit a gate insulating layer on the surface of the gate dielectric layer and the gate electrode; wherein, the top surface of the gate insulating layer is flush with the top surface of the well region.
  • a gate electrode can also be formed around each active pillar in the well region; the gate dielectric layer and the gate electrode can also be formed by the following steps:
  • Step 1 Etch the well region to form multiple active pillars arranged in an array.
  • Step 2 Deposit oxidation material, charge trapping material and polarizing material on the sidewall of each active pillar in sequence from the inside to the outside to form an initial gate dielectric layer.
  • the polarizable material may include ferroelectric oxides, ferroelectric fluorides, ferroelectric semiconductor materials, doped ferroelectric oxides, polymer ferroelectric materials, or any combination thereof.
  • Step 3 Deposit the gate material outside the initial gate dielectric layer to form the initial gate.
  • Step 4 Carry back the initial gate dielectric layer and the initial gate electrode to expose part of the active pillars to form the gate dielectric layer and gate electrode.
  • the method for forming a semiconductor structure has a process flow similar to a standard CMOS process, and can easily and quickly prepare new semiconductor devices with low operating voltage, low power consumption and high reliability.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the components shown or discussed are coupled to each other, or directly coupled.
  • the units described above as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the semiconductor structure includes a gate dielectric layer and a gate located on the surface of the gate dielectric layer;
  • the gate dielectric layer includes an oxide layer, a charge trapping layer, and an isolation layer stacked in sequence.
  • the isolation layer is composed of a polarizable material capable of spontaneous polarization;
  • the gate electrode is located on the surface of the isolation layer.
  • the gate dielectric layer of the semiconductor structure provided by the embodiment of the present disclosure at least includes an isolation layer formed of a polarization material capable of spontaneous polarization, and the isolation layer can generate an additional polarization electric field, the polarization electric field can cause electrons or holes to It is easier to enter the charge trapping layer, and therefore, embodiments of the present disclosure can provide a semiconductor device with low operating voltage, low power consumption, and high reliability.

Abstract

本公开实施例提供一种半导体结构及其形成方法，其中，所述半导体结构包括：栅极介质层；栅极，所述栅极位于所述栅极介质层的表面；其中，所述栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层；所述隔离层由能够发生自发极化的极化材料构成。

Description

半导体结构及其形成方法
相关的交叉引用
本公开基于申请号为202210216344.0、申请日为2022年03月07日、发明名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其形成方法。
背景技术
硅-二氧化硅-氮化硅-二氧化硅-硅(Silicon-Oxide-Nitride-Oxide-Silicon，SONOS)型快闪存储器和铁电场效应晶体管(Ferroelectric Field Effect Transistor，FeFET)存储器是目前最具有前景的两种存储器。
SONOS存储器由硅衬底-隧穿氧化层-电荷存储层氮化硅-阻挡氧化层-多晶硅栅极组成，这种存储器利用电子的隧穿来进行编译，并利用空穴的注入来进行数据的擦除。SONOS存储器具有工艺简单、操作电压低和易于集成到标准互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)工艺中等优点。然而，随着半导体器件工艺节点的不断缩小，传统SONOS存储器在尺寸缩小时将导致其保持性变差，并存在严重的可靠性问题。
FeFET存储器由金属电极、铁电薄膜、金属电极、缓冲层和半导体导电通道构成，通过给栅极施加电压，调节铁电薄膜中的电偶极子的极化，使得铁电薄膜中的铁电材料具有两种不同的极化状态，进而实现数据“0”和“1”的存储。FeFET存储器具有快速的读写响应、低功耗及非破坏性读取等优点。然而，FeFET存储器在多次读写擦除操作后的可靠性明显下降。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构，包括：
栅极介质层；
栅极，所述栅极位于所述栅极介质层的表面；
其中，所述栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层； 所述隔离层由能够发生自发极化的极化材料构成。
在一些实施例中，所述极化材料包括以下至少之一：铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物和聚合物铁电材料。
在一些实施例中，所述隔离层的厚度大于1纳米。
在一些实施例中，所述氧化层为高K材料层；所述氧化层的材料包括以下至少之一：氧化铪和氧化硅。
在一些实施例中，所述电荷捕获层的材料包括：氮化硅。
在一些实施例中，所述半导体结构还包括侧墙结构，所述侧墙结构位于所述栅极介质层和所述栅极的侧壁；
其中，所述侧墙结构包括第一侧墙层和位于所述第一侧墙层外侧的第二侧墙层。
在一些实施例中，所述第一侧墙层的材料为氧化硅或者低K材料；所述第二侧墙层的材料为绝缘材料。
在一些实施例中，所述半导体结构还包括基底，所述基底内包括多个阱区，作为晶体管的源极或漏极；
其中，所述栅极介质层位于所述基底的上表面，且位于源极和漏极之间。
在一些实施例中，所述半导体结构还包括基底，所述基底内包括多个阱区，作为晶体管的源极或漏极，且每一所述阱区内具有至少一个栅极沟槽；
所述栅极位于所述栅极沟槽中，所述栅极介质层位于所述栅极与所述栅极沟槽之间；
其中，在垂直于所述基底的方向上，所述栅极的厚度小于所述栅极沟槽的厚度。
在一些实施例中，所述半导体结构还包括位于所述栅极和所述栅极介质层表面的栅极绝缘层；
其中，所述栅极绝缘层的顶表面与所述阱区的顶表面平齐。
在一些实施例中，所述半导体结构还包括多个阱区；每一所述阱区包括多个相互隔离的有源柱；
所述栅极介质层和所述栅极依次环形覆盖部分所述有源柱，剩余部分所述有源柱作为晶体管的源极或漏极。
在一些实施例中，所述栅极介质层与所述栅极的顶表面平齐，且所述有源柱的顶表面超出于所述栅极介质层的顶表面。
第二方面，本公开实施例提供一种半导体结构的形成方法，包括：
形成栅极介质层，其中，所述栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层，所述隔离层由能够发生自发极化的极化材料构成；
在所述隔离层的表面形成栅极。
在一些实施例中，所述栅极形成于阱区的表面，所述栅极介质层和所 述栅极通过以下步骤形成：
在所述阱区表面由下至上依次沉积氧化材料、电荷捕获材料、极化材料和栅极材料，对应形成初始氧化层、初始电荷捕获层、初始隔离层和初始栅极；
通过具有预设窗口的掩膜版，依次刻蚀所述初始栅极、所述初始隔离层、所述初始电荷捕获层和所述初始氧化层，形成所述栅极、所述隔离层、所述电荷捕获层和所述氧化层。
在一些实施例中，在形成所述栅极介质层和所述栅极之前，所述方法还包括：
采用热氧化工艺，在每一所述阱区的表面形成牺牲氧化层；
通过湿法刻蚀工艺，去除所述牺牲氧化层。
在一些实施例中，所述栅极形成于阱区中的栅极沟槽中；所述栅极介质层和所述栅极通过以下步骤形成：
在所述栅极沟槽的内壁依次沉积氧化材料、电荷捕获材料和极化材料，形成初始栅极介质层；
在具有所述栅极介质层的栅极沟槽中沉积栅极材料，形成初始栅极；
对所述初始栅极介质层和所述初始栅极进行回刻，暴露出部分栅极沟槽的内壁，形成所述栅极介质层和所述栅极。
在一些实施例中，所述方法还包括：
在所述栅极介质层和所述栅极的表面沉积形成栅极绝缘层；其中，所述栅极绝缘层的顶表面与所述阱区的顶表面平齐。
在一些实施例中，所述方法还包括：
依次在所述栅极介质层和所述栅极的侧壁形成第一侧墙层和第二侧墙层，所述第一侧墙层和所述第二侧墙层形成侧墙结构。
在一些实施例中，所述栅极形成于阱区中每一有源柱的周围；所述栅极介质层和所述栅极通过以下步骤形成：
在每一所述有源柱的侧壁由内至外依次沉积氧化材料、电荷捕获材料和极化材料，形成初始栅极介质层；
在所述初始栅极介质层的外侧沉积栅极材料，形成初始栅极；
对所述初始栅极介质层和所述初始栅极进行回刻，暴露出部分有源柱，形成所述栅极介质层和所述栅极。
在一些实施例中，所述极化材料包括以下至少之一：铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物和聚合物铁电材料。
本公开实施例提供的半导体结构及其形成方法，其中，半导体结构包括栅极介质层和位于栅极介质层表面的栅极；栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层；隔离层由能够发生自发极化的极化材料构成；栅极位于隔离层的表面。由于本公开实施例提供的半导体结构的栅极介质层至少包括能够发生自发极化的极化材料形成的隔离层，且隔离层能 够产生额外的极化电场，极化电场能够使得电子或者空穴更加容易地进入电荷捕获层，因此，本公开实施例可以提供一种具有低工作电压、低功耗和高可靠性的半导体器件。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的半导体结构的一种结构示意图；
图2和图3为本公开实施例提供的半导体结构的工作原理示意图；
图4为本公开实施例提供的半导体结构的另一种结构示意图；
图5a为本公开实施例提供的半导体结构的剖视图；
图5b为本公开实施例提供的半导体结构的俯视图；
图6为本公开实施例提供的半导体结构的形成方法的流程示意图；
图7a～7h为本公开实施例提供的半导体形成过程的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一 个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
由于相关技术中的SONOS存储器在工艺节点的不断缩小时，存在保持性和可靠性变差问题，且相关技术中的FeFET存储器在多次读写擦除操作后存在可靠性明显下降的问题，本公开实施例结合SONOS存储器技术和FeFET存储器技术提出一种具有低工作电压、低功耗和高可靠性的新型半导体器件。
图1为本公开实施例提供的半导体结构的一种结构示意图，如图1所示，半导体结构10包括栅极介质层101和位于栅极介质层表面的栅极102。
其中，栅极介质层101包括依次堆叠的氧化层101a、电荷捕获层101b和隔离层101c；隔离层101c由能够发生自发极化的极化材料构成。栅极102位于隔离层101c的表面。氧化层101a可以是高K材料层，高K材料层可以改善栅极介质层101的等效氧化层厚度(EOT，Effective oxide thickness)，举例来说，氧化层101a的材料可以包括以下至少之一：氧化铪(HfO 2)和氧化硅。电荷捕获层101b可以是任意一种能够捕获电子的材料层，例如为氮化硅层，也就是说，电荷捕获层101b可以由氮化硅材料构成。极化材料包括：铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物、聚合物铁电材料或其任意组合。
本公开实施例中，隔离层在垂直于基底所在平面的方向上的厚度大于1纳米。隔离层用于阻止电子在栅极与电荷捕获层之间的隧穿，辅助电子进入电荷捕获层或者离开电荷捕获层，从而可以降低半导体结构的工作电压，并改善半导体结构的保持特性和耐久性。
在一些实施例中，半导体结构的栅极可以是平面栅结构，请继续参见图1，半导体结构10还包括基底，基底内包括有源区(图1中仅示出有源区中的一个阱区)，其中，栅极介质层101位于阱区103的表面，且栅极介质层101包括由下至上依次堆叠的氧化层101a、电荷捕获层101b和隔离层101c。
本公开实施例中，阱区是对半导体衬底(例如为硅衬底)进行N型掺 杂或者P型掺杂而形成的区域，用来形成晶体管。
在一些实施例中，请继续参见图1，半导体结构10还包括侧墙结构104；侧墙结构104位于栅极介质层101和栅极102的侧壁，且侧墙结构104包括第一侧墙层104a和位于第一侧墙层104a外侧的第二侧墙层104b。
本公开实施例中，第一侧墙层的材料可以为氧化硅或者低K材料，低K材料可以改善栅极和源漏极之间的耦合寄生电容；第二侧墙层的材料可以为任意的绝缘材料，从而能够实现源极和漏极掺杂时对栅极的保护，例如，第二侧墙层的材料可以是氮化硅。
在一些实施例中，请继续参见图1，半导体结构10还包括轻掺杂漏注入区105；轻掺杂漏注入区105位于栅极介质层101底部的阱区103中。
在一些实施例中，请继续参见图1，半导体结构10还包括源极106和漏极107；源极106和漏极107分别位于轻掺杂漏注入区105的外侧的阱区中，关于栅极结构对称分布。
本公开实施例中，轻掺杂漏注入区的存在一方面为了防止随着栅极宽度和栅极所对应的沟道长度的不断减小，而产生的短沟道效应，另一方面用于减小源极和漏极之间的沟道漏电流。
在一些实施例中，请继续参见图1，半导体结构10还包括浅槽隔离区108；多个阱区103通过浅槽隔离区108相互隔离。
图2和图3为本公开实施例提供的半导体结构的工作原理示意图，下面结合图2和图3说明本公开实施例提供的半导体结构的工作原理。
如图2所示，当在栅极102上施加正工作电压Vg时，阱区103中的电子在栅极电压产生的外电场A的作用下，隧穿通过氧化层101a，进入电荷捕获层101b中，被电荷捕获层101b中的深能级陷阱捕获，进而实现编程过程。在编程前由于隔离层101c的自发极化作用，使得隔离层中的电子和空穴发生分离，在编程过程中，在外电场A的作用下，隔离层101c的极化方向逐渐与外电场A的方向一致，从而产生了极化电场B，外电场A和极化电场B共同控制阱区103中的电子隧穿进入电荷捕获层101b中。
本公开实施例中，由于隔离层的存在可以产生额外的极化电场，极化电场与栅极电压产生的外电场的方向相同，因此，极化电场可以控制帮助阱区中的电子向电荷捕获层中的跃迁，即极化电场的存在可以增强电子的隧穿能力，因此，当半导体结构包括隔离层时，编程过程的工作电压较小，耐久能力好，减小了高电压可能对隧穿层造成的损坏，同时注入的电子或空穴可以达到基底更远的距离，使得电子或空穴保留性能好，可能的漏电路径变长，一次读写的漏电少。
如图3所示，当在栅极102上施加负工作电压Vg时，电荷捕获层101b中所捕获的电子在外电场A的作用下从陷阱中逃逸，隧穿通过氧化层101a，注入到阱区103中；或者，阱区103中的空穴在外电场A的作用下隧穿通过氧化层101a，进入电荷捕获层101b中，与电荷捕获层101b中捕获的电 子复合，实现擦除过程。在擦除前由于隔离层101c的自发极化作用，使得电子和空穴发生分离，在擦除过程中，在外电场A的作用下，隔离层101c的极化方向逐渐与外电场A的方向一致，从而产生了极化电场B，外电场A和极化电场B共同控制电荷捕获层101b的电子逃逸进入阱区103中，或者，外电场A和极化电场B共同控制阱区103中的空穴注入电荷捕获层101b中，与电荷捕获层101b中捕获的电子复合。
本公开实施例中，由于隔离层的存在可以产生额外的极化电场，极化电场与栅极电压产生的外电场的方向相同，因此，极化电场可以控制电荷捕获层中的电子向阱区逃逸，或者，控制阱区中的空穴注入电荷捕获层中，即极化电场的存在可以增强电子或者空穴的隧穿能力，因此，当半导体结构包括隔离层时，栅极只需要施加一个较小的负电压即可实现擦除过程，也就是说，隔离层的存在可以降低半导体结构的擦除电压，且使得半导体结构具有更好保持力。
在一些实施例中，半导体结构的栅极还可以是掩埋栅结构，图4为本公开实施例提供的半导体结构的另一种结构示意图，如图4所示，半导体结构40包括栅极介质层401和位于栅极介质层401内的栅极402。
其中，栅极介质层401包括依次堆叠的氧化层401a、电荷捕获层401b和隔离层401c；隔离层401c由能够发生自发极化的极化材料构成；栅极402位于隔离层401c所形成的凹槽的内部。
本公开实施例中，极化材料包括：铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物、聚合物铁电材料或其任意组合。
在一些实施例中，半导体结构40还包括基底，基底内包括多个阱区403(图4中仅示出了一个阱区)，且每一阱区403内具有至少一个栅极沟槽C(图4中示出了2个栅极沟槽)；栅极402位于栅极沟槽C中，栅极介质层401位于栅极402与栅极沟槽C之间。
请继续参见图4，本公开实施例中，在垂直于基底的方向上，栅极402的厚度h1小于栅极沟槽C的厚度h2。
在一些实施例中，请继续参见图4，半导体结构40还包括位于栅极402和栅极介质层401表面的栅极绝缘层404；其中，栅极绝缘层404的顶表面与阱区403的顶表面平齐。栅极绝缘层404用于隔离掩埋于阱区403内部的栅极结构和位于阱区403表面的其它功能结构(图中未示出)。
需要说明的是，本公开实施例所提供的半导体结构的工作原理与上述实施例中具有平面栅极结构的半导体结构的工作原理类似，这里不再详细描述。
在一些实施例中，半导体结构的栅极还可以是全环栅结构，图5a为本公开实施例提供的半导体结构的剖视图，图5b为本公开实施例提供的半导体结构的俯视图，如图5a和5b所示，半导体结构50包括栅极介质层501和位于栅极介质层501所形成的凹槽内部的栅极502。
其中，栅极介质层501包括依次堆叠的氧化层501a、电荷捕获层501b和隔离层501c；隔离层501c由能够发生自发极化的极化材料构成；栅极502位于隔离层501c的表面。
本公开实施例中，极化材料包括：铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物、聚合物铁电材料或其任意组合。
在一些实施例中，半导体结构50还包括有源区(图5a中仅示出有源区中的一个阱区)；每一阱区503包括多个相互隔离的有源柱D(图5a中示出了2个有源柱)；栅极介质层501环绕每一有源柱D，栅极502填充栅极介质层501之间的间隙。
请继续参见图5a，本公开实施例中，栅极介质层501与栅极502的顶表面平齐，且有源柱D的顶表面超出于栅极介质层501的顶表面。有源柱D超出栅极介质层501的部分或者有源柱D超出栅极502的部分，用于形成半导体结构50的源极或者漏极。栅极介质层501和栅极502依次环形覆盖部分有源柱D，剩余部分有源柱D作为晶体管的源极或漏极。
在一些实施例中，每一有源柱D之间的空隙底部填充有绝缘材料504，位于绝缘材料504之间的有源柱用于形成半导体结构50的漏极或者源极。
在一些实施例中，半导体结构还包括位于每一有源柱底部的掩埋位线结构(图中未示出)和位于每一有源柱顶表面的电容结构(图中未示出)。
需要说明的是，本公开实施例所提供的半导体结构的工作原理与上述实施例中具有平面栅极结构的半导体结构的工作原理类似，这里不再详细描述。
本公开实施例提供的半导体结构，由于栅极介质层至少包括能够发生自发极化的极化材料形成的隔离层，且隔离层能够产生额外的极化电场，极化电场能够使得电子或者空穴更加容易地进入电荷捕获层，如此，可以降低半导体结构的编程电压和擦除电压，进而能够提供一种具有低工作电压、低功耗和高可靠性的半导体器件。
除此之外，本公开实施例还提供一种半导体结构的形成方法，图6为本公开实施例提供的半导体结构的形成方法的流程示意图，如图6所示，半导体结构的形成方法包括以下步骤：
步骤S601、形成栅极介质层，其中，栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层，隔离层由能够发生自发极化的极化材料构成。
步骤S602、在隔离层的表面形成栅极。
在一些实施例中，栅极可以形成于阱区的表面。图7a～7h为本公开实施例提供的半导体形成过程的结构示意图，下面结合图7a～7h说明本公开实施例中的半导体结构的详细形成过程。
本公开实施例中，栅极形成于阱区的表面，阱区可以通过以下步骤形成：
步骤S6011、提供半导体衬底，且半导体衬底表面形成有一图形化的光 刻胶层。
如图7a所示，半导体衬底700表面形成有图形化的光刻胶层701。需要说明的是，本公开实施例所提供的半导体衬底700是经过N型离子或者P型离子掺杂后的衬底。
步骤S6012、通过图形化的光刻胶层，刻蚀半导体衬底，形成多个刻蚀沟槽。
步骤S6013、在每一刻蚀沟槽中填充绝缘材料，形成浅槽隔离区和位于相邻两个浅槽隔离区之间的阱区。
如图7b所示，通过图形化的光刻胶层701刻蚀半导体衬底700，形成了两个刻蚀沟槽，在两个刻蚀沟槽中填充绝缘材料，形成浅槽隔离区702和位于相邻两个浅槽隔离区702之间的阱区703。
本公开实施例中，栅极介质层和栅极可以通过以下步骤形成：
步骤S6014、在阱区表面由下至上依次沉积氧化材料、电荷捕获材料、极化材料和栅极材料，对应形成初始氧化层、初始电荷捕获层、初始隔离层和初始栅极。
本公开实施例中，氧化材料可以是高K氧化材料，例如可以是氧化硅或者氧化铪；电荷捕获材料可以是任意一种具有捕获陷阱的材料，例如，氮化硅；极化材料可以包括铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物、聚合物铁电材料或其任意组合；栅极材料可以包括钨、钴、铜、铝、多晶硅、掺杂硅、硅化物、氮化钛或其任何组合。本公开实施例中，可以通过任意一种合适的沉积工艺形成初始氧化层、初始电荷捕获层、初始隔离层和初始栅极，例如，化学气相沉积(Chemical Vapor Deposition，CVD)工艺、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺或者涂敷工艺。
如图7c所示，在阱区703表面依次形成了初始氧化层704a、初始电荷捕获层705a、初始隔离层706a和初始栅极707a。
步骤S6015、通过具有预设窗口的掩膜版，依次刻蚀初始栅极、初始隔离层、初始电荷捕获层和初始氧化层，形成栅极、隔离层、电荷捕获层和氧化层。
结合图7c和7d所示，通过预设的掩膜版E，依次刻蚀初始栅极707a、初始隔离层706a、初始电荷捕获层705a和初始氧化层704a，形成栅极707、隔离层706、电荷捕获层705和氧化层704。其中，隔离层706、电荷捕获层705和氧化层704共同构成半导体结构的栅极介质层708。
在一些实施例中，在形成栅极介质层和栅极之前，半导体结构的形成方法还包括：采用热氧化工艺，在每一阱区的表面形成牺牲氧化层，以捕获每一阱区表面的残余离子；并通过湿法刻蚀工艺，去除牺牲氧化层。
热氧化工艺是将阱区置于高温氧化气氛中，使阱区表面的一层薄硅材 料氧化为二氧化硅。残余离子包括形成N阱时的磷离子(P-)或形成P阱时的硼离子(B+)。本公开实施例中，牺牲氧化层可以改善阱区的表面的缺陷，提高初始氧化层的形成精度，进而提升半导体结构的性能。
在一些实施例中，在形成栅极之后，半导体结构的形成方法还包括：
步骤S6016、采用预设类型的离子对部分阱区进行掺杂，形成轻掺杂漏注入区。
如图7e所示，对部分阱区703进行砷离子或硼离子注入形成了低能量的轻掺杂漏注入区709。
步骤S6017、在栅极介质层和栅极的侧壁形成侧墙结构；其中，侧墙结构的一部分位于轻掺杂漏注入区的表面。
在一些实施例中，侧墙结构包括第一侧墙层和位于第一侧墙外侧的第二侧墙层；步骤S6017可以包括以下步骤：
在阱区的表面、栅极介质层的侧壁、栅极的侧壁和顶部依次形成第一初始侧墙层和第二初始侧墙层。
第一初始侧墙层可以是氧化硅层或者低K材料层，第二初始侧墙层的材料可以是绝缘材料，例如，氮化硅。本公开实施例中，可以通过任意一种合适的沉积工艺形成第一初始侧墙层和第二初始侧墙层。
如图7f所示，在阱区703的表面、栅极介质层708的侧壁、栅极707的侧壁和顶部依次形成第一初始侧墙层710a和第二初始侧墙层711a。
分别刻蚀第一初始侧墙层和第二初始侧墙层，对应保留位于栅极介质层和栅极侧壁的第一初始侧墙层和第二初始侧墙层，形成第一侧墙层和第二侧墙层；其中，第一侧墙层位于轻掺杂漏注入区的表面。
本公开实施例中，可以采用干法或者湿法刻蚀工艺刻蚀图7f中的第一初始侧墙层710a和第二初始侧墙层711a，对应保留位于栅极介质层708和栅极707侧壁的第一初始侧墙层710a和第二初始侧墙层711a，形成第一侧墙层710和第二侧墙层711，且第一侧墙层710位于轻掺杂漏注入区709的表面。
在一些实施例中，在形成侧墙结构之后，半导体结构的形成方法还包括：
步骤S6018、形成位于轻掺杂漏注入区外侧的源极和漏极。
如图7h所示，在轻掺杂漏注入区709外侧的阱区中进行离子掺杂形成源极712和漏极713。
在一些实施例中，在形成源极和漏极之后，半导体结构的形成方法还包括：在具有栅极、源极和漏极的阱区的表面形成金属互连层。
本公开实施例中，形成金属互连层的工艺与标准CMOS工艺中形成金属互连层的过程类似，这里不再赘述。
在一些实施例中，栅极还可以形成于阱区中的栅极沟槽中；栅极介质层和栅极可以通过以下步骤形成：
步骤一：在栅极沟槽的内壁依次沉积氧化材料、电荷捕获材料和极化材料，形成初始栅极介质层。
极化材料可以包括铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物、聚合物铁电材料或其任意组合。
步骤二：在具有栅极介质层的栅极沟槽中沉积栅极材料，形成初始栅极。
步骤三：对初始栅极介质层和初始栅极进行回刻，暴露出部分栅极沟槽的内壁，形成栅极介质层和栅极。
在一些实施例中，在栅极沟槽中形成栅极和栅极介质层之后，半导体结构的形成方法还包括：
步骤四：在栅极介质层和栅极的表面沉积形成栅极绝缘层；其中，栅极绝缘层的顶表面与阱区的顶表面平齐。
在一些实施例中，栅极还可以形成于阱区中每一有源柱的周围；栅极介质层和栅极还可以通过以下步骤形成：
步骤一：刻蚀阱区，形成阵列排布的多个有源柱。
步骤二：在每一有源柱的侧壁由内至外依次沉积氧化材料、电荷捕获材料和极化材料，形成初始栅极介质层。
极化材料可以包括铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物、聚合物铁电材料或其任意组合。
步骤三：在初始栅极介质层的外侧沉积栅极材料，形成初始栅极。
步骤四：对初始栅极介质层和初始栅极进行回刻，暴露出部分有源柱，形成栅极介质层和栅极。
本公开实施例提供的半导体结构的形成过程与上述实施例中的的半导体结构类似，对于本公开实施例未详尽披露的技术特征，请参考上述实施例进行理解，这里不再赘述。
本公开实施例提供的半导体结构的形成方法，具有与标准CMOS工艺相似的工艺流程，可以简便快速地制备出具有低工作电压、低功耗和高可靠性的新型半导体器件。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开实施例的一些实施方式，但本公开实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开实施例的保护范围之内。因此，本公开实施例的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供的半导体结构及其形成方法，其中，半导体结构包括栅极介质层和位于栅极介质层表面的栅极；栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层；隔离层由能够发生自发极化的极化材料构成；栅极位于隔离层的表面。由于本公开实施例提供的半导体结构的栅极介质层至少包括能够发生自发极化的极化材料形成的隔离层，且隔离层能够产生额外的极化电场，极化电场能够使得电子或者空穴更加容易地进入电荷捕获层，因此，本公开实施例可以提供一种具有低工作电压、低功耗和高可靠性的半导体器件。

Claims (20)

  1. 一种半导体结构，包括：
    栅极介质层；
    栅极，所述栅极位于所述栅极介质层的表面；
    其中，所述栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层；所述隔离层由能够发生自发极化的极化材料构成。
  2. 根据权利要求1所述的半导体结构，其中，所述极化材料包括以下至少之一：铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物和聚合物铁电材料。
  3. 根据权利要求1所述的半导体结构，其中，所述隔离层的厚度大于1纳米。
  4. 根据权利要求1所述的半导体结构，其中，所述氧化层为高K材料层；所述氧化层的材料包括以下至少之一：氧化铪和氧化硅。
  5. 根据权利要求1所述的半导体结构，其中，所述电荷捕获层的材料包括：氮化硅。
  6. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括侧墙结构，所述侧墙结构位于所述栅极介质层和所述栅极的侧壁；
    其中，所述侧墙结构包括第一侧墙层和位于所述第一侧墙层外侧的第二侧墙层。
  7. 根据权利要求6所述的半导体结构，其中，所述第一侧墙层的材料为氧化硅或者低K材料；所述第二侧墙层的材料为绝缘材料。
  8. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括基底，所述基底内包括多个阱区，作为晶体管的源极或漏极；
    其中，所述栅极介质层位于所述基底的上表面，且位于源极和漏极之间。
  9. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括基底，所述基底内包括多个阱区，作为晶体管的源极或漏极，且每一所述阱区内具有至少一个栅极沟槽；
    所述栅极位于所述栅极沟槽中，所述栅极介质层位于所述栅极与所述栅极沟槽之间；
    其中，在垂直于所述基底的方向上，所述栅极的厚度小于所述栅极沟槽的厚度。
  10. 根据权利要求9所述的半导体结构，其中，所述半导体结构还包括位于所述栅极和所述栅极介质层表面的栅极绝缘层；
    其中，所述栅极绝缘层的顶表面与所述阱区的顶表面平齐。
  11. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括多个阱区；每一所述阱区包括多个相互隔离的有源柱；
    所述栅极介质层和所述栅极依次环形覆盖部分所述有源柱，剩余部分 所述有源柱作为晶体管的源极或漏极。
  12. 根据权利要求11所述的半导体结构，其中，所述栅极介质层与所述栅极的顶表面平齐，且所述有源柱的顶表面超出于所述栅极介质层的顶表面。
  13. 一种半导体结构的形成方法，所述方法包括：
    形成栅极介质层，其中，所述栅极介质层包括依次堆叠的氧化层、电荷捕获层和隔离层，所述隔离层由能够发生自发极化的极化材料构成；
    在所述隔离层的表面形成栅极。
  14. 根据权利要求13所述的方法，其中，所述栅极形成于阱区的表面，所述栅极介质层和所述栅极通过以下步骤形成：
    在所述阱区表面由下至上依次沉积氧化材料、电荷捕获材料、极化材料和栅极材料，对应形成初始氧化层、初始电荷捕获层、初始隔离层和初始栅极；
    通过具有预设窗口的掩膜版，依次刻蚀所述初始栅极、所述初始隔离层、所述初始电荷捕获层和所述初始氧化层，形成所述栅极、所述隔离层、所述电荷捕获层和所述氧化层。
  15. 根据权利要求14所述的方法，其中，在形成所述栅极介质层和所述栅极之前，所述方法还包括：
    采用热氧化工艺，在每一所述阱区的表面形成牺牲氧化层；
    通过湿法刻蚀工艺，去除所述牺牲氧化层。
  16. 根据权利要求13所述的方法，其中，所述栅极形成于阱区中的栅极沟槽中；所述栅极介质层和所述栅极通过以下步骤形成：
    在所述栅极沟槽的内壁依次沉积氧化材料、电荷捕获材料和极化材料，形成初始栅极介质层；
    在具有所述栅极介质层的栅极沟槽中沉积栅极材料，形成初始栅极；
    对所述初始栅极介质层和所述初始栅极进行回刻，暴露出部分栅极沟槽的内壁，形成所述栅极介质层和所述栅极。
  17. 根据权利要求16所述的方法，其中，所述方法还包括：
    在所述栅极介质层和所述栅极的表面沉积形成栅极绝缘层；其中，所述栅极绝缘层的顶表面与所述阱区的顶表面平齐。
  18. 根据权利要求13所述的方法，其中，所述方法还包括：
    依次在所述栅极介质层和所述栅极的侧壁形成第一侧墙层和第二侧墙层，所述第一侧墙层和所述第二侧墙层形成侧墙结构。
  19. 根据权利要求13所述的方法，其中，所述栅极形成于阱区中每一有源柱的周围；所述栅极介质层和所述栅极通过以下步骤形成：
    在每一所述有源柱的侧壁由内至外依次沉积氧化材料、电荷捕获材料和极化材料，形成初始栅极介质层；
    在所述初始栅极介质层的外侧沉积栅极材料，形成初始栅极；
    对所述初始栅极介质层和所述初始栅极进行回刻，暴露出部分有源柱，形成所述栅极介质层和所述栅极。
  20. 根据权利要求13至19任一项所述的方法，其中，所述极化材料包括以下至少之一：铁电氧化物、铁电氟化物、铁电半导体材料、掺杂型铁电氧化物和聚合物铁电材料。
PCT/CN2022/088945 2022-03-07 2022-04-25 半导体结构及其形成方法 WO2023168807A1 (zh)

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