TW520560B - Use of ALN as a copper passivation layer and thermal conductor, and its method of formation - Google Patents

Use of ALN as a copper passivation layer and thermal conductor, and its method of formation Download PDF

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Publication number
TW520560B
TW520560B TW090108691A TW90108691A TW520560B TW 520560 B TW520560 B TW 520560B TW 090108691 A TW090108691 A TW 090108691A TW 90108691 A TW90108691 A TW 90108691A TW 520560 B TW520560 B TW 520560B
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Taiwan
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copper
layer
conductor
item
connection structure
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TW090108691A
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English (en)
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Allen Mcteer
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Micron Technology Inc
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

520560 A7 經濟部智慧財產局員工消費合作社印製 --------- —___五、發明說明(2 ) =連接結構中之擴散能破壞在㈣板中形成之有源裝置 口电晶體或電容。此外,銅對中間層介電質特別是叫之 黏著力通常不佳且金屬對底層基板材料之黏著力必須極佳 以形成可信賴的連接結構。更進一步地,銅在低溫容易氧 化且具有不佳之對基板黏著力。銅亦與大部份矽鋁化物具 低反應溫度且對由反應離子蝕刻之圖案要求高溫。 在企圖克服銅連接器產生之這些缺點中,已做的努力主 要在詳加討論連接結構應用之銅中氧化機構之了解。例如 ,w·A·藍福德(1^11£01:(1)研究離子注入作爲鈍化銅膜之有效 方法 1福德,W.A·等人在薄固態膜中之「以摻雜Ai或Mg 低溫鈍化銅」234_41(1995)。藉分析銅之成長機構,藍福德 觀察到氧化速率可藉只添加極小濃度之摻雜劑如A1或Mg 至銅中減少。 相似地,注入硼(B)之銅的抗腐餘性,特別是其機構已由 丁(P.J· Ding)等人在「注入B之銅的抗腐蝕性之引起機械之 研究」B 85核子儀器方法物理研究(NUCL. INSTRUML METHODS· PHYS· RES.,)260-63( 1994)中研究。藉研究注入 删之銅及銅氧化物(Cu2〇)之氧化,丁發現注入硼之Cu2〇的 氧化速率與注入硼之銅金屬(Cu)—樣慢。 克服銅連接缺點之其他方法還包括在連接形成之前立刻 刮除麵層以移除銅氧化物,或使用障壁層鈍化銅表面。例 如,美國專利第4,987,750號敘述使用氮化鈦(TiN)、鎢(W) 、氮化鎢(WN)、氮化锆(ZrN)、碳化鈦(TiC)、碳化鐫(Wc) 、姮(Ta)、氮化鈕(TaN)或鎢化鈦(TiW)作爲銅之障壁層。 -5- (請先閱讀背面之注意事項再本頁) ¾ |<太 . ' --線· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 520560 五、發明說明(4 膨脹之抑制氧化成長層之銅連接結構及形成這樣之銅連接 結構之簡單方法亦有需求。 發明概要 發明提供包括A1N障壁層之銅連接結構,其提供增強 4熱傳導率。本發明亦提供用A1N障壁層於銅上提供銅表 面(鈍化,藉增加金屬層及鍵結結構間之接觸黏著力進一 步增強鍵結降伏強度。 本發明足這些及其他優點及特徵由下面提供附圖之本發 明詳述將更清楚地了解。 圖式簡述 圖1爲描繪根據本發明之較佳具體實施例及方法銅連接 結構之形成之傳統記憶體DRAM裝置之剖視圖。 圖2爲在圖1所示隨後之加工階段圖1之銅連接結構之剖 視圖。 圖3爲在圖2所示隨後之加工階段圖1之銅連接結構之剖 視圖。 圖4爲在圖3所示隨後之加工階段圖1之銅連接結構之剖 視圖。 經濟部智慧財產局員工消費合作社印製 圖5爲在圖4所示隨後之加工階段圖1之銅連接結構之剖 視圖。 圖έ爲在圖5所示隨後之加工階段圖1之銅連接結構之剖 視圖。 圖7爲在圖6所示隨後之加工階段圖1之銅連接結構之剖 視圖。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 520560 A7 k發明說明(7 ) j形成圖案之後’最初開口 27(圖2)存在隨後氧化物蚀刻 〈光阻層26。之後圖2之結構經蚀刻、移除光阻層%,且如 圖3中所示,通過第一絕緣層24之接觸開口 4〇形成。圖3之 接觸開口懈刻至接觸開口⑽接觸基㈣之源極或没極區 域16 〇 其次,接觸開口 40充填導體材料如接雜之多晶碎、姑、 氮化欽(TiN)、鎮(W)、氮化鎢、銅、紹或舶,其平面化至 或接近第-絕緣層24之平面表面,以形成检或填充物5〇, 如圖4中所描述。雖然可用任何導體材料充填栓5(),爲了簡 化,栓50稱爲多晶梦栓50。之後多晶珍检5〇異向性蚀刻直 到頂表面凹下至與第一絕緣層24相同之水平。 第一絕緣層25(圖5)可爲例如氧化矽(Si〇」、四乙基正磷 酸鹽(TEOS)、硼磷矽酸鹽玻璃(BpsG)、硼矽酸鹽(bsg)、 磷矽酸鹽玻璃(PSG)或低介電材料如SILK、FLARE或黑鑽 石,隨後沉積在第一絕緣層24及聚矽酸5〇之上表面。再一 次,使用如用於形成通過第一絕緣層24之接觸開口 4〇(圖3) 足相同製造技術,形成通過第二絕緣層25之窗41(圖5)。 形成窗41(圖5)之後,薄障壁層52(圖6)在多晶矽栓5〇及第 二絕緣層25上藉CVD、PVD、濺鍍或蒸發至约6〇至約2〇〇埃 之厚度形成。障壁層52之較佳材料爲難熔金屬化合物如難 熔金屬化合物(例如TiN或HfN)、難熔金屬碳化物(例如Tic 或WC)、或難溶金屬硼化物(例如TiB或m〇b)。然而,必須 注意儘管障礙層52之較佳材料包括寬範圍之金屬化合物, 鈥石夕化物(TiSi2)並非較佳因爲鈥梦化物之梦與隨後在障壁 (請先閱讀背面之注音?事項再_本頁) . 線· 經濟部智慧財產局員工消費合作社印製 -10- 520560 A7 --- B7 五、發明說明(8) 層52之頂部上形成之銅(圖7)反應。如此,障壁層52之金屬 化合物必須抗抗銅之擴散,且儘管亦可使用非難熔金屬作 障壁層52,難熔金屬仍然爲較佳之材料。如技藝界中所知 ,障壁層52必須亦抑制栓5〇之矽或金屬原子之擴散,.同時 才疋供栓50及障壁層52間及隨後沉積之銅(圖7)及障壁層52 間低阻抗及低接觸阻力。 現在參照圖7,連接銅層55沉積在障壁層52上。使用銅層 55以形成金屬線連接種種形成在基板以上之裝置。障壁層 52防止銅層55弋銅的擴散,且如上面之解釋,銅良好地黏 著至卩早壁層52。連接銅層55之黏著力對可靠積體電路之製 造極重要。其次,蝕刻銅層55形成銅栓或導體56(圖8)。在 本發明之杈佳具體實施例中,金屬層55(圖7)藉化學機構拋 光(CMP)或熟知之RiE乾蝕刻方法蝕刻。在化學機械拋光中 ’使用研磨物拋光移除銅層55之頂表面且障壁層52之水平 部份至或接近第二絕緣層25之平面表面。此一方法,障壁 層52及銅栓56之頂表面均勻跨過基板之整個表面,如圖8 所描述。如此之化學機械拋光法產生極平之表面,這在製 造高密度多階積體電路中非常重要。 在完成拋光過程時,AlxNy鈍化層6〇(圖9)(此處x&y可爲 相同或不同)在銅栓56及第二絕緣層25之上表面上形成,故 銅連I矣結構100(圖9)之形成可完成。爲了簡化,此應用中 AlxNy鈍化層60將標記爲ΑιΝ鈍化層6〇。因此,銅連接結構 100包括多晶矽(或其他導體)栓5〇、障壁層52、銅栓56&A1N 鈍化層60。 -11 - 本紙張尺度_巾_家鮮(CNS)A4 ^(210x 297 ^) (請先閱讀背面之注意事項再填寫本頁) --線· 經濟部智慧財產局員工消費合作社印製 520560 A7 B7 五、發明說明(9) A1N鈍化層60(圖9)可例如藉使用電漿、反應性濺鍍或傳 統化學氣相沉積沉積以形成跨越基板12之連續且平滑之 A1N層,其包括銅栓56及第二絕緣層25之上表面。A1N鈍化 層60之厚度在約100埃至約1000埃之範圍内。以約300埃較 佳。A1N亦具有良好之熱膨脹係數(2.6x10 e(-6))。高熔點 (2400°C)及極高之熱傳導率(1.5 W/cmK)。A1N鈍化層60具 有輻射大量之熱以防止半導體基板及銅連接結構100中溫 度之上升的額外優點。如此,當鈍化銅之時,A1N層亦作 爲銅連接結構100之熱傳導介電障壁層。 更進一步地,雖然A1N純化層已敘述爲相關銅之純化及 熱傳導層,A1N亦構成使用其他冶金學之熱消散路徑且本 發明不限於使用A1N層作爲銅之熱導體。如此,A1N層亦可 作爲相接觸之其他金屬及其相關合金如铭、金、銀、鶴或 砷化鎵等等之熱消散路徑,這些金屬在種種金屬化設計中 作爲電導體。 爲促進A1N鈍化層之形成及隨後銅之鈍化,銅栓56之表 面可在A1N鈍化層形成前清潔及/或預處理。如此,若使用 就地清潔技術,可使貴重氣體如氬或氖清除任何銅氧化物 或任何其他殘留例子如鋁氧化物或乾淤漿,在A1N鈍化層 形成之前在銅栓之銅表面上形成。另一方面,外加技術如 濕化拿蝕刻可用於在A1N層形成之前預處理銅表面。 雖然只有一種銅連接結構100顯示於圖9中,事實上在基 板12上形成之任何數目之這類銅連接結構對熟諳此藝者將 顯而易見。 -12- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再^寫本頁) 士 -丨線· 經濟部智慧財產局員工消費合作社印製 520560 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(10) - 雖然圖9亦描述只具一個以A1N層鈍化之銅栓的銅連接 結構’必須了解任何數目具有其相符Ain層之這類銅栓可 根據裝置之特定要求形成。例如,如圖1 〇所描述,二銅栓 56、56a可在多晶矽(或其他導體)5〇上形成,銅栓56a鄰接且 在銅栓56之頂郅上。參照圖5-9於上面敘述之製造銅栓56之 相同加工步驟應用於製造銅栓56&。依此,銅栓56a首先通 過第二絕緣層25a(圖10)形成,此絕緣層依次在ain鈍化層 60(圖9)之頂部形成。其次,Α1χΝ/4化層60a(圖10)(此處X 及y可相同或不同)在銅栓56a及第二絕緣層25a上形成,故 可完成銅連接結構1〇〇(圖1〇)之形成,其現在含有二個藉二 A1N層鈍化之銅栓。可應用額外之步驟提供銅連接結構丨〇〇 及基板12之源極或没極區域16間之電接觸。必須注意雖然 圖10描述二個銅栓56、56a彼此相鄰,大部份藉其相符ain 層純化之銅栓不需要相鄰,只要多階連接系統之操作電路 可完成。 可形成額外連接層及相關介電層以產生由銅栓56a及障 壁層52a至銅栓56、障壁層52與多晶矽栓50及向下至基板12 之源極或没極區域16之操作電路。必須注意雖然氮化銘爲 熱導體’亦爲介電材料。因此,爲產生多階連接之操作電 路,熟諳此藝者將了解必須在A1N層製造小接觸開口讓銅 栓56、56a及高水平之金屬化路徑間進一步之電子連接。 進一步地,本發明不限於特定形式之連接結構,但亦可 與任何銅連接結構如導線、TAB、C4或凸起、導體黏著劑 或類似物使用。如此,儘管本發明已參照連接鋼導體之 -13 - 本紙張尺度適用中國國家標準(CNS)A4規格m〇 X 297公髮) ---- (請先閱讀背面之注意事項再靖寫本頁) 士 訂· 丨線· 520560 A7 B7 五、發明說明(11) 層60(圖9-10),A1N層60可進一步連接至鍵結墊及/或外部熱 路徑例如外部熱槽。 雖然本發明亦敘述爲連接通過導體栓之記憶體單元之活 化區之銅栓,應了解本發明不限於銅栓,但亦可與多階連 接系統之銅層金屬化以及其他導體栓與金屬化層使用。 A1N層作爲多階連接銅線之熱導體及鈍化層,可用與沉積 A1N層60、60a所應用且相關銅連接結構100(圖1-10)之形成 所解釋相似之方法沉積。 典型之處理器基系統400包括記憶體線路448,如DRAM ,其含有根據本發明描述於圖11之銅連接結構。處理器系 統,如電腦系統,通常包括一個中央處理器單元(CPU)444 ,如微處理器、一個數位信號處理器或其他程式數位邏輯 裝置,其透過匯流排452與輸入/輸出(I/O)裝置446溝通。記 憶體448透過匯流排452與系統溝通。 在電腦系統之情況中,處理器系統可包括週邊裝置如軟 碟機454及光碟機(CD ROM)456,其亦透過匯流排452與 CPU 444溝通。記憶體448以構造成積體電路較佳,其包括 如前面相關圖1-10敘述形成之銅連接結構。記憶體448可與 處理器如CPU 444結合在單一積體電路中。 雖然上面敘述之例示具體實施例指出一種銅連接結構, 應了解本發明打算使用多個銅連接結構且不受描述具體實 施例之限制。因此,上面之敘述及圖式僅考慮描述完成本 發明之特徵及優點的例示具體實施例。可對特定製程條件 及結構修正或取代而不達背本發明之精神及範圍。因此, -14- 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) (請先閱讀背面之注意事項再Wk本頁) m. A- 經濟部智慧財產局員工消費合作社印製 520560 A7 B7 五、發明說明( 12 本發明不被考慮受前面之敘述及圖式限制 申請專利範圍之限制。 但只藉附上之 (請先閱讀背面之注意事項再靖寫本頁) 丨線· 經濟部智慧財產局員工消費合作社印製 -15- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)

Claims (1)

  1. 520560 六、申請專利範圍 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 1· 一種銅連接結構,其提供半導體基板之電子連接,該銅 連接結構包括: 一個導體栓; 一個與該導體栓電子上連接之銅導體; 一個在該銅導體上表面部份上形成且成爲基板上一層 連續層之氮化鋁層;及 土 v個鍵結墊及連接該氮化鋁層之外部熱消散路徑。 2·如申請專利範圍第丨項之銅連接結構,其中該氮化鋁層連 接至該鏈結塾。 3·如申請專利範圍第丨項之銅連接結構,其中該氮化鋁層連 接至該外部熱消散路徑。 4·如申請專利範園第丨項之銅連接結構,其中該銅導體爲在 该導體栓上形成之銅栓且進一纟包括在該導體才全及該銅 導體間形成之障壁層。 5·如申請專利範圍第丨項之銅連接結構,其中該導體栓連接 至該基板之活化區。 6·如申請專利範圍第丨項之銅連接結構,其中該銅導體由元 素銅形成。 7.如申請專利範圍第丨項之銅連接結構,其中該氮化鋁層作 爲該銅導體之熱消散路徑。 8·如申請專利範圍第丨項之銅連接結構,其中該氮化鋁層鈍 化該銅導體之上表面。 9.如申請專利範圍第1項之銅連接結構,其中該氮化鋁層之 厚度在約100埃至1000埃之範圍内。
    訂 線 -16- 本紙張尺度顧+關家標準(CNS)/U規格(21Q x 297公爱- 520560
    六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 1 〇 ·如申請專利範圍第1項之銅連接結構,其中該氮化铭層之 厚度約爲300埃。 曰 U·如申請專利範圍第1項之鋼連接結構,其中該導體拴由選 自下列各材科形成:多晶矽、鈷、氮化鈦、鎢、氮化鎢 、銅、鋁及鉑。 12. 如申請專利範圍第4項之銅連接結構,其中該障壁層包括 難溶金屬化合物。 13. 如申凊專利範圍第12項之銅連接結構,其中該難熔金屬 化合物係選自難熔金屬氮化物、難熔金屬碳化物及難熔 金屬硼化物。 14·如申請專利範圍第1項之銅連接結構,其中該銅連接結構 爲金屬化層之部份。 15· —種在半導體基板上提供電子連接之連結結構,該連接結 構包括: 一個導體栓; 一個與該導體拴電子連接之導體;及 一個在該導體之上表面部份上形成之氮化鋁層,其提 供該導體之熱消散路徑。 16·如申請專利範圍第15項之連接結構,其中該導體栓連接 至該基板之有源區。 17·如申請專利範圍第1 5項之連接結構,其中該氮化鋁之厚 度在約100埃至1〇〇〇埃之範圍内。 18.—種積體電路之銅連接結構,其包括: 一層銅層;及 -17- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) (請先閱讀背面之注意事項再本頁) 士 · -線· 520560
    、申請專利範圍 一層在該銅層之上表面部份上形成之氮化鋁層。 19·如申請專利範圍第18項之銅連接結構,其尚包括與該銅 層接觸之導體。 20.如申請專利範圍第丨9項之銅連接結構,其尚包括在該銅 層及該導體間形成之導體障壁層。 21·如申請專利範圍第19項之銅連接結構,其中該銅層形成 至少部份之該積體電路之金屬化層。 22· —種形成提供電子連接至基板之銅連接結構之方法,其 包括下列步驟: 开> 成一個進入該基板第一絕緣層之第一接觸開口; 形成一個在該第一接觸開口中之導體栓; 开> 成一個在該導體栓及該第一絕緣層上之第二絕緣層; 形成一個在該第二絕緣層中之第二接觸開口; 形成一個在該第二接觸開口中之障壁層; 形成一個在該障壁層上之銅導體;及 形成一個在該銅導體之上表面部份上之氮化鋁層,該 氮化銘層純化該銅導體之上表面部份。 23. 如申請專利範圍第22項之方法’其尚包括化學機械抛光 經濟部智慧財產局員工消費合作社印製 1請先閲讀背面之注意事頊再 15k本 ί線 該銅層及該障壁層之步驟。 24. 如申請專利範圍第22項之方法,其尚包括在形成該氮化 銘層清潔該銅導體之上表面部份的步驟。 &如申請專利範圍第22項之方法,其中;;氮化銘層藉沉積 至約300埃之厚度形成。 、 26.如申請專利範圍第22項之方*,其切成減化紹層之 本紙張尺度適用中國國家標準(CNS)A4規格(210 X -18- 520560 A8 B8 C8 D8 、 In 經濟部智慧財產局員工消費合作社印製 申請專利範圍 步驟包括沉積過程。 27.如申凊專利範圍第22項之方法,其中形成該氮化鋁層之 步驟包括濺鍍過程。 28·如申請專利範圍第22項之方法,其中該障壁層由難熔金 屬化合物形成,該化合物選自難熔金屬氮化物、難熔金 屬碳化物及難熔金屬硼化物。 29.—種形成提供半導體裝置電子連接結構之方法,其包括: 形成一個在該裝置絕緣層中之接觸開口; 在該接觸開口中沉積一種導體;及 形成一層在該導體上表面部份之氮化鋁層,其提供該 導體一個熱消散路徑。 30·如申請專利範圍第29項之方法,其尚包括在該沉積導體 步驟之前在該接觸開口沉積障壁層之步驟。 31.如申請專利範圍第29項之方法,其尚包括在形成該氮化 銘層之前清潔該導體上表面部份之步驟。 32·如申請專利範圍第29項之方法,其中該氮化鋁層藉沉積 至約300埃之厚度形成。 33·如申請專利範圍第29項之方法,其中該形成氮化鋁層之 步驟包括沉積過程。 34·如申請專利範圍第29項之方法,其中該形成氮化鋁層之 步驟包括滅鍍過程。 35.如申請專利範圍第29項之方法,其中該導體係選自下列 各物:鋁、金、銀、鎢及銅。 36· —種積體電路結構,其包括: 19- 本紙張尺度適用中國國豕標準(CNS)A4規格(21〇 X 297公釐) 520560
    六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 一片基板; 一個包括在基板上之-個間及―個_㈣排列之源 極/汲極區域之電晶體; 、個棱供私子連接至至少一個該源極/汲極區域之銅 連接結構,其包括-個連接至該基板之源極/汲極區域之 導體栓;一個提供在該導體栓頂部之銅導體;及一個在 孩銅導體上表面部份上形成之氮化鋁層。 37·如申請專利範圍第36項之結構,其尚包括形成在該導體 栓及該銅導體間之障壁層。 38·如申請專利範圍第36項之結構,其中該氮化鋁層鈍化該 銅導體之^ t表面部份。 39·如申請專利範圍第36項之結構,其中該氮化鋁層作爲該 銅導體之熱消散路徑。 40·如申請專利範圍第36項之結構,其中該氮化鋁層連接至 一個鍵結墊。 41·如申請專利範圍第36項之結構,其中該氮化鋁層連接至 一個外部熱消散路徑。 42·如申請專利範圍第36項之結構,其中該氮化鋁層之厚度 在約100埃至1〇〇〇埃之範圍内。 43·如申叫專利範圍第3 6項之結構,其中該氮化鋁層之厚产 約300埃。 又 44·如申請專利範圍第36項之結構,其中該導體拴由下列各 材料形成:多晶矽、鈷、氮化鈦、鎢、氮化鎢、銅、叙 及銘。 (請先閲讀背面之注意事項再本頁) 太 -線· -20- 本紙張尺度適用中國國家標準(CNS}A4規格(ϋ〇 x 297公爱) 520560 A8 B8 C8 D8 六、申請專利範圍 45·如申叫專利範圍弟3 7項之結構,其中該障壁 卞土嘈包括一種 難熔金屬化合物。 46.如申請專利範圍第45項之結構,其中該難熔金屬化人物 係由難熔金屬氮化物、難熔金屬碳化物及難口 奋i屬棚化 物 47· — 括: 一層銅層;及 種含有一個銅連接結構之積體電路,該銅連接結構包 經濟部智慧財產局員工消費合作社印製 一層形成在該銅層上之氮化鋁。 48·如申請專利範圍第47項之積體電路, 層之導體栓。 49·如申請專利範圍第48項之積體電路, 銅層及該導體栓間之導體障壁層。 50.如申請專利範圍第47項之積體電路, 少部份該積體電路之金屬化層。 51·如申請專利範圍第47項之積體電路, 爲該銅層之熱消散路徑。 52·如申請專利範圍第47項之積體電路, 化該銅層。 53· —種含有一個連接結構之積體電路, 一層導體層;及 一層形成在該導體層上之氮化。 54.如申請專利範圍第5 3項之積體電路, 層之導體栓。 其尚包括接觸該銅 其尚包括形成在該 其中該銅層形成至 其中該氮化鋁層作 其中該氮化鋁層純 該連接結構包括: 其尚包括接觸導體 21 - 私紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 520560 A8 B8 C8 D8 申請專利範圍 55. 如申請專利範圍第53項之積體電路,其中該層氮化鋁作 爲熱消散路徑。 56. 如申請專利範圍第53項之積體電路,其尚包括形成在該 導體層及該導體栓間之導體障壁層。 57. 如申請專利範圍第53項之積體電路,其中該導體層形成 至少部份該積體電路之金屬化層。. 請 先 閱 讀 背 S 之 注 意 事 項
    經濟部智慧財產局員工消費合作社印制衣 -22- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
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* Cited by examiner, † Cited by third party
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CN106463396B (zh) * 2014-02-05 2020-03-10 应用材料公司 防止铜扩散的电介质/金属阻挡体集成

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KR100652120B1 (ko) 2006-11-30
US7679193B2 (en) 2010-03-16
US20070164442A1 (en) 2007-07-19
US20020175362A1 (en) 2002-11-28
GB2378040B (en) 2004-10-13
JP2003530694A (ja) 2003-10-14
US20070042596A1 (en) 2007-02-22
WO2001078141A2 (en) 2001-10-18
KR20030030989A (ko) 2003-04-18
US7205223B2 (en) 2007-04-17
DE10196065T1 (de) 2003-04-03
US7061111B2 (en) 2006-06-13
GB0223484D0 (en) 2002-11-13
DE10196065B3 (de) 2015-04-16
GB2378040A (en) 2003-01-29
AU2001251504A1 (en) 2001-10-23

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