A7 __B7 五、發明説明（1 ) 本發明係有關半導體電路製程，特別係有關一種在 基底與導體層間形成電性連接（接觸）之方法，更有關使用 選擇性成長技術以形成鎮栓塞接觸之製程。 半導體積體電路係由形成於矽基底（或井）上/内之數 以百萬計主動元件所組成。主動元件係連接在一起，以 形成功能性電路與裝置。這些元件係以接觸與多層内連 接而連接在一起。在第1A圖中係顯示出習知多層内連接 結構100之剖面圖。内連接結構一般具有第一金屬化或 内連接層102(—般為鋁合金或鎢），第二金屬化層1〇4， 有時甚至有第三或第四金屬化層。内層介電物 106(ILDS)，如二氧化矽，係將不同金屬層與矽基底或井 1 〇 8將進行電性絕緣。不同内連接層之間的電性連接係經 由形成於ILD106内之金屬通孔（via)u〇而達成。 同樣地，金屬接觸112係電性連接内連接層與形成 於井108内之元件。金屬通孔11〇與接觸112，往後將寫 為通孔（via)，一般係填滿鎢114，且具有氮化鈦阻障層 16氮化鈦阻障層116提供鶴金屬114之附著層。這是 因為錄對如氧化物’金屬，梦與魏物等材質呈現不好 的附著性。 如第1B圖所示，在習知鎢栓塞製程中阻障層ιι6 係覆蓋接觸洞114與絕緣層表面。其次，鎮係全面覆蓋 (Manket)沉積於接觸㈤⑴内及絕緣層表面上層然後 被回蝕刻。在小尺寸接觸洞或高縱橫比洞中，鎢層114A7 __B7 V. Description of the invention (1) The present invention relates to a semiconductor circuit manufacturing process, and in particular relates to a method for forming an electrical connection (contact) between a substrate and a conductor layer, and more particularly to a process using selective growth techniques to form a ball plug contact . Semiconductor integrated circuits are made up of millions of active components formed on / in a silicon substrate (or well). Active components are connected together to form functional circuits and devices. These components are connected by contact and multilayer interconnections. A cross-sectional view of a conventional multilayer interconnect structure 100 is shown in FIG. 1A. The interconnect structure generally has a first metallization or interconnect layer 102 (typically aluminum alloy or tungsten), a second metallization layer 104, and sometimes even a third or fourth metallization layer. Inner layer dielectric 106 (ILDS), such as silicon dioxide, is to electrically insulate different metal layers from the silicon substrate or well 108. The electrical connection between the different interconnect layers is achieved via metal vias u0 formed in the ILD106. Similarly, the metal contact 112 electrically connects the interconnect layer with a component formed in the well 108. The metal through hole 11 and the contact 112 will be written as a via in the future. It is generally filled with tungsten 114 and has a titanium nitride barrier layer 16 and a titanium nitride barrier layer 116 to provide an adhesion layer for the crane metal 114. . This is because the recording shows poor adhesion to materials such as oxide ’metals, dreams and Wei Wu. As shown in FIG. 1B, in the conventional tungsten plug process, the barrier layer ι6 covers the contact hole 114 and the surface of the insulating layer. Secondly, Manket was deposited in the contact pads and on the surface of the insulation layer and then etched back. In small contact holes or high aspect ratio holes, the tungsten layer 114
B7 五、發明説明（2) 係形成影響可靠度且造成問題之"鑰匙洞（keyhole)"。此 外，當接觸洞直徑變小時，附著層116會佔去更多空間， 而使得縱橫比更高，並使"鑰匙洞”之問題更加嚴重。同 時，在一些小接觸直徑下，接觸洞側壁上之附著層將不 被使用，因其佔去太多空間且造成"鑰匙洞"鶴之問趣。 而金屬化通孔110與112之問題在於氮化鈦附著層 係由濺渡法所形成。濺渡製程一般呈現不好的步階覆蓋 118，如第1A圖所示。不好的步階覆蓋將導致内連接結 構之可靠性（電路開路）與性能（電阻增加）之問題。當減少 通孔尺寸以得到更高密度電路時，步階覆蓋將變得更 差，並達無法接受之程度。當形成具有垂直側壁之小尺 寸通孔時，此問題將更為複雜。只能在通孔之縱橫比小 於3.0時，才能可靠地使用濺渡法所形成之氮化鈦阻障 層。濺渡法所形成之氮化鈦阻障層將不適用於縱橫比大 於4.0之未來ULSI電路。 經濟部中央梯準局員工消费合作社印繁 化學氣相沉積法（CVD)氮化鈦附著層可視為取代濺 渡法所形成之氮化鈦阻障層。比起濺渡法製程，CVD製 程一般展現較好步階覆蓋。不幸的是，CVD氮化鈦需要 TiCLj高溫製程（600 °〇。如此高溫製程係不適用於多層金 屬化架構中之某些層。此外，由TiCl4之氣可能併入於阻 障層中，而影举其品質。甚而，CVD氮化鈦需要高成本 與複雜設備。 此外’也可使用矽化鎢附著層，來當成氮化鈦附著 本紙張尺度適用中國國家標準（CNS) /U規格（21〇χ297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（3) 層之替代品。不幸的是，具有矽化鎢附著層之鎢通孔將 面臨"過度蝕刻（etch out)"之問題，如第1C圖所示。也就 是，現在並無可適用於對鎢層進行回蝕刻之電槳蝕刻化 學物，該化學物不會優先攻擊矽化鎢附著層2〇2，且不 造成過度蝕刻◊如果附著層被蝕刻完，鎢金屬係被"堆出 (pop out)”，而造成缺陷。電漿回蝕刻製程之另一問題係 如第1C圖所示，其在於鎢金屬204可能在回蝕刻時拒絕 進入通孔洞。如此所形成之栓塞可能嚴重影響後續形成 之内連接層之平坦化效果。因而，運用併用矽化鎢附著 層之鎢通孔係為不好之製程。 因而，在現在高密度多階積體電路中，需要形成一 可靠鎢栓塞之方法。 克服上述各種困難之重要性，係可由指向此目標而 發展出之延伸技術，如相關專利與技術文獻而得知。最 近一個具南度相關性之技術專利文獻係由美國專利第 5，604，158(Cadien等人）所揭露，其顯示一積體性矽 化鎢栓塞製程，其中鎢層係沉積在矽化鎢層之上。美國 專利第5，599，739(Merchant等人）則提出在矽化鎢層 上形成鎮之方法。 然而’仍需要一種形成方法，其形成小直徑開口之 鶴栓塞，且在接觸洞之側壁上沒有附著層，並形成具低 阻抗之接觸。 本發明之目的之一在於提供一種對矽基底形成鎢栓 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X29*?公楚） (諳先閲讀背面之注意事項再填寫本頁)B7 V. Description of the invention (2) The "keyhole" that affects reliability and causes problems is formed. In addition, when the contact hole diameter becomes smaller, the adhesion layer 116 takes up more space, which makes the aspect ratio higher and makes the "key hole" problem more serious. At the same time, under some small contact diameters, the sidewall of the contact hole The adhesion layer on it will not be used because it takes up too much space and causes the "keyhole" of the crane. The problem with the metallized through holes 110 and 112 is that the titanium nitride adhesion layer is made by sputtering. The resulting sputtering process generally exhibits poor step coverage 118, as shown in Figure 1A. Poor step coverage will cause problems with the reliability (open circuit) and performance (increased resistance) of the interconnect structure. When reducing the size of vias to get higher density circuits, step coverage will become worse and unacceptable. This problem will be more complicated when forming small vias with vertical sidewalls. Only The titanium nitride barrier layer formed by the sputtering method can be used reliably when the aspect ratio of the through hole is less than 3.0. The titanium nitride barrier layer formed by the sputtering method will not be suitable for future ULSI with aspect ratio greater than 4.0. Circuit. Central Ministry of Economic Affairs Prospective employee consumer cooperatives Indo-China chemical vapor deposition (CVD) titanium nitride adhesion layer can be regarded as a replacement for the titanium nitride barrier layer formed by the sputtering method. Compared with the sputtering method, the CVD process generally shows a better step. TiClj unfortunately, CVD titanium nitride requires a high temperature TiCLj process (600 ° 0. Such high temperature processes are not suitable for certain layers in multilayer metallization structures. In addition, TiCl4 gas may be incorporated into the barrier layer In addition, its quality is even more important. In addition, CVD titanium nitride requires high cost and complicated equipment. In addition, 'tungsten silicide adhesion layer can also be used as titanium nitride adhesion. This paper applies Chinese national standard (CNS) / U specifications. (21 × 297 mm) A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (3) layer replacement. Unfortunately, tungsten vias with tungsten silicide adhesion layer will face " over-etching (Etch out) " problem, as shown in Figure 1C. That is, there is no electric pad etching chemical suitable for etching back the tungsten layer, and this chemical will not preferentially attack the tungsten silicide adhesion layer 2 〇2, and Causes over-etching. If the adhesion layer is etched, the tungsten metal is " popped out ", causing defects. Another problem with the plasma etch-back process is shown in Figure 1C, which consists of tungsten metal. 204 may refuse to enter the through hole during the etch-back. The plug formed in this way may seriously affect the planarization effect of the subsequent formation of the interconnect layer. Therefore, the tungsten through hole using the tungsten silicide adhesion layer is a bad process. In today's high-density multi-level integrated circuits, a reliable tungsten plug needs to be formed. The importance of overcoming the various difficulties mentioned above can be learned from the extended technologies developed towards this goal, such as related patents and technical literature A recent technology-related patent document was disclosed by US Patent No. 5,604,158 (Cadien et al.), Which shows an integrated tungsten silicide plug process in which a tungsten layer is deposited on a tungsten silicide layer Above. U.S. Patent No. 5,599,739 (Merchant et al.) Proposes a method for forming a town on a tungsten silicide layer. However, there is still a need for a method of forming a crane plug with a small diameter opening, without an adhesion layer on the side wall of the contact hole, and forming a contact with low resistance. One of the purposes of the present invention is to provide a tungsten plug for forming a silicon substrate. The paper size is applicable to China National Standard (CNS) A4 (210X29 *? Gongchu) (谙 Please read the precautions on the back before filling this page)
A7 B7 五、發明説明（4) "' 塞接觸之形成方法，其使用選擇性鎢CVD製程，而允許 填滿較小尺寸之接觸洞。 本發明之另一目的在於提供_種形成嫣检塞接觸之 方法’其使用選擇性鎢CVD製程，而具有RTp自對準矽 化鎢阻障層。 為達成上述目的’本發明提供—種對基底形成鶴检 塞接觸之方法，其使用選擇性鎢CVD製程，而具有一自 對準矽化鎢阻障層。該方法包括下列步驟： 、 (a) 在矽半導體基底上形成第一絕緣層; (b) 第2圖-在第一絕緣層2〇内形成第一（接觸）開口 24，使基底之表面露出；第一開口 24之寬度（開口尺寸） 較好在0.15至0.2 " m之範圍内，更好是小於〇 2 # m ; (c) 第3圖-選擇性成長第一薄鎢層3〇於露出之基底 表面上，第一薄鶴層30之厚度範圍約在2〇〇〜5〇〇A ; (d) 第4圖對基底進行快速熱退火，以由第一薄鶴層 3〇形成第一薄矽化鎢層34 ;基底之快速熱退火之操作溫 度範圍係在於500〜800 °C内，操作時間範圍係在15〜6〇 秒内；以及 (e) 第5圓-選擇性沉積鎮插36於第一石夕化鶴層34之 上，其本質上填滿第一開口 24。 本發明係提供一種形成鎢栓塞接觸之方法，其使用 具有RTP(快速熱處理製程）自對準矽化鴿阻障層34之選 擇性鎢CVD製程。本發明係克服習知技術之許多問題， 6 本紙张尺度適用中國國家榡準（CNS ) Α4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁A7 B7 V. Description of the invention (4) " 'The method for forming the plug contact uses a selective tungsten CVD process, and allows the contact holes of a smaller size to be filled. Another object of the present invention is to provide a method for forming a plug contact, which uses a selective tungsten CVD process and has an RTp self-aligned tungsten silicide barrier layer. To achieve the above object, the present invention provides a method for forming a crane plug contact on a substrate, which uses a selective tungsten CVD process and has a self-aligned tungsten silicide barrier layer. The method includes the following steps: (a) forming a first insulating layer on a silicon semiconductor substrate; (b) FIG. 2-forming a first (contact) opening 24 in the first insulating layer 20 to expose the surface of the substrate The width (opening size) of the first opening 24 is preferably in the range of 0.15 to 0.2 " m, and more preferably less than 0 2 # m; (c) FIG. 3-Selective growth of the first thin tungsten layer 3 On the exposed surface of the substrate, the thickness of the first thin crane layer 30 is in the range of 2000-500A; (d) Figure 4: The substrate is subjected to rapid thermal annealing to form the first thin crane layer 30. The first thin tungsten silicide layer 34; the operating temperature range of the rapid thermal annealing of the substrate is within 500 ~ 800 ° C, and the operating time range is within 15 ~ 60 seconds; and (e) the fifth circle-selective deposition town Insert 36 on the first stone evening crane layer 34, which essentially fills the first opening 24. The present invention provides a method for forming a tungsten plug contact using a selective tungsten CVD process with a RTP (rapid thermal processing) self-aligned silicided dopant barrier layer 34. This invention overcomes many problems of conventional technology. 6 This paper size is applicable to China National Standard (CNS) Α4 size (210X 297 mm) (Please read the precautions on the back before filling this page
*1T 經濟部中央標隼局貝工消費合作社印聚 B7 五、發明説明（5 ) 與習知技術相較係具良率與成本上之優點。本發明之選 擇性鎢栓塞沉積係減少對鎢回蝕刻製程之需求，並減少 附著層過度蚀刻之問題。本方法也減少鶴栓塞之摺皺與 鍮匙孔問題。 本發明之矽化鎢阻障層34係增加接觸之導電性，並 可製造出更快速之元件。本發明之矽化鎢阻障層34係減 少對TiW或TiN"附著層"之需求，因而可形成更小栓塞 接觸。在接觸開口側壁上減少阻障層，允許在接觸洞内 有更多鎢栓塞空間。此多出來空間使得接觸栓塞開口之 直徑減少。這將減少錄匙孔問題’而使得鶴栓塞經由開 口而形成於更小直徑接觸内。同樣，因為矽化鎢阻障層 34可當成附著層（增進鎢與基底間之附著），鎢栓塞之選 擇性沉積係更簡易，且有更廣之製程空間。 為讓本發明之該目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例’並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 經濟部中央榡準局貝工消費合作社印聚 第1A圖至1C圖係為習知技術之检塞接觸之製造方 法之剖面圖； 第2至5囷係為本發明之半導體記憶元件之栓塞接 觸之製造方法之剖面圖；以及 第6圖係為本發明之第2圖至第5圖中製程之步驟 (602、603、604、605)流程圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） 經濟部中央標準局貝工消费合作社印衆 A7 -___ B7 五、發明説明（6) ~ 【符號說明】 10〜基底；20〜第一絕緣層；24〜開口 ； 3〇〜薄鎢 層，34〜梦化鶴層；36〜鶴检塞 實施例 請參考所附圖示來了解本發明。本發明係提供一種 對基底形成鎢栓塞接觸之方法，其使用選擇性鎢CVD製 程，而具有自對準矽化鎢阻障層。 本發明之製程可總結為如表1所示般： __表 1 :_ 星2圖-在基底上形成第一絕緣層2〇____ 第2圖-形成接觸開口 24 里—3圖-於基底表面上選擇性形成一薄鎢屉3〇__ 第4圖-對薄鶴層30進行快速熱退火，以於接觸開口 24 内形成矽化鎞屉34__ 第5圖-於矽化鎢層34上，選擇性成長鎢栓塞於接觸開口 24内__ 如第2圓所示，第一絕緣層2〇係形成於矽半導體基 底1〇之上。 基底10可能包括一半導體晶圓，於晶圓内係有主動 性1被動性元件形成於其内，並有層形成於晶圓表面 上。基底"這個詞意指包括有元件形成於半導體晶圓内， 並有層復蓋晶圓。"基底表面"這個詞係指包括半導體晶 圓上之最上層露出層，如妙表面，絕緣層及/或金屬線。 本紙張尺賴財賴 (請先閱讀背面之注意事項再填寫本頁) 、1Τ 線丨： 經濟部中央標準局貝工消費合作社印家 A7 B7 五、發明説明（7) 第一絕緣層20之厚度較好介於8000〜10000 A 之 間，其組成材質較好由下列中選擇：PSG，BPSG及未 摻雜二氧化矽，更好係由三層之三明治結構所形成，係 包括：（1)下層係為未摻雜矽玻璃層（USG) ; (2)中層係為 BPSG層；以及（3)上層係為未摻雜矽玻璃層（此三層係以 層20而示出）。 如第2圖所示，第一（接觸）開口 24係形成於第一絕 緣層20之内，而使得基底之表面露出。第一開口 24之 寬度（開口直徑）較好在〇·15與0.2以m之間，更好係小於 0.2 /z m。接觸開口可為任何形狀。 如第3圖所示，在重要步驟中，第一薄鎢層30係選 擇性成於露出之基底表面上。此薄第一鎢層30係厚度範 圍較好係在200〜500A之間，更好係約300A。 第一薄鎢層30係選擇性沉積而成，而其沉積條件係 為：H2氣艎流速約在1500〜2500 seem ; WF6氣體流速約 在50〜150sccm ;溫度介於380~430 °C之間，更好係為 380〜400 °C之間；壓力係在150〜250毫托耳之間；以及沉 積速率約在200〜500A/分；並於適當之反應器之内作用， 如冷壁Genius 8402/4系統。 本發明之第一鎢層30係選擇性成長於基底上，因為 矽基底表面可當成反應區。氧化層20係不當成反應層。 此反應係為2WF6+3Si — 2W+3SiF4。因此，將不會有反 應在Si02層20上發生，因為沒有Si可參與反應。 本紙張尺度適用中國國豕標準（CNS ) A4規格（210X297公鏟） -一* (諳先閲讀背面之注意事項再填寫本頁)* 1T Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative B7. 5. Description of the invention (5) Compared with the known technology, it has advantages in yield and cost. The selective tungsten plug deposition of the present invention reduces the need for a tungsten etch-back process and reduces the problem of over-etching of the adhesion layer. This method also reduces wrinkles and keyhole problems in crane embolism. The tungsten silicide barrier layer 34 of the present invention increases the contact's conductivity and can make faster devices. The tungsten silicide barrier layer 34 of the present invention reduces the need for TiW or TiN " adhesive layer ", so that a smaller plug contact can be formed. Reducing the barrier layer on the contact opening sidewall allows more tungsten plug space in the contact hole. This extra space reduces the diameter of the contact plug opening. This will reduce the keyhole problem 'and allow the crane plug to form in the smaller diameter contact via the opening. Similarly, because the tungsten silicide barrier layer 34 can be used as an adhesion layer (to improve the adhesion between tungsten and the substrate), the selective deposition of tungsten plugs is simpler and has a wider process space. In order to make the purpose, features, and advantages of the present invention more comprehensible, the following describes in detail the preferred embodiments and the accompanying drawings, as follows: Brief description of the drawings: Central Bureau of Standards, Ministry of Economic Affairs Figures 1A to 1C printed by the Paige Consumer Cooperatives are cross-sectional views of the manufacturing method of contact detection of conventional techniques; 2 to 5 are cross-sectional views of the method of manufacturing plug contact of semiconductor memory elements of the present invention And Figure 6 is a flowchart of the steps (602, 603, 604, 605) of the process in Figures 2 to 5 of the present invention. This paper size is applicable to Chinese National Standard (CNS) A4 (2 丨 0X297 mm), Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Yinzhong A7 -___ B7 V. Description of Invention (6) ~ [Symbol Description] 10 ~ substrate; 20 to the first insulating layer; 24 to the opening; 30 to the thin tungsten layer, 34 to the dreaming crane layer; 36 to the crane plug embodiment. Please refer to the attached drawings to understand the present invention. The invention provides a method for forming a tungsten plug contact on a substrate, which uses a selective tungsten CVD process and has a self-aligned tungsten silicide barrier layer. The manufacturing process of the present invention can be summarized as shown in Table 1: __Table 1: _ Star 2 image-forming a first insulating layer 2 on the substrate____ Fig. 2-forming a contact opening 24 li-3 image-in A thin tungsten drawer 30__ is selectively formed on the surface of the substrate. FIG. 4-rapid thermal annealing of the thin crane layer 30 to form a silicide pan 34__ in the contact opening 24. FIG. 5-on the tungsten silicide layer 34, Selectively growing tungsten plugs in the contact opening 24 __ As shown in the second circle, the first insulating layer 20 is formed on the silicon semiconductor substrate 10. The substrate 10 may include a semiconductor wafer in which an active 1 passive element is formed, and a layer is formed on the surface of the wafer. The term " substrate " means including a component formed in a semiconductor wafer and a layer covering the wafer. The term " substrate surface " refers to the uppermost exposed layer on a semiconductor wafer, such as a wonderful surface, an insulating layer, and / or a metal wire. This paper rule relies on money (please read the precautions on the back before filling out this page), 1T line 丨: A7 B7, Printed Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) 20 of the first insulation layer The thickness is preferably between 8000 and 10000 A, and its composition material is preferably selected from the following: PSG, BPSG and undoped silicon dioxide, more preferably formed by a three-layer sandwich structure, including: (1 ) The lower layer is an undoped silica glass layer (USG); (2) the middle layer is a BPSG layer; and (3) the upper layer is an undoped silica glass layer (the three layers are shown as layer 20). As shown in Fig. 2, the first (contact) opening 24 is formed in the first insulating layer 20 so that the surface of the substrate is exposed. The width (opening diameter) of the first opening 24 is preferably between 0.15 and 0.2 m, more preferably less than 0.2 / z m. The contact opening can be of any shape. As shown in FIG. 3, in an important step, the first thin tungsten layer 30 is selectively formed on the exposed substrate surface. The thickness of the thin first tungsten layer 30 is preferably between 200 and 500 A, and more preferably about 300 A. The first thin tungsten layer 30 is selectively deposited, and its deposition conditions are: H2 gas radon flow rate is about 1500 ~ 2500 seem; WF6 gas flow rate is about 50 ~ 150sccm; temperature is between 380 ~ 430 ° C , More preferably between 380 ~ 400 ° C; pressure between 150 ~ 250 millitorr; and deposition rate of about 200 ~ 500A / min; and acting in a suitable reactor, such as cold wall Genius 8402/4 system. The first tungsten layer 30 of the present invention is selectively grown on the substrate, because the surface of the silicon substrate can be used as a reaction region. The oxide layer 20 is not considered as a reaction layer. This reaction system is 2WF6 + 3Si — 2W + 3SiF4. Therefore, no reaction will occur on the SiO2 layer 20 because no Si can participate in the reaction. This paper size applies to China National Standard (CNS) A4 (210X297 male shovel)-1 * (谙 Please read the precautions on the back before filling this page)
經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（8) 參考第4圖，基底係經由快速熱退火處理，而由第 一薄鎢層30形成第一薄矽化鎢層34(也就是阻障層34)。 基底之快速退火之溫度係於500〜800 °C之間，較好係於 650〜750 °C之間，其置於於Ar氣體内，其反應時間約為 15〜60秒。本發明之層34係當成附著層，及阻障層，以 增加後續鎢栓塞製程之應用範圍。 再度參考第5圖，鎢栓塞36係選擇性沉積於第一薄 矽化鎢層34上，並將第一開口 24填滿。鎢並不沉積於 第一絕緣層之上。經由減壓CVD方法，較好於WF6氣體 與H2氣體進行縮減反應，鎢層係選擇性成長於開口（或 通孔）之中。或者，亦可使用WF6氣體與SiH4氣體間之縮 減反應。此選擇性沉積係減少對回蝕刻步驟之需求。鎢 栓塞36之選擇性沉積所使用之SiH4與WF6之比率約在 0.55-1.3之間，較好大於1.0 ;其所處之壓力係於175〜225 毫托耳之間，較好約200毫托耳；其沉積速率介於 4000〜6000A/分之間，較好約5000A/分。 栓塞36之厚度係於5000〜6000A之間，較好係約 5000A。 本發明提供一種形成具有RTP自對準矽化鎢阻障層 之鎢栓塞接觸之方法，其使用選擇性鎢CVD製程。本發 明克服習知技術中的許多缺點。與習知技術相較，本發 明具有產率與成本上之優點。本發明中之選擇蜮鎢栓塞 36沉積減少對鎢回蝕刻製程之需求，也減少附著層過度 10 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (8) Referring to Figure 4, the substrate is processed by rapid thermal annealing, and the first thin tungsten silicide layer 34 is formed from the first thin tungsten layer 30 (also Is the barrier layer 34). The rapid annealing temperature of the substrate is between 500 ~ 800 ° C, preferably between 650 ~ 750 ° C. It is placed in Ar gas, and the reaction time is about 15 ~ 60 seconds. The layer 34 of the present invention is used as an adhesion layer and a barrier layer to increase the application range of the subsequent tungsten plug process. Referring again to FIG. 5, the tungsten plug 36 is selectively deposited on the first thin tungsten silicide layer 34 and fills the first opening 24. Tungsten is not deposited on the first insulating layer. Through the reduced pressure CVD method, it is better that the WF6 gas and the H2 gas undergo a reduction reaction, and the tungsten layer is selectively grown in the opening (or through hole). Alternatively, a reduction reaction between WF6 gas and SiH4 gas may be used. This selective deposition reduces the need for an etch-back step. The ratio of SiH4 to WF6 used in the selective deposition of tungsten plug 36 is between about 0.55 and 1.3, preferably greater than 1.0; the pressure at which it is located is between 175 and 225 mTorr, preferably about 200 mTorr Ear; its deposition rate is between 4000 ~ 6000A / min, preferably about 5000A / min. The thickness of the plug 36 is between 5000 and 6000A, preferably about 5000A. The invention provides a method for forming a tungsten plug contact with an RTP self-aligned tungsten silicide barrier layer, which uses a selective tungsten CVD process. The present invention overcomes many of the shortcomings of conventional techniques. Compared with the conventional technology, the present invention has advantages in productivity and cost. The choice of thorium tungsten plug 36 in the present invention reduces the need for the tungsten etch-back process and reduces the excessive adhesion layer. 10 The paper size applies the Chinese National Standard (CNS) A4 specification (210X29 * 7 mm) (Please read the back (Please fill in this page again)
五 9 A7 B7 發明説明（ 蝕刻之問題。本方法也減少鎢摺皺與鑰匙孔問題。 本發明之矽化鎢阻障層34係增加接觸之導電度，而 製造出更快速之元件。本發明之矽化鎢阻障層34係減少 對TiW或ΤιΝ"附著層"之需求，因而可形成更小栓塞接 觸。減少在接觸開口側壁上之阻障層允許在接觸洞内有 更多的鎢栓塞空間。此多出來空間使得接觸栓塞開口之 直徑減少。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此項技藝者，在不脫離本發明 之精神和範圍内，當可作更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 請 先 閱 讀 背 之 注 項 再， 筠t. 本 頁- 訂 經濟部中央標準局員工消费合作社印製 本纸張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐.)Five 9 A7 B7 invention description (the problem of etching. This method also reduces the problem of tungsten wrinkles and keyholes. The tungsten silicide barrier layer 34 of the present invention increases the conductivity of the contact, and makes faster components. The silicidation of the present invention The tungsten barrier layer 34 reduces the need for TiW or TiN " adhesive layer ", which can form smaller plug contacts. Reducing the barrier layer on the sidewall of the contact opening allows more tungsten plug space in the contact hole. This extra space reduces the diameter of the opening of the contact plug. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art will not depart from the spirit and scope of the present invention. Changes and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. Please read the note below, 筠 t. This page-Order staff of the Central Standards Bureau of the Ministry of Economic Affairs The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm.)