CN106463396B - 防止铜扩散的电介质/金属阻挡体集成 - Google Patents

防止铜扩散的电介质/金属阻挡体集成 Download PDF

Info

Publication number
CN106463396B
CN106463396B CN201580006488.1A CN201580006488A CN106463396B CN 106463396 B CN106463396 B CN 106463396B CN 201580006488 A CN201580006488 A CN 201580006488A CN 106463396 B CN106463396 B CN 106463396B
Authority
CN
China
Prior art keywords
metal
layer
dielectric layer
cobalt
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580006488.1A
Other languages
English (en)
Other versions
CN106463396A (zh
Inventor
任河
M·B·奈克
曹勇
石美仪
程亚娜
S·R·V·克萨普拉嘎达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN106463396A publication Critical patent/CN106463396A/zh
Application granted granted Critical
Publication of CN106463396B publication Critical patent/CN106463396B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

描述一种在半导体器件中使用的互连件结构和用于制造所述互连件结构的方法。所述方法包括将基板定位在真空处理腔室中。所述基板具有暴露的铜表面和暴露的低k电介质表面。金属层形成在所述铜表面上方而不是在所述低k电介质表面上方。基于金属的电介质层形成在所述金属层和所述低k电介质层上方。

Description

防止铜扩散的电介质/金属阻挡体集成
背景
技术领域
本发明的方面总体上涉及在半导体器件中使用的互连件结构(interconnectstructure)和用于形成此类结构的方法。
背景技术
近数十年来，集成电路上的部件的特征尺寸已不断减小。随着特征尺寸减小，计算机已变得更加强大且对于消费者而言较不昂贵。为了此降低的趋势继续，环绕互连件的电介质阻挡体的厚度也必须减小。互连件连接集成电路上的不同部件。较薄的电介质阻挡体与较低的电介质阻挡体的介电常数以及较低的环绕此互连件的电容(下文中的“线间(interline)电容”)相关联。常规的互连件由铜制成，选择铜是因为与其他金属相比，铜是高度导电的。然而，铜扩散进入常规的电介质阻挡体，最终造器件故障。遗憾地，铜的扩散率随着电介质阻挡体的厚度减小而变得放大。
因此，本领域中需要的是一种改进的互连件结构和用于形成此类结构的方法。
发明内容
本发明的实施例涉及一种互连件结构和制造所述互连件结构的方法。所述方法包括将基板定位在真空处理腔室中。所述基板具有暴露的铜表面和暴露的低k电介质表面。金属层沉积在所述铜表面上方。例如，所述金属层可选择性地沉积在所述铜表面上方。所述金属层可包括钴化合物。基于金属的电介质层沉积在所述金属层上方且在所述电介质表面的至少一部分上方。所述基于金属的电介质层可包括铝化合物。
所述互连件结构包括低k电介质层。所述低k电介质层具有沟槽，所述沟槽于所述低k电介质层中经图案化而成。铜层至少部分地填充所述沟槽。金属层形成在所述铜层上方且包括钴化合物。基于金属的电介质层形成在所述金属层和所述低k电介质层上方。所述基于金属的电介质层可包括铝化合物。
附图说明
为了详细地理解本发明的上述特征的方式，可通过参考实施例(实施例中的一些在附图中示出)得出以上简要概括的本发明的更具体的描述。然而应注意，所附附图仅描绘此发明的典型实施例，并且因此不应视为限制本发明的范围，因为本发明可允许其他等效实施例。
图1是用于形成互连件结构的工艺的流程图；以及
图2A至图2G描绘图1的工艺的不同阶段处的互连件结构。
为了促进理解，已在可能的情况下使用相同的元件标号指定附图所共有的相同元件。构想到，一个实施例的元件和特征可有益地并入其他实施例而无需进一步的记叙。
具体实施方式
虽然前述内容涉及本发明的实施例，可设计本发明的其他和进一步的实施例而不背离本发明的基本范围，并且本发明的范围由所附权利要求书确定。
如在本文中所用，真空处理系统包括工具，在此工具内，可在不破坏真空的情况下(即不将基板暴露于周围环境的情况下)在两个或更多个真空处理腔室中处理基板。代表性的真空处理系统是群集工具。如在本文中所用，真空处理腔室包括蚀刻腔室、清洁腔室、或沉积腔室。沉积腔室可例如是化学气相沉积反应器(CVD)、原子层沉积反应器(ALD)、物理气相沉积反应器(PVD)、或适合于沉积电介质层(诸如低k电介质层)、金属层、和/或金属氧化物、金属氮化物、或金属氮氧化物层的其他腔室。如在本文所用，低k电介质材料是介电常数低于二氧化硅的介电常数(或低于4.0)的材料，且包括碳掺杂的氧化硅和其他适合的材料，例如可购自位于美国加利福尼亚州圣克拉拉市的应用材料公司的BLACK
Figure BDA0001063953010000021
低k电介质。如在本文所用，“钴化合物”包括金属钴以及包含钴与一种其他元素的化合物，诸如，例如磷化钴钨、氮化钴钨、或磷氮化钴钨。如在本文所用，“铝化合物”包括含有铝与至少一种其他元素的化合物，诸如，例如氧化铝、氮化铝、和氮氧化铝。如在本文所用，“铜”包括金属铜和铜的合金。术语“前体”用于指参与反应以从表面移除或沉积材料的任何工艺气体。
通过在铜层上方顺序地形成金属层和基于金属的的电介质层，可制造薄的集成电介质阻挡体，所述薄的集成电介质阻挡体具有降低的线间电容和对铜的低扩散率。金属层可沉积在互连件结构的暴露的铜表面上，而不是在互连件结构的暴露的电介质表面上。金属层可以是钴或对铜有良好附着力的其他金属。通过良好地附着到铜，金属层对电迁移有抗性且辅助防止铜扩散。基于金属的电介质层可包括由铝化合物(诸如氧化铝、氮化铝、和/或氮氧化铝)。基于金属的电介质层提供器件整体性，防止铜扩散，且充当电介质阻挡体。包括金属层和基于金属的电介质层的集成结构的对于铜扩散率的抗性是惊人的，所述金属层包括钴化合物；所述基于金属的电介质层包括铝化合物。此集成结构的对铜扩散的抗性基本上高于组合的金属层与基于金属的电介质层的对扩散的抗性之和。
图1是工艺流程图，概述了用于形成具有多个层的互连件结构的工艺100。图2A至图2G是互连件结构在工艺100的不同阶段的剖面视图。在框102，在真空处理腔室中(诸如，在真空处理系统的真空处理腔室中)将电介质层210形成在基板200上。基板200提供表面，多个器件可形成在所述表面上，利用形成在这些器件上方的互连件结构来选择性地连接这些器件。如此，基板可以是半导体材料(诸如硅、锗、或化合物半导体)、电介质材料(诸如玻璃、陶瓷、或塑料)、或导电材料(诸如铝或另外的金属)。电介质层210可沉积达约
Figure BDA0001063953010000031
至约
Figure BDA0001063953010000032
的厚度。电介质层210可包括低k电介质材料。
在框104，沟槽212形成在电介质层210中。例如，可通过在电介质层210上图案化光阻层并且使用适合的蚀刻工艺来形成沟槽212。沟槽212可延伸至基板210(如图2B所示)或可终止在不到基板210的位置。沟槽212具有侧壁211和底面213。侧壁211可垂直于基板210(如图所示)或可以倾斜。
在任选的框106并且如图2C所示，衬里层214形成在沟槽212的侧壁211和底面213上。衬里层214可充当阻挡层。衬里层214可保形地(conformally)形成在侧壁211和底面213上。衬里层214可沉积达例如约
Figure BDA0001063953010000033
Figure BDA0001063953010000034
至约
Figure BDA0001063953010000035
的厚度。衬里层214可例如为钽、氮化钽、钴、钌、或其他适合的材料。
在框108，铜层216形成在衬里层214上。铜层216至少部分地填充沟槽212。铜层216可仅部分地填充沟槽212、可完整地填充沟槽212、或且可完整地填充沟槽212且覆盖电介质层210的一部分(如图2D所示)。可通过电镀或其他适合的技术来沉积铜层216。
在任选的框110并且如图2E所示，移除铜层216和衬里层214的多个部分以暴露电介质层210的表面、衬里层214的表面和铜层216的表面。可使用化学机械研磨来移除铜层216、衬里层214和电介质层210的那些部分。框110之后，电介质层210、衬里层214以及铜层216的上表面可基本上共面。
在任选的框112，可预清洁铜层216。预清洁工艺从铜表面移除污染物，诸如氧化铜。可通过将基板200暴露于还原剂来化学地还原氧化铜。在热工艺或等离子体工艺期间，预清洁工艺可将基板200暴露于还原剂。还原剂可具有液态、气态、等离子体态、或前述态的组合。可在预清洁工艺期间使用的还原剂包括例如氢(例如H2或原子H)、氨(NH3)以及氢与氨的混合物(H2/NH3)。
在框114，金属层218形成在铜层216的暴露的表面上。金属层218可沉积成使得电介质层210无金属或基本上无金属，如图2F中所示。在框112与框114之间，可在不破坏真空的情况下执行框114。通过防止基板暴露于真空处理系统外的周围环境，可完全或基本上无氧化地形成铜层216。金属层218可包括钴化合物或金属铝。钴化合物可以是，例如钴(Co)、磷化钴钨(CoWP)、氮化钴钨(CoWN)、磷氮化钴钨(CoWPN)、或前述各项的混合物。金属层218可具有范围从
Figure BDA0001063953010000041
至约
Figure BDA0001063953010000042
(例如从约
Figure BDA0001063953010000043
至约
Figure BDA0001063953010000044
诸如约
Figure BDA0001063953010000045
)的厚度。
可使用ALD、CVD、PVD、旋涂技术、或其他适合的技术来沉积金属层218。ALD可用于一些实施例，在这些实施例中，通过使基板暴露于与铜层216起反应而不与电介质层210起反应的前体，金属层218沉积在铜层216上而不是在电介质层210上。在金属层218包括钴的实施例中，可将含钴前体引入真空处理腔室中。在金属层218包括钴与钨的实施例中，可将含钴前体与含钨前体引入真空处理腔室中。氮和/或磷可通过在处理期间将含氮和/或磷的掺杂剂引入真空处理腔室而被引入金属层218。
使用CVD或ALD沉积工艺的代表性处理条件包括以下。温度可以在约50℃与约300℃之间，诸如在约100℃与约200℃之间。真空处理腔室的压力可维持在约100毫托与约5托之间，诸如在约1托与约2托之间。含钴前体与任何含钨前体任何掺杂剂的流速范围可从约50sccm至约5000sccm，诸如在约500sccm与约2500sccm之间。
适合的含钴前体包括钴前体，诸如：甲基环戊二烯基钴双(羰基)(MeCpCo(CO)2)、乙基环戊二烯基钴双(羰基)(EtCpCo(CO)2)、二钴八(羰基)(Co2(CO)8)以及亚硝酰基钴三(羰基)((ON)Co(CO)3)。适合的含钴前体还包括钴羰基化合物或复合物，诸如环戊二烯基钴双(羰基)(CpCo(CO)2)、三羰基烯丙基钴((CO)3Co(CH2CH═CH2))、二钴六羰基丁基乙炔(CCTBA，(CO)6Co2(HC≡CtBu))、二钴六羰基甲基丁基乙炔((CO)6Co2(MeC≡CtBu))以及二钴六羰基苯基乙炔((CO)6Co2(HC≡CPh))。适合的含钴前体还包括钴脒盐(amidinate)或钴酰胺基复合物，诸如双(二(丁基二甲基硅烷基)酰胺基)钴(((BuMe2Si)2N)2Co)、双(二(乙基二甲基硅烷基)酰胺基)钴(((EtMe2Si)2N)2Co)、双(二(丙基二甲基硅烷基)酰胺基)钴(((PrMe2Si)2N)2Co)以及双(二(三甲基硅烷基)酰胺基)钴(((Me3Si)2N)2Co)。
适合的含钨前体包括W(CO)6。适合的含钨前体还包括钨卤化物(WX6，其中X是卤素)。适合的氮掺杂剂包括NF3、NH3、N2、N2H4。适合的磷掺杂剂包括例如PH3。
在框116，基于金属的电介质层220形成在电介质层210和金属层218的顶部上。基于金属的电介质层220可形成在电介质层210的暴露表面的至少一部分上，诸如在电介质层210的整个暴露表面上(如图2G所示)。基于金属的电介质层220可具有约
Figure BDA0001063953010000051
至约
Figure BDA0001063953010000052
的厚度，诸如约
Figure BDA0001063953010000053
至约
Figure BDA0001063953010000054
Figure BDA0001063953010000055
在框114与框116之间，可在不破坏真空的情况下执行框116。通过防止基板200暴露于真空处理系统外的周围环境，可完全或基本上无氧化地形成金属层218。例如，如果破坏真空，则钴金属层218的表面5至
Figure BDA0001063953010000056
可能是CoO。如果不破坏真空，则钴金属层218的表面5至
Figure BDA0001063953010000057
可以是纯钴。
基于金属的电介质层220可包括氧化铝、氮化铝、氮氧化铝、或前述各项的混合物。基于金属的电介质层220可使用PVD来沉积。代表性的PVD处理条件包括以下。靶材可以为氧化铝、氮化铝、氮氧化铝、或前述各项的混合物。温度可以在约100℃与约400℃之间，诸如在约150℃与约350℃之间，例如200℃。压力可以在约3毫托与约400毫托之间，诸如在约50毫托与100毫托之间，诸如70毫托。可使用氩运载等离子体，且源功率可以在约500瓦与约3000瓦之间，诸如在约1000瓦与约2000瓦之间，诸如约1500瓦。
在任选的框118，如果在基板200上要求附加的互连件，则可将第二电介质层210’(未示出)形成在基于金属的电介质层220的顶部上，且可重复框102、104、106、108、110、112、114以及116的工艺。在一个实施例中，第二电介质层210’直接形成在基于金属的电介质层220上方。通过重复此工艺任何期望的次数，可提供任何数目的互连件。
示例
为了将钴金属层218沉积在铜层216的暴露的表面上，在类似ALD的工艺中，可顺序地将甲基环戊二烯基钴双(羰基)(MeCpCo(CO)2)与NH3引入真空处理腔室中。可将甲基环戊二烯基钴双(羰基)连同氩运载气体一起以200sccm的流速引入真空处理腔室中，同时处理腔室维持在1.5托。随后此腔室可被排空且用氩净化。随后可将氨连同氩运载气体一起以300sccm引导，同时真空处理腔室维持在120毫托。在引入甲基环戊二烯基钴双(羰基)与氨两者期间，处理腔室可维持在150℃。
为了使用PVD工艺将氮化铝的基于金属的电介质层220沉积在金属层218和电介质层210上，基板可定位在真空处理腔室内，所述真空处理腔室维持在5毫托和200℃。可使用铝金属靶材，且可由1000瓦源功率的源功率生成N2/Ar等离子体。
前述实施例具有许多优点，包括所公开的电介质阻挡体的实施例具有减少的线间电容、比常规技术低的铜扩散率；并且可比常规技术更薄。例如，在20nm工艺节点(N20)，与常规的电介质阻挡体相比，本文公开的电介质阻挡体已证实在线间电容上降低了大约5％。本文公开的实施例证实有约160pF的线间电容，然而常规技术证实有约152pF的线间电容。线间电容中的这种剧烈降低是令人惊讶的，因为先前尝试降低线间电容只努力使线间电容降低2％而已。此外，本文公开的电介质阻挡体比常规阻挡体更薄，同时证实有低的铜扩散率。本文公开的实施例可基本上防止总体
Figure BDA0001063953010000061
或更小的厚度处的铜扩散。例如，当在铜基板的顶部上形成包括钴化合物的
Figure BDA0001063953010000071
金属层与
Figure BDA0001063953010000072
氮化铝层时，铜扩散的激活能与电介质阻挡体的击穿电压基本上相同。此外，线对线泄漏也与具有
Figure BDA0001063953010000073
的厚度的常规SiN阻挡体相当。前述优点是说明性的而非限制性的。本发明的所有实施例没必要具有本发明的所有优点或实现本发明的所有目的。
虽然前述内容涉及本发明的实施例，但可设计本发明的其他和进一步的实施例而不背离本发明的基本范围，且本发明的范围由所附权利要求书确定。

Claims (15)

1.一种用于形成互连件结构的方法，所述方法包括以下步骤：
将基板定位在真空处理腔室中，其中所述基板包括具有暴露的表面的铜层和具有暴露的表面的低k电介质层；
将金属层形成在暴露的铜表面上方，其中所述金属层包括钴化合物；以及
形成与所述金属层和暴露的低k电介质表面的至少一部分实体接触的基于金属的电介质层，其中所述基于金属的电介质层包括铝化合物。
2.如权利要求1所述的方法，其中所述钴化合物包括钴、磷化钴钨、氮化钴钨、或磷氮化钴钨。
3.如权利要求2所述的方法，其中所述金属层的厚度为从
Figure FDA0002230754800000011
至
Figure FDA0002230754800000012
且所述基于金属的电介质层的厚度为从
Figure FDA0002230754800000013
至
Figure FDA0002230754800000014
4.如权利要求1所述的方法，其中在没有空气断开的情况下形成所述金属层和所述基于金属的电介质层。
5.如权利要求1所述的方法，其中所述铝化合物包括氧化铝、氮化铝、或氮氧化铝。
6.如权利要求1所述的方法，其中所述金属层不形成在所述低k电介质层的暴露的表面上。
7.如权利要求1所述的方法，进一步包括下述步骤：
直接在所述基于金属的电介质层上方形成第二低k电介质层；
在所述第二低k电介质层中形成沟槽；以及
至少部分地以铜填充所述沟槽。
8.一种用于形成互连件结构的方法，所述方法包括下述步骤：
将基板定位在真空处理腔室中，其中所述基板包括具有暴露的表面的铜层以及具有暴露的表面的低k电介质层；
将金属层形成在暴露的铜表面上方而不在暴露的电介质表面上方，其中所述金属层包括钴、磷化钴钨、氮化钴钨、或磷氮化钴钨，且其中所述金属层通过物理气相沉积形成；
形成与所述暴露的电介质表面和所述金属层实体接触的基于金属的电介质层，其中所述基于金属的电介质层包括氧化铝、氮化铝、或氮氧化铝，并且在没有空气断开的情况下形成所述金属层和所述基于金属的电介质层；
直接在所述基于金属的电介质层上方形成第二低k电介质层；
在所述第二低k电介质层中形成沟槽；以及
至少部分以铜填充所述沟槽。
9.一种互连件结构，包括：
低k电介质层，其中所述低k电介质层被图案化有沟槽；
铜层，至少部分地填充所述沟槽；
金属层，其中所述金属层设置在所述铜层上方，且其中所述金属层包括钴化合物；以及
基于金属的电介质层，设置为与所述金属层和所述低k电介质层实体接触，其中所述基于金属的电介质层包括铝化合物。
10.如权利要求9所述的结构，其中所述钴化合物包括钴、磷化钴钨、氮化钴钨、或磷氮化钴钨。
11.如权利要求9所述的结构，其中所述金属层的厚度为从
Figure FDA0002230754800000021
至
Figure FDA0002230754800000022
12.如权利要求9所述的结构，其中所述基于金属的电介质层的厚度为从
Figure FDA0002230754800000023
至
Figure FDA0002230754800000024
13.如权利要求9所述的结构，其中所述铝化合物包括氧化铝、氮化铝、或氮氧化铝。
14.如权利要求9所述的结构，进一步包括：
第二低k电介质层，直接设置在所述基于金属的电介质层上方，其中所述第二低k电介质层被图案化有沟槽；以及
第二铜层，所述第二铜层至少部分地填充所述第二低k电介质层的所述沟槽。
15.如权利要求9所述的结构，其中所述金属层不设置在所述低k电介质层上方。
CN201580006488.1A 2014-02-05 2015-01-16 防止铜扩散的电介质/金属阻挡体集成 Active CN106463396B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/173,807 US9601431B2 (en) 2014-02-05 2014-02-05 Dielectric/metal barrier integration to prevent copper diffusion
US14/173,807 2014-02-05
PCT/US2015/011714 WO2015119760A1 (en) 2014-02-05 2015-01-16 Dielectric/metal barrier integration to prevent copper diffusion

Publications (2)

Publication Number Publication Date
CN106463396A CN106463396A (zh) 2017-02-22
CN106463396B true CN106463396B (zh) 2020-03-10

Family

ID=53755475

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580006488.1A Active CN106463396B (zh) 2014-02-05 2015-01-16 防止铜扩散的电介质/金属阻挡体集成

Country Status (5)

Country Link
US (2) US9601431B2 (zh)
KR (2) KR102389811B1 (zh)
CN (1) CN106463396B (zh)
TW (1) TWI694501B (zh)
WO (1) WO2015119760A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090269507A1 (en) * 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US9719167B2 (en) * 2015-12-31 2017-08-01 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Cobalt-containing film forming compositions, their synthesis, and use in film deposition
KR102662612B1 (ko) * 2016-10-02 2024-05-03 어플라이드 머티어리얼스, 인코포레이티드 루테늄 라이너로 구리 전자 이동을 개선하기 위한 도핑된 선택적 금속 캡
US10358719B2 (en) 2016-11-23 2019-07-23 Applied Materials, Inc. Selective deposition of aluminum oxide on metal surfaces
US10373906B2 (en) * 2017-04-20 2019-08-06 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of interconnection structure of semiconductor device
US20190309422A1 (en) * 2018-04-06 2019-10-10 Versum Materials Us, Llc Spin-On Metallization
US20200347493A1 (en) 2019-05-05 2020-11-05 Applied Materials, Inc. Reverse Selective Deposition
CN113257734B (zh) * 2021-04-30 2023-06-23 北海惠科半导体科技有限公司 半导体器件及其制作方法和芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW520560B (en) * 2000-04-11 2003-02-11 Micron Technology Inc Use of ALN as a copper passivation layer and thermal conductor, and its method of formation
CN1623228A (zh) * 2002-05-03 2005-06-01 英特尔公司 导电无电镀沉积刻蚀停止层、衬垫层及通孔插塞在互连结构中的使用
CN101032015A (zh) * 2004-06-14 2007-09-05 恩索恩公司 在电子装置集成电路上的金属互连结构元件盖
CN102760684A (zh) * 2011-04-26 2012-10-31 中芯国际集成电路制造(上海)有限公司 金属互连方法
CN103026466A (zh) * 2010-06-09 2013-04-03 应用材料公司 形成互连结构的方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256663A (ja) * 1985-05-09 1986-11-14 Agency Of Ind Science & Technol 半導体装置
US5783483A (en) * 1993-02-24 1998-07-21 Intel Corporation Method of fabricating a barrier against metal diffusion
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6495452B1 (en) * 1999-08-18 2002-12-17 Taiwan Semiconductor Manufacturing Company Method to reduce capacitance for copper interconnect structures
US20040096592A1 (en) 2002-11-19 2004-05-20 Chebiam Ramanan V. Electroless cobalt plating solution and plating techniques
US7402519B2 (en) * 2005-06-03 2008-07-22 Intel Corporation Interconnects having sealing structures to enable selective metal capping layers
TWI295816B (en) * 2005-07-19 2008-04-11 Applied Materials Inc Hybrid pvd-cvd system
US7405154B2 (en) 2006-03-24 2008-07-29 International Business Machines Corporation Structure and method of forming electrodeposited contacts
US7482261B2 (en) 2006-07-26 2009-01-27 International Business Machines Corporation Interconnect structure for BEOL applications
US8278216B1 (en) * 2006-08-18 2012-10-02 Novellus Systems, Inc. Selective capping of copper
DE102007004867B4 (de) * 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid
US8138604B2 (en) 2007-06-21 2012-03-20 International Business Machines Corporation Metal cap with ultra-low k dielectric material for circuit interconnect applications
US20090269507A1 (en) * 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US8242019B2 (en) * 2009-03-31 2012-08-14 Tokyo Electron Limited Selective deposition of metal-containing cap layers for semiconductor devices
US8039920B1 (en) * 2010-11-17 2011-10-18 Intel Corporation Methods for forming planarized hermetic barrier layers and structures formed thereby
US20120161320A1 (en) * 2010-12-23 2012-06-28 Akolkar Rohan N Cobalt metal barrier layers
WO2013095433A1 (en) * 2011-12-21 2013-06-27 Intel Corporation Electroless filled conductive structures
US9090641B2 (en) * 2012-03-09 2015-07-28 Applied Materials, Inc. Precursors and methods for the selective deposition of cobalt and manganese on metal surfaces
CN104347476B (zh) * 2013-07-23 2018-06-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
US9659857B2 (en) * 2013-12-13 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method making the same
US9487864B2 (en) * 2014-01-15 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Metal capping process and processing platform thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW520560B (en) * 2000-04-11 2003-02-11 Micron Technology Inc Use of ALN as a copper passivation layer and thermal conductor, and its method of formation
CN1623228A (zh) * 2002-05-03 2005-06-01 英特尔公司 导电无电镀沉积刻蚀停止层、衬垫层及通孔插塞在互连结构中的使用
CN101032015A (zh) * 2004-06-14 2007-09-05 恩索恩公司 在电子装置集成电路上的金属互连结构元件盖
CN103026466A (zh) * 2010-06-09 2013-04-03 应用材料公司 形成互连结构的方法
CN102760684A (zh) * 2011-04-26 2012-10-31 中芯国际集成电路制造(上海)有限公司 金属互连方法

Also Published As

Publication number Publication date
KR20210103592A (ko) 2021-08-23
TWI694501B (zh) 2020-05-21
US20170162511A1 (en) 2017-06-08
US9601431B2 (en) 2017-03-21
CN106463396A (zh) 2017-02-22
TW201535487A (zh) 2015-09-16
US20150221596A1 (en) 2015-08-06
KR20160117541A (ko) 2016-10-10
US10008448B2 (en) 2018-06-26
KR102388695B1 (ko) 2022-04-19
WO2015119760A1 (en) 2015-08-13
KR102389811B1 (ko) 2022-04-21

Similar Documents

Publication Publication Date Title
CN106463396B (zh) 防止铜扩散的电介质/金属阻挡体集成
US11959167B2 (en) Selective cobalt deposition on copper surfaces
US9209074B2 (en) Cobalt deposition on barrier surfaces
KR102662612B1 (ko) 루테늄 라이너로 구리 전자 이동을 개선하기 위한 도핑된 선택적 금속 캡
CN110214200B (zh) 通过掺杂钌增强的钴抗团聚性与缝隙填充性能
KR101615292B1 (ko) 기판상에 막 스택을 형성하는 방법
US8524600B2 (en) Post deposition treatments for CVD cobalt films
KR102189781B1 (ko) 망간 및 망간 니트라이드들의 증착 방법들
KR100477816B1 (ko) 반도체 소자의 티타늄 실리사이드 콘택 형성 방법
CN109461698B (zh) 用于铜互连件的种晶层

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant