TW519708B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW519708B
TW519708B TW086108833A TW86108833A TW519708B TW 519708 B TW519708 B TW 519708B TW 086108833 A TW086108833 A TW 086108833A TW 86108833 A TW86108833 A TW 86108833A TW 519708 B TW519708 B TW 519708B
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TW
Taiwan
Prior art keywords
gate
finger
drain
source
pad
Prior art date
Application number
TW086108833A
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English (en)
Inventor
Tomoaki Kimura
Original Assignee
Nec Corp
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Publication date
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Publication of TW519708B publication Critical patent/TW519708B/zh

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Wire Bonding (AREA)

Description

經濟部中央標準局員工消費合作社印製 519708 A7 _____ B7 ___ 五、發明説明（l ) 本發明是有關於一種半導體裝置，特別是有關於一種 微波電晶體。 如第4圖所示的圖樣是一種低雜訊電晶體，其係廣泛 地用在雜訊c到ku頻帶的微波放大元件中。這電晶體圖樣 中含有閘極指狀物12a，閘電極墊片12，源極墊片I4和 汲極墊片13。閘極指狀物12a直排於柱11之上。閘電極 墊片12則從閘極指狀物12a的中央部份向外延伸至一側。 源極墊片14圍繞著閘電極墊片12。汲極墊片13設置在源 極墊片14相對於閘極指狀物12a的另側。這種電晶體圖樣 稱為π型圖樣。連接線16經由焊球π與電極墊片12、13 和14分別連接。 相對於π型圖樣，近年來則又發展出另種雜訊電晶 體，係以架空線(earial wirings)形成圖樣。如第5圖所示， 這類圖樣含有閘極墊片22，4個閘極指狀物22a，〆個Η 形源極塾片24和一個源極路徑24b，一個源極指狀物 24a、一個汲極墊片23、兩個汲極指狀物23&、和一個架 空線25。閘極墊片22設置在柱21上。四個閘極指狀物22a 則從閘極墊片22向外平行拉出。源極墊片24和源極路徑 24b係以三明治夾層方式與閘極墊片22和閘極指狀物22a 搭配β又置。源極指狀物24a從源極路徑2朴拉出並設置在 為兩個中央閘極指狀物22a之間的區域。汲極墊片23設置 在源極路徑24b相對於閘極墊片22的另側。兩個汲極指狀 物23a則位於剩餘的位置，並夾在閘極指狀物22a之間。 架空線25連接汲極指狀物23a而延伸穿過源極路徑24b。 -----：--.--0^-- (請先閲讀背面之注意事項再填寫本頁) 訂
519708 A7 B7 五、發明説明（2) 這種圖樣稱為Η形圖樣。連接線26則經由焊點27分別與 電極墊片22、23和24連接。 在第4圖的π型圖樣中，閘極墊片12為源極墊片14 圍繞，而在第5圖Η型圖樣中，閘極墊片22和汲極墊片 23都為源極墊片24夾住。因此，閘極墊片12的面積或閘 極墊片22和汲極墊片23的面積都受到源極墊片14和24 的限制。而且，柱11和21都有尺寸的限制，不可能形成 大尺寸的閘極墊片12和22，以及汲極墊片23，而焊接時 更可能因為對不準而產生缺陷。 因此，本發明之目的在提供一種半導體裝置，用以防 止因焊接不對準產生的缺陷。 為了達到此一目的，本發明乃提出一種半導體裝置， 含有矩形柱，柱有一第一和第二對角線，而在第一對角線 的兩個矩形角其中之一設有閘極墊片，汲極墊片則在另一 個角上。一對源極墊片則在柱的第二對角線兩個角上，並 且以一源極路徑連接兩個源極墊片。 圖式之簡單說明： 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 第1圖為依照本發明一第一實施例之低雜訊微波電晶 體半導體裝置之基本圖樣； 第2圖為依照本發明一第二實施例之低雜訊微波電晶 體半導體裝置之基本圖樣； 第3圖為依照本發明一第三實施例之低雜訊微波電晶 體半導體裝置之基本圖樣； 第4圖為一傳統半導體裝置的π型圖樣；以及 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐〉 519708 五、 A7 B7 發明説明（3 ,) 第5圖為一傳統半導體裝置的Η型圖樣。 以下即以圖式辅助詳細說明本發明。 (第一實施例） 第1圖為依照本發明第一實施例之低雜訊微波電晶體 基本圖樣。請參照第1圖，本實施例之基本圖樣含有閘極 塾片102、没極墊片1〇3以及兩個源極墊片1〇4。閘極墊 片102位於一矩形柱101的四個角之一，而係在一對角線 上。汲極墊片103位於同一條對角線的另一端角落。源極 墊片104在柱101的另一條對角線兩端的兩個角落上。 四個梳狀閘極指狀物1 〇2a從閘極塾片1 〇2伸出到柱 1〇1的中央部份。兩個汲極指狀物l〇3a從汲極墊片1〇3伸 出’而位於閘極指狀物1 〇2a兩末端邊所夾住的兩個區域之 間。 兩個源極墊片104經由一條源極路10413彼此相連，源 極路徑104b則係位於閘極塾片102和從沒極塾片1Q3伸出 之汲極指狀物103a遠端之間。源極路徑1〇4b在閘極指狀 物l〇2a上方延伸而穿過架空線1〇5。一源極指狀物1〇私 從源極路徑104b伸出而位於兩個中央閘極指狀物1〇2&之 間。 連接線106經焊球107與閘極墊片1〇2及汲極墊片1〇3 分別連接。兩個源極墊片104各有兩條連接線1〇6經焊球 1〇7，而形成四條連接線106。為了減小源極接地阻抗， 以使頻率提高，可以更多的連接線1〇6連接源極墊片1〇4。 依照刖述圖樣配置’由於電極塾片，亦即焊接墊片 ：--— ιφ^-- (請先閲讀背面之注意事項再填寫本頁) ，1Τ 經濟部中央標準局員工消費合作社印製 519708 A7 B7 五、發明説明（4 ) 一 ' 102、1〇3和1〇4係置於柱ι〇1的四個角落上，即使柱1〇1 有尺寸限制，焊接墊片1〇2、103和1〇4的面積仍可維持 相當大。例如，若柱1〇1的面積是350平方微米，墊片1〇2、 103和1〇4的總面積可以達到ι〇〇平方微米。 因焊接墊片102、103和104的面積得以增大，焊接 時對不準的容忍量也可增大，以致焊接失敗的可能性就減 小了。例如，焊接失敗的比率得從〇·5%降到〇〇1%或更低。 隨著焊接指數速率加快，焊接不準的機會也增大。依 照本發明，因焊接不對準的容忍量加大了，焊接指數速率 得以增至比傳統方式更高的程度。因此，產量得以增高約 百分之十。 在本實施例中，源極路徑l〇4b是以架空線構成。然 而，閘極指狀物102a可以架空線構成。除了架空線，交又 線亦得利用，其係以一絕緣層隔開一上繞線和一下繞線。 (第二實施例） 經濟部中央標準局員工消費合作社印製 ------^--·— -- (請先閲讀背面之注意事項再填寫本頁) f 第2圖為依照本發明第二實施例低雜訊微波電晶體的 基本圖樣’請參照第2圖，一閘極坠片1 〇2、一沒極塾片 1〇3和一源極墊片1〇4構成類似第1圖的圖樣配置，故其 細部描述乃予以省略。 六個梳狀閘極指狀物1 〇2a從閘極塾片1 〇2向柱1 〇 1的 中央部份伸出。三個汲極指狀物103a從汲極墊片1〇3伸 出’而係配置在由中央閘極指狀物102a和兩個側閘極指狀 物102a所隔成的三個區域中。兩個源極塾片1 係藉經由 沒極塾片103和延伸自閘極墊片1〇2的閘極指狀物102a之 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） 經濟部中央標準局員工消費合作社印製 519708 A7 _Μι 7 五、發明説— 遠端之間的一個源極路徑104b而相連。汲極指狀物103a 係於源極路徑1〇4b上伸展而穿過架空線1〇5。 兩個源極指狀物104a係從源極路徑1〇4b伸出而配置 在為閘極指狀物l〇2a所隔的兩個剩餘區域之間。兩條連接 線106經由焊球1〇7連接每一閘極墊片和汲極墊片 103。兩個源極墊片1〇4則分別有兩條連接線1〇6經由焊 球107連接，而構成總共四條焊線1〇6。 在本實施例中，汲極指狀物1〇3&係以架空線構成。然 而，源極路徑1〇4b亦可以架空線構成。除了架空線1〇5， 父叉線亦得以利用，其係以一絕緣層隔開一上繞線和一下 繞線。 (第三實施例） 第3圖係依照本發明第三實施例一低雜訊微波電晶體 之基本圖樣，其中之標號係等效於第1圖所繪之相對部 份’而其詳細說明乃予以省略。在本實施例中，如第3圖 所示’閘極指狀物l〇2a的間隔大小與焊接線106和焊球 107的尺寸並不改變，但其他部份則變小，以致柱ι〇1的 大小約減半。與第1圖和第2圖相較，兩個源極墊片1〇4 的位置係為閘極墊片102和汲極墊片1〇3所取代，而如第3 圖所示。 據此，當閘極墊片102和汲極墊片1〇3分別置於一對 角線兩端之角落，而兩個源極墊片1〇4分別置於另一對角 線兩端之兩個角落上，就已足夠。因此配置方式，閘極墊 片102和汲極墊片1〇3可有較傳統方式更大的面積，在相 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^--.---- (請先閱讀背面之注意事項再填寫本頁) 、1Τ 519708 A7 B7 五、發明説明（6 ) 同的源極墊片104尺寸之下。換言之，若閘極墊片102和 汲極墊片103有相同的面積，柱101可以有此傳統方式更 小的尺寸，於是柱101的尺寸就可以縮小化。 如上所述，依照本發明，閘極墊片和汲極墊片的尺寸 可以做得比傳統方式還大，其係將閘極、源極和汲極墊片 分別配置在柱的四個角落。因此，焊接不準的容忍量就可 以提高，以致焊接失敗率降低，而產能得以提昇。據此， 柱的尺寸可做得比傳統的柱還要小。 ------1. I·I -- (請先閱讀背面之注意事項再填寫本頁)
、1T 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐）

Claims (1)

  1. 519708 A8 B8 C8 D8 六、申請專利範圍 1. 一種半導體裝置，包括： 一矩形柱（101)，含一第一和一第二對角線； 一閘極墊片（102)，位於該柱之第一對角線兩端之一之 角落上； 一汲極墊片（103)，位於該柱之第一對角線之另一端之 角落上； 一對源極墊片（104)，位於該柱之第二對角線兩端之角 落上；以及 一源極路徑（104b)，用以連接該二源極墊片。 2. 如申請專利範圍第1項所述之半導體裝置，更包括： 複數個梳狀閘極指狀物（102a)，從該閘極墊片伸出， 而置於該柱之中央部份； 汲極指狀物（103a)，從該汲極墊片伸出，而位於該閘 極指狀物所隔之複數區域當中；以及 一源極指狀物（104a)，從該源極路徑伸出，而位於該 閘極指狀物所隔之複數區域之剩餘區域之中； 其中，該閘極指狀物、該汲極指狀物和該源極指狀物 係與該源極路徑電性隔離。 3. 如申請專利範圍第2項所述之半導體裝置，其中該 源極路徑係位於該閘極墊片和從該汲極墊片伸出之該汲極 指狀物之遠端之間，而穿過該閘極指狀物。 4. 如申請專利範圍第3項所述之半導體裝置，其中在 該源極路徑和該閘極指狀物之交叉部份，該源極路徑和該 閘極指狀物之一係架空線。 10 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ：------- (請先閱讀背面之注意事項再填寫本頁) 、τ 經濟部中央標準局員工消費合作社印製 519708 A8 B8 C8 D8 々、申請專利範圍 5. 如申請專利範圍第3項所述之半導體裝置，其中在 該源極路徑和該汲極指狀物之交叉部份，該源極路徑和該 閘極指狀物係經一絕緣層交叉繞線。 6. 如申請專利範圍第2項所述之半導體裝置，其中該 源極路徑係位於該汲極墊片和從該閘極墊片伸出之該閘極 指狀物遠端之間，而穿過該汲極指狀物。 7. 如申請專利範圍第6項所述之半導體裝置，其中在 該源極路徑和該汲極指狀物之交叉部份，該源極路徑和該 閘極指狀物其中之一係架空線。 8. 如申請專利範圍第6項所述之半導體裝置，其中在 源極路徑和該汲極指狀物之交叉部份，該源極路徑和該閘 極指狀物係經由一絕緣層交叉繞線。 9. 如申請專利範圍第1項所述之半導體裝置，更包括 複數係由該閘極、汲極和源極經由焊球伸出之焊接線，而 具有既定之形狀。 (請先閲讀背面之注意事項再填寫本頁) 、τ 經濟部中央標準局員工消費合作社印製 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐）
TW086108833A 1996-07-04 1997-06-24 Semiconductor device TW519708B (en)

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JPH11195973A (ja) * 1998-01-07 1999-07-21 Oki Electric Ind Co Ltd 半導体装置及びそれを用いた双方向光ｍｏｓリレー
US6373143B1 (en) * 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
JP2003007727A (ja) * 2001-06-22 2003-01-10 Sanyo Electric Co Ltd 化合物半導体装置
US6774416B2 (en) 2001-07-16 2004-08-10 Nanowave, Inc Small area cascode FET structure operating at mm-wave frequencies
US7994632B2 (en) * 2006-01-10 2011-08-09 International Rectifier Corporation Interdigitated conductive lead frame or laminate lead frame for GaN die

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JPS566476A (en) * 1979-06-28 1981-01-23 Nec Corp Ultrahigh frequency field effect transistor
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DE69010546T2 (de) * 1989-04-17 1995-02-09 Matsushita Electric Ind Co Ltd Hochfrequenz-Halbleiteranordnung.
JP2822739B2 (ja) * 1992-01-21 1998-11-11 日本電気株式会社 半導体装置
JPH05315369A (ja) * 1992-05-08 1993-11-26 Sharp Corp 高周波用半導体装置
JP2576773B2 (ja) * 1993-10-29 1997-01-29 日本電気株式会社 マルチフィンガー型電界効果トランジスタ
US5554881A (en) * 1993-12-17 1996-09-10 Nippondenso Co., Ltd. Constitution of an electrode arrangement in a semiconductor element
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