484223 6961twfdoc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（I ) 本發明是有關於一種晶片上具有導腳構裝，且特別 是有關於一種導腳之打線尖端部份的排列形式，使得導棒 架可以容納晶片上更多的焊墊與導腳電性連接。 在現今資訊爆炸的世界，積體電路已與日常生活有 密不可分的關係，無論在食衣住行育樂方面，都常會用到 積體電路元件所組成之產品。隨著電子科技的不斷演進， 更人性化、功能性更複雜之電子產品不斷推陳佈新，然而 各種產品無不朝向輕、薄、短、小的趨勢設計，以提供更 便利舒適的使用。 在電子構裝的領域中，晶片上有導腳（Lead On Chip，L0C)的封裝形式係爲一般常見的封裝形式，L0C封 裝形式是少數能通過JEDEC國際組織認證爲第一等級的 (level 1)封裝，其封裝形式是透過貼帶或其他非導電性 黏著材質，將導線架貼附於晶片的主動表面上，並藉由導 線使晶片之焊墊（die pad)與導線架之導腳電性連接，而 一封裝材料包覆晶片與導腳。上述之L0C結構具有導線路 徑短、封裝面積小等優點、並且不易發生剝離 (delamination)的情形，因而具有較佳的可靠度 (reliability)及電性效能（electrical performance)。 然而，在半導體製程上，已邁入〇·18微米線寬的 積體電路量產時代，晶片的體積可以大幅地縮小，並且由 於電子元件的多功能整合，使得在單一晶片中作爲輸入/ 輸出接點之焊墊（die pad)的數目會顯著地增加。就晶片 上具有導腳（L0C)的封裝形式而言，必須要克服在極小的 3 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） — — — — — — — — — — — — I· . I I (請先閱讀背面之注意事項ml寫本頁) 訂· Ϊ線- 484223 6961twfdoc/006 A7 B7 五、發明說明（l ) 晶片上容納更多的導腳之問題。以記憶體之LOC封裝爲例’ 習知所用的導線架之導腳數目爲54個，然而應用在未來 的記憶體晶片上已不敷使用，必須開發更高導腳數目的導 線架，但是以目前導線架製造技術而言，導腳間距（Pitch) 的極限僅約能達0.22密爾，在此限制下導線架之導腳配 置型態必須有所變更，使得在晶片之主動表面上才可以允 許更高腳數導腳的導線架。 經濟部智慧財產局員工消費合作社印製 ---------------- (請先閱讀背面之注意事項寫本頁) ·-線· 請參照第1圖，其繪示習知晶片上有導腳構裝製程 的俯視示意圖。首先提供一導線架110，導線架110具有 多個導腳120、多個導流板130，導腳120分別排列於導 線架110的左、右兩側，而導流板130置於導線架110的 上、下兩側。每一導腳120具有一打線尖端部份122與一 外導腳部份部份124，而打線尖端部份122分別朝向導線 架110的中間區域，縱向排列於導線架11〇中間區域的左、 右兩側。還要提供一晶片150，晶片150具有一主動表面 152，在主動表面152的表層還具有多個焊墊154，其中焊 墊154以雙排縱向排列於晶片150之主動表面152的中央 區域。接下來，進行一晶片貼合之製程，透過多個貼帶1〇2 將導線架110貼覆於晶片150之主動表面152上。然後進 行一電性連接之製程，採用打導線的方式，藉由多個導線 104使焊墊154與打線尖端部份122電性連接。接下來進 行一封膠之製程，一封裝材料106包覆晶片15〇、打線尖 端部份122、焊墊154、導線1〇4、導流板13〇，而暴露出 外導腳邰份部份124。最後進行一剪切成型的製程，使外 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱"7 484223 6961twfdoc/006 A7 B7 五、發明說明（$ ) 導腳部份部份124彎折成]型腳型態或海鷗型（guU wing type)腳型態。 經濟部智慧財產局員工消費合作社印製 在上述習知晶片上有導腳構裝中，、由於打線尖端部 、份分別朝向導線架的中間區域，並且僅縱向排列於導線架 中間區域的左、右兩側，如此在面對晶片體積逐漸縮小的 趨勢下，晶片之主動表面上將難以容納具有更高腳數導線 架的打線尖端部份。 ‘ 因此本發明的目的就是在提供一種晶片上具有導腳 構裝，可以容許更高腳數導線架之打線尖端部份貼附於晶 片之主動表面上並與其焊墊電性連接。 爲達成本發明之上述和其他目的，提出一種晶片上 具有導腳構裝，其包括：一導線架，具有多個第一導腳與 多個第二導腳，其中每一第一導腳之一端爲一第一打線尖 端部份，另一端爲一第一外導腳部份，而每一第二導腳之 一端爲一第二打線尖端部份，另一端爲一第二外導腳部 份。其中第一打線尖端部份與第二打線尖端部份朝向導線 架之中央延伸，圍繞一約略長方形區域，其中此約略長方 形區域具有二長對邊及垂直對應之二短對邊。並且，第一 外導腳部份及第二外導腳部份以垂直於二長對邊的方向朝 導線架之外圍延伸，而第一打線尖端部份配置於二長對 邊’且其延伸方向垂直於此二長對邊，另外第二導腳配置 於約略長方形區域的四個角落，第二打線尖端部份配置於 一短對邊，且其延伸方向垂直於此二短對邊。一晶片，具 有一主動表面，在晶片之主動表面的表層還具有多個焊 5 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閲讀背面之注意事 裝— :寫本頁) . · --線. 484223 6 9 6 1twfdo c/〇 〇 6 Α7 _____Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（+) 墊’並且第一打線尖端部分及第二打線尖端部分貼附於晶 片之主動表面上，而第一導腳、第二導腳與焊墊電性連通。 以及一封裝材料，封裝材料包覆第一打線尖端部份、第二 打線尖端部份、晶片、焊墊，並且暴露出第一外導腳部份 與第二外導腳部份。 依照本發明的一較佳實施例，其中焊墊以雙排或單 排縱向排列於晶片之主動表面的中間區域。另外藉由多個 第一導線使第一導腳與對應之焊墊電性連接，而透過多個 線使第二導腳與對應之焊墊電性連接，而第二導線可以連 接至第二打線尖端部份或遠離第二打線尖端部份之第二導 腳處，並且第二導線之至少一個橫越過第二導腳之至少一 個。此外，晶片係藉由多個貼帶貼附於第一導腳上與第二 導腳上，而貼帶之至少一個係爲L型之形狀。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例’並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知晶片上有導腳構裝製程的俯視示意 圖。 第2圖至第4圖繪示依照本發明第一較佳實施例的 一種晶片上具有導腳構裝之製程剖面示意圖。 第2A圖繪示對應於第2圖中導線架之俯視示意圖。 第2B圖繪示對應於第2圖之俯視示意圖。 第4A圖繪示對應於第4圖之俯視示意圖。 6 (請先閱讀背面之注意事 項肇 寫本頁) 言 r 良 ΡΓ張尺度刺+目(CNS)A4規格（210 X 297公釐） 484223 6961twfd< :/006 A7 B7 五、發明說明（f) 第4B圖繪示依照本發明第二較佳實施例對應於第4 圖之俯視示意圖。 圖式之標示說明： 110、210 :導線架 120 :導腳 122 :打線尖端部份 124 :外導腳部份部份 130、250 ··導流板 220 :第一導腳 222 :第一打線尖端部份 224 :第一外導腳部份部份 230 :第二導腳 232 :第二打線尖端部份 234 :第二外導腳部份部份 240 :約略長方形區域 242 :長對邊 244 :短對邊 150、260 :晶片 152、262 :主動表面 154、264 :焊墊 102、202 ··貼帶 104 :導線 270 :第一導線 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） --------------- (請先閲讀背面之注意事項寫本頁： r -1矣· 經濟部智慧財產局員工消費合作社印製 484223 6 9 6 1 twfdo c/ 0 0 6 八7 ---B7____ 五、發明說明（厶） 280 :第二導線 290:模具 292 :模穴 106、204 ·•封裝材料 實施例 請參照第2圖至第4圖，其繪示依照本發明第一較 佳實施例的一種晶片上具有導腳構裝之製程剖面示意圖。 而導線架的導腳數目可以爲86個，一般常用於記憶體的 構裝。 經濟部智慧財產局員工消費合作社印製 • ml — — — — — — — —— · I I (請先閱讀背面之注意事寫本頁) 線· 請先參照第2圖以及第2A圖，其中第2A圖繪示對 應於第2圖中導線架之俯視示意圖。如第2A圖所示，首 先提供一導線架210，導線架210包括多個第一導腳220、 多個第二導腳230、多個導流板250。每一第一導腳220 之一端係爲一第一打線尖端部份222,而另一端係爲一第 一外導腳部份224 ;每一第二導腳230之一端係爲一第二 打線尖端部份232，而另一端係爲一第二外導腳部份234。 並且第一導腳220及第二導腳230排列於導線架210之左、 右兩側，而導流板250置於導線架210之上、下兩側。其 中第一打線尖端部份222與第二打線尖端部份232朝向導 線架之中央延伸，圍繞一約略長方形區域240，而此約略 長方形區域240具有二長對邊242以及垂直對應之二短對 邊244。並且第一外導腳部份224及第二外導腳部份234 以垂直於二長對邊242的方向朝導線架210之外圍延伸， 而第一打線尖端部份222配置於二長對邊242 ’且其延伸 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484223 6961twfdoc/006 A7 B7 五、發明說明（η ) --------------裝--- (請先閱讀背面之注意事項寫本頁) 方向垂直於二長對邊242，另外，第二導腳230配置於約 略長方形區域240的四個角落，第二打線尖端部份232則 配置於二短對邊244，且其延伸方向垂直於二短對邊244 ; 言f參照第2圖、第2B圖，其中第2B圖繪示對應於 第2圖之俯視示意圖。然後還要提供一晶片260，晶片260 具有一主動表面262 ’晶片260之主動表面262的表層還 具有多個焊墊264，而焊墊264雙排縱向排列於晶片260 之主動表面262的中間區域。然而本發明並非侷限於上述 的方式，焊墊亦可以單排或多排縱向排列於晶片之主動表 面的中間區域。 --線· 接下來進行一晶片黏貼之製程，藉由多個貼帶202 將導線架210貼附於晶片260之主動表面262上，而貼帶 202係爲L型的形狀。然後進行一電性連接之製程，採用 打導線的方式，藉由多個第一導線270使第一打線尖端部 份222與晶片260之焊墊264電性連接，並且透過多個第 二導線280使第二打線尖端部份232與晶片260之焊墊264 電性連接。 經濟部智慧財產局員工消費合作社印製 請參照第3圖、第2B圖，然後進行一封膠製程， 使用一模具290，模具290具有一模穴292，將晶片260、 第一打線尖端部份222、第二打線尖端部份232、第一導 線270、第二導線280放入模穴292中，模具290夾持住 第一導腳220、第二導腳230,並灌入熔融的一封裝材料（未 繪示）於模穴中292，然後進行固化、脫膜的步驟，而獲得 如第4圖的結構。 9 度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484223 6961twfdoc/006 A7 B7 五、發明說明（s) 請爹照第4圖、第4A圖，其中第4A圖繪示對應於 第4圖之俯視示意圖。一封裝材料204包覆第一打線尖端 部份222、第二打線尖端部份232、晶片260、焊墊264、 第一導缚270、桌一導線280，並且封裝材料2Q4暴露出 第一外導腳部份224、第二外導腳部份234。然後進行一 剪切成型之製程’採用衝壓的方式將第一外導腳部份224、 第一外導腳部份234壓成海_型（gUii wing type)導腳的 形式或]型腳的形式。 在上述之構裝中，由於在本發明之導線架中，第二 導腳230之第二打線尖端部份232還可以橫向排列貼附於 晶片260之主動表面262的上、下兩側，因此可以容許更 高腳數導線架210之打線尖端部份222、232貼附於晶片260 之主動表面262上，並與其焊墊264電性連接。 請參照第4B圖，其繪示依照本發明第二較佳實施 例對應於第4圖之俯視示意圖。在前述的第一較佳實施例 中，第二導線280連接至第二打線尖端部份232，然而本 發明並非侷限於上述之方式，亦可以將第二導線280連接 至遠離第二打線尖端部份232之第二導腳230處，並且第 二導線280還橫越過第二打線尖端部份232。 經濟部智慧財產局員工消費合作社印製 --------------裝i — (請先閱讀背面之注意事寫本頁) --線- 綜上所述，本發明之晶片上具有導腳構裝及其製程 θ以將第二導腳之第二打線尖端部份橫向排列貼附於晶片 之主動表面的上、下兩側，且其與長對邊垂直，因此可容 許更高腳數導線架之打線尖端部份貼附於晶片之主動表面 上，並與其焊墊電性連因此，本發明之構裝結構適於 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484223 6961twfdoc/006 A7 _B7_ 五、發明說明（q ) 應用於未來高積集度及較高腳位的晶片上具有導腳構裝。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和1¾圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。. --------------裝— (請先閱讀背面之注意事寫本頁) 訂： •線. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）484223 6961twfdoc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (I) The present invention relates to a chip with a guide pin structure, and in particular to a wire tip of a guide pin. The arrangement form allows the guide bar holder to accommodate more solder pads on the wafer and be electrically connected to the guide pins. In today's world of information explosion, integrated circuits have an inseparable relationship with daily life. Regardless of food, clothing, living, travel and entertainment, products composed of integrated circuit components are often used. With the continuous evolution of electronic technology, more humane and more complex electronic products are constantly being introduced. However, all products are designed to be light, thin, short, and small to provide more convenient and comfortable use. In the field of electronic assembly, the package with lead on chip (L0C) is a common package, and the L0C package is one of the few that can be certified by the JEDEC international organization as the first level (level 1). ) Package, the package form is to attach the lead frame to the active surface of the chip through a tape or other non-conductive adhesive material, and electrically conductive the die pad of the chip and the lead of the lead frame through the wire. The chip and the guide pin are covered by a packaging material. The above-mentioned L0C structure has the advantages of short conductive path diameter, small package area, and the like, and is not prone to delamination. Therefore, it has better reliability and electrical performance. However, in the semiconductor manufacturing process, it has entered the era of mass production of integrated circuits with a width of 18 microns, and the size of the chip can be greatly reduced. Due to the multi-functional integration of electronic components, it can be used as input / output in a single chip. The number of die pads of the contacts will increase significantly. As for the package with the lead pin (L0C) on the wafer, it must be overcome that the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) is applicable in the smallest 3 paper sizes — — — — — — — — — — — — I ·. II (please read the precautions on the back to write this page first) Order · Coil wire-484223 6961twfdoc / 006 A7 B7 5. Description of the invention (l) The problem of more guide pins on the chip. Take the LOC package of memory as an example. The number of lead pins used in the conventional lead frame is 54. However, it will not be used in future memory chips. A lead frame with a higher number of lead pins must be developed. In terms of current leadframe manufacturing technology, the limit of the pitch of the leadframe can only reach about 0.22 mils. Under this limit, the configuration of the leadframe of the leadframe must be changed so that it can be used on the active surface of the chip. Lead frame for higher pin count. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --- (Please read the precautions on the back and write this page first) · -line · Please refer to Figure 1, which is drawn A schematic plan view of a guide pin assembly process on a conventional wafer is shown. First, a lead frame 110 is provided. The lead frame 110 has a plurality of guide legs 120 and a plurality of deflectors 130. The guide legs 120 are respectively arranged on the left and right sides of the lead frame 110, and the deflector 130 is disposed on the lead frame 110. The upper and lower sides. Each guide pin 120 has a wire guide tip portion 122 and an outer guide pin portion portion 124, and the wire guide tip portions 122 respectively face the middle area of the lead frame 110 and are longitudinally arranged at the left and right sides of the middle area of the lead frame 110. Right sides. A wafer 150 is also provided. The wafer 150 has an active surface 152, and a plurality of pads 154 are also provided on the surface of the active surface 152. The pads 154 are longitudinally arranged in a double row in the central area of the active surface 152 of the wafer 150. Next, a wafer bonding process is performed, and the lead frame 110 is pasted on the active surface 152 of the chip 150 through a plurality of tapes 102. Then, an electrical connection process is performed, and the bonding pad 154 is electrically connected to the bonding wire tip portion 122 by a plurality of wires 104 by using a wire bonding method. Next, a glue process is performed. A packaging material 106 covers the wafer 150, the wire tip portion 122, the bonding pad 154, the wire 104, and the deflector 130, and the outer guide pin portion 124 is exposed. . Finally, a shear forming process is performed to make the outer 4 paper sizes applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 Public Love " 7 484223 6961twfdoc / 006 A7 B7. 5. Description of the invention ($) Guide feet Part 124 is bent into a foot type or a guU wing type. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed a guide pin structure on the conventional chip. The parts and parts respectively face the middle area of the lead frame, and are arranged longitudinally on the left and right sides of the middle area of the lead frame. Therefore, in the face of the gradual shrinking of the wafer volume, the active surface of the wafer will be difficult to accommodate higher The pin tip portion of the pin count lead frame. Therefore, the object of the present invention is to provide a chip with a guide pin structure, which can allow the pin tip portion of a higher pin lead frame to be attached to the active surface of the chip and To achieve the above and other objects of the present invention, a chip with a guide pin structure is provided, which includes: a lead frame having a plurality of first guide pins and a plurality of first pins. Guide pins, where one end of each first guide pin is a first wire tip portion, the other end is a first outer guide pin portion, and one end of each second guide pin is a second wire tip portion , The other end is a second outer guide leg portion, wherein the first wire-tipped tip portion and the second wire-tipped tip portion extend toward the center of the lead frame and surround a roughly rectangular area, where the roughly rectangular area has two long opposite sides And the two short opposite sides corresponding to the vertical. Moreover, the first outer guide leg portion and the second outer guide leg portion extend toward the periphery of the lead frame in a direction perpendicular to the two long opposite sides, and the first wire tip portion is configured In the two long opposite sides' and its extending direction is perpendicular to the two long opposite sides, in addition, the second guide pin is arranged at the four corners of the approximately rectangular area, and the second wire drawing tip portion is arranged at a short opposite side, and its extending direction It is perpendicular to the two short opposite edges. A wafer has an active surface, and the surface of the active surface of the wafer also has multiple welds. 5 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm). Please read the note on the back first (Establishment:: write this page). ·-Line. 484223 6 9 6 1twfdo c / 〇〇6 Α7 _____ Β7 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 5. Description of the invention (+) pads and the first tip Part and the second wire bonding tip are attached to the active surface of the chip, and the first and second lead pins are in electrical communication with the solder pads; and a packaging material covering the first wire bonding tip part, the Two wire tips, wafers, and solder pads, and exposed the first outer guide pin portion and the second outer guide pin portion. According to a preferred embodiment of the present invention, the pads are arranged in a double or single row longitudinally. It is arranged in the middle area of the active surface of the chip. In addition, the first lead is electrically connected to the corresponding pad by a plurality of first wires, and the second lead is electrically connected to the corresponding pad by a plurality of wires. The second wire can be connected to the second wire tip portion or a second guide pin away from the second wire tip portion, and at least one of the second wire crosses at least one of the second wire pin. In addition, the chip is attached to the first guide pin and the second guide pin by a plurality of tapes, and at least one of the tapes is L-shaped. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: FIG. 1 A schematic plan view of a guide pin assembly process on a conventional wafer is shown. FIG. 2 to FIG. 4 are schematic cross-sectional views of a manufacturing process with a guide pin structure on a wafer according to a first preferred embodiment of the present invention. FIG. 2A is a schematic top view corresponding to the lead frame in FIG. 2. FIG. 2B is a schematic plan view corresponding to FIG. 2. FIG. 4A is a schematic plan view corresponding to FIG. 4. 6 (Please read the note on the back first and write this page) rr Good PΓ Zhang scale thorn + mesh (CNS) A4 specification (210 X 297 mm) 484223 6961twfd <: / 006 A7 B7 V. Description of the invention (f) FIG. 4B is a schematic plan view corresponding to FIG. 4 according to the second preferred embodiment of the present invention. Description of the diagrams: 110, 210: lead frame 120: guide pin 122: wire tip portion 124: outer guide pin portion 130, 250 · deflector 220: first guide pin 222: first wire Tip portion 224: first outer guide leg portion 230: second guide leg 232: second wire guide tip portion 234: second outer guide leg portion 240: approximately rectangular area 242: long opposite sides 244 : Short side edges 150, 260: Wafers 152, 262: Active surfaces 154, 264: Pads 102, 202 ·· Strips 104: Conductor 270: First conductor This paper is sized for China National Standard (CNS) A4 (210 χ 297 mm) --------------- (Please read the notes on the back first to write this page: r -1 矣 · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484223 6 9 6 1 twfdo c / 0 0 6 8 7 --- B7____ V. Description of the invention (厶) 280: Second wire 290: Mould 292: Mould cavity 106, 204 • For examples of packaging materials, please refer to Figures 2 to 4 FIG. Shows a schematic cross-sectional view of a manufacturing process with a guide pin structure on a wafer according to the first preferred embodiment of the present invention. The number of guide pins of a lead frame can be 86, Generally used for the construction of memory. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • ml — — — — — — — — II (Please read the notes on the back first to write this page) Line · Please refer to the first 2 and FIG. 2A, wherein FIG. 2A shows a schematic plan view corresponding to the lead frame in FIG. 2. As shown in FIG. 2A, a lead frame 210 is first provided, and the lead frame 210 includes a plurality of first guide pins 220. A plurality of second guide pins 230 and a plurality of deflectors 250. One end of each first guide pin 220 is a first wire tip portion 222, and the other end is a first outer guide pin portion 224 One end of each second guide pin 230 is a second wire tip portion 232, and the other end is a second outer guide pin portion 234. The first guide pin 220 and the second guide pin 230 are arranged at The left and right sides of the lead frame 210, and the deflectors 250 are placed above and below the lead frame 210. The first wire drawing tip portion 222 and the second wire drawing tip portion 232 extend toward the center of the wire frame. A substantially rectangular area 240 is surrounded, and the approximately rectangular area 240 has two long opposite sides 242 and a vertical Corresponding to the two short opposite sides 244. And the first outer guide leg portion 224 and the second outer guide leg portion 234 extend in a direction perpendicular to the two long opposite sides 242 toward the periphery of the lead frame 210, and the first wire drawing tip portion Copies 222 are arranged on the two long opposite sides 242 'and its extension 8 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 484223 6961twfdoc / 006 A7 B7 V. Description of the invention (η) ---- ---------- Install --- (Please read the notes on the back first to write this page) The direction is perpendicular to the two long opposite sides 242. In addition, the second guide leg 230 is arranged on the four sides of the approximately rectangular area 240. Corners, the second wire-tipped tip portion 232 is disposed on the second short-opposite side 244, and its extending direction is perpendicular to the second short-opposite side 244; refer to FIG. 2 and FIG. 2B, where FIG. Figure 2 is a schematic plan view. Then, a wafer 260 is provided. The wafer 260 has an active surface 262. The surface of the active surface 262 of the wafer 260 also has a plurality of pads 264, and the pads 264 are arranged in two rows in a longitudinal direction in the middle area of the active surface 262 of the wafer 260. . However, the present invention is not limited to the above-mentioned manner, and the pads may also be arranged in a single row or multiple rows in the middle region of the active surface of the wafer in the longitudinal direction. -Line · Next, a wafer sticking process is performed. The lead frame 210 is attached to the active surface 262 of the wafer 260 by a plurality of sticking tapes 202, and the sticking tapes 202 are L-shaped. Then, an electrical connection process is performed, and the first wire tip portion 222 is electrically connected to the bonding pad 264 of the chip 260 by a plurality of first wires 270 through a plurality of first wires 270, and a plurality of second wires 280 are passed through The second wire bonding tip portion 232 is electrically connected to the bonding pad 264 of the chip 260. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 3 and Figure 2B, and then perform a glue process. A mold 290 is used, and the mold 290 has a cavity 292. The chip 260 and the first wire tip 222, the second wire tip portion 232, the first wire 270, and the second wire 280 are placed in the cavity 292, and the mold 290 clamps the first guide leg 220 and the second guide leg 230, and is poured into a molten package. The material (not shown) is placed in the cavity 292, and then the steps of curing and removing the film are performed to obtain the structure as shown in FIG. 4. 9 degrees applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 484223 6961twfdoc / 006 A7 B7 V. Description of the invention (s) Please refer to Figure 4 and Figure 4A, where Figure 4A shows the corresponding Figure 4 is a schematic plan view. A packaging material 204 covers the first wiring tip portion 222, the second wiring tip portion 232, the chip 260, the bonding pad 264, the first guide 270, and the table-first wire 280, and the packaging material 2Q4 exposes the first outer conductor. The leg portion 224 and the second outer guide leg portion 234. Then, a shear molding process is performed. The first outer guide leg portion 224 and the first outer guide leg portion 234 are pressed into a sea-shaped (gUii wing type) guide foot form or a] -shaped foot form by stamping. . In the above-mentioned configuration, in the lead frame of the present invention, the second wire-tip tip portion 232 of the second guide pin 230 can also be horizontally arranged and attached to the upper and lower sides of the active surface 262 of the chip 260, so It is allowable that the wire-tipped tip portions 222 and 232 of the higher-pin lead frame 210 are attached to the active surface 262 of the chip 260 and electrically connected to the bonding pad 264 thereof. Please refer to FIG. 4B, which is a schematic plan view corresponding to FIG. 4 according to the second preferred embodiment of the present invention. In the aforementioned first preferred embodiment, the second wire 280 is connected to the second wire tip portion 232. However, the present invention is not limited to the above-mentioned manner, and the second wire 280 can also be connected far from the second wire tip portion. The second guide pin 230 of the portion 232 and the second wire 280 also cross the second wire tip portion 232. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------------- install i-(Please read the note on the back first to write this page)-Line-In summary, the present invention The wafer has a guide pin structure and a process θ for laterally aligning and attaching the second wire tip portion of the second guide pin to the upper and lower sides of the active surface of the wafer, and it is perpendicular to the long opposite side, so Allows the higher-pin lead frame to be attached to the active surface of the chip and electrically connected to its pads. Therefore, the structure of the present invention is suitable for the paper size and applicable to China National Standard (CNS) A4 Specifications (210 X 297 mm) 484223 6961twfdoc / 006 A7 _B7_ V. Description of the invention (q) It will be applied to a chip with a high pin density and a higher pin position in the future. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. -------------- Installation— (Please read the note on the back to write this page) Order: • Thread. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Standard (CNS) A4 specification (210 X 297 mm)