TW516077B - Method of creating design rule, design rule creating system, and recording medium - Google Patents

Method of creating design rule, design rule creating system, and recording medium Download PDF

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Publication number
TW516077B
TW516077B TW090115957A TW90115957A TW516077B TW 516077 B TW516077 B TW 516077B TW 090115957 A TW090115957 A TW 090115957A TW 90115957 A TW90115957 A TW 90115957A TW 516077 B TW516077 B TW 516077B
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TW
Taiwan
Prior art keywords
design
prediction
design rule
compression
completed shape
Prior art date
Application number
TW090115957A
Other languages
English (en)
Chinese (zh)
Inventor
Toshiya Kotani
Satoshi Tanaka
Soichi Inoue
Original Assignee
Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
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Publication of TW516077B publication Critical patent/TW516077B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
TW090115957A 2000-06-30 2001-06-29 Method of creating design rule, design rule creating system, and recording medium TW516077B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000199839A JP4077141B2 (ja) 2000-06-30 2000-06-30 デザインルール作成方法、デザインルール作成システム及び記録媒体

Publications (1)

Publication Number Publication Date
TW516077B true TW516077B (en) 2003-01-01

Family

ID=18697788

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090115957A TW516077B (en) 2000-06-30 2001-06-29 Method of creating design rule, design rule creating system, and recording medium

Country Status (4)

Country Link
US (4) US6507931B2 (https=)
JP (1) JP4077141B2 (https=)
KR (1) KR100437980B1 (https=)
TW (1) TW516077B (https=)

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US7886564B2 (en) 2004-09-10 2011-02-15 Nippon Steel Corporation System, method, software arrangement and computer-accessible medium for press-forming of materials
TWI393172B (zh) * 2007-12-20 2013-04-11 Fujitsu Semiconductor Ltd 半導體裝置、用於製造半導體裝置之方法及電腦可讀取媒體

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JP4077141B2 (ja) * 2000-06-30 2008-04-16 株式会社東芝 デザインルール作成方法、デザインルール作成システム及び記録媒体
JP2002368093A (ja) * 2001-06-12 2002-12-20 Mitsubishi Electric Corp レイアウト生成装置、レイアウト生成方法およびプログラム
TWI252516B (en) 2002-03-12 2006-04-01 Toshiba Corp Determination method of process parameter and method for determining at least one of process parameter and design rule
JP2003345854A (ja) * 2002-05-23 2003-12-05 Mitsubishi Electric Corp デザインルール作成システム
US7117456B2 (en) * 2003-12-03 2006-10-03 International Business Machines Corporation Circuit area minimization using scaling
JP2005181523A (ja) 2003-12-17 2005-07-07 Toshiba Corp 設計パターン補正方法、マスクパターン作成方法、半導体装置の製造方法、設計パターン補正システム、及び設計パターン補正プログラム
JP4488727B2 (ja) 2003-12-17 2010-06-23 株式会社東芝 設計レイアウト作成方法、設計レイアウト作成システム、マスクの製造方法、半導体装置の製造方法、及び設計レイアウト作成プログラム
JP4357287B2 (ja) 2003-12-18 2009-11-04 株式会社東芝 修正指針の発生方法、パターン作成方法、マスクの製造方法、半導体装置の製造方法及びプログラム
WO2005098686A2 (en) * 2004-04-02 2005-10-20 Clear Shape Technologies, Inc. Modeling resolution enhancement processes in integrated circuit fabrication
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
JP2006053248A (ja) * 2004-08-10 2006-02-23 Toshiba Corp 設計パターンデータ作成方法、マスクパターンデータ作成方法、マスク製造方法、半導体装置の方法およびプログラム
JP4817746B2 (ja) * 2005-07-27 2011-11-16 株式会社東芝 半導体装置の設計データ処理方法、そのプログラム、及び半導体装置の製造方法
US20070074142A1 (en) * 2005-09-27 2007-03-29 Applied Materials, Inc. Integrated circuit layout methods
US7934184B2 (en) * 2005-11-14 2011-04-26 Takumi Technology Corporation Integrated circuit design using modified cells
US7568179B1 (en) 2006-09-21 2009-07-28 Armen Kroyan Layout printability optimization method and system
JP4745256B2 (ja) 2007-01-26 2011-08-10 株式会社東芝 パターン作成方法、パターン作成・検証プログラム、および半導体装置の製造方法
US8010912B2 (en) * 2007-03-09 2011-08-30 Broadcom Corporation Method of shrinking semiconductor mask features for process improvement
JP4891817B2 (ja) * 2007-03-16 2012-03-07 株式会社日立製作所 設計ルール管理方法、設計ルール管理プログラム、ルール構築装置およびルールチェック装置
KR100898232B1 (ko) * 2007-09-03 2009-05-18 주식회사 동부하이텍 축소과정에서의 패턴 설계 방법
JP2009290150A (ja) * 2008-06-02 2009-12-10 Renesas Technology Corp 半導体装置の製造システムおよび製造方法
US8214771B2 (en) * 2009-01-08 2012-07-03 Kla-Tencor Corporation Scatterometry metrology target design optimization
KR101044295B1 (ko) * 2010-01-07 2011-06-28 주식회사 엔타시스 자동화된 칩 면적 최적화를 위한 블록 패킹방법 및 표준 셀 패킹 방법
US20150067621A1 (en) * 2012-09-05 2015-03-05 Mentor Graphics Corporation Logic-Driven Layout Pattern Analysis
KR102227127B1 (ko) 2014-02-12 2021-03-12 삼성전자주식회사 리소그래피 시뮬레이션을 이용한 디자인룰 생성 장치 및 방법
US10628544B2 (en) 2017-09-25 2020-04-21 International Business Machines Corporation Optimizing integrated circuit designs based on interactions between multiple integration design rules
US11023648B2 (en) 2017-12-12 2021-06-01 Siemens Industry Software Inc. Puzzle-based pattern analysis and classification
KR102755274B1 (ko) 2024-07-05 2025-01-22 최병렬 압축기와 반응기와 촉매제 기반 에틸렌과 프로판과 고분자 재료 혼합 복합 생산 시스템 및 그 운용방법

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JP4077141B2 (ja) * 2000-06-30 2008-04-16 株式会社東芝 デザインルール作成方法、デザインルール作成システム及び記録媒体
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7886564B2 (en) 2004-09-10 2011-02-15 Nippon Steel Corporation System, method, software arrangement and computer-accessible medium for press-forming of materials
US8091395B2 (en) 2004-09-10 2012-01-10 Nippon Steel Corporation System, method, software arrangement and computer-accessible medium for press-forming of materials
TWI393172B (zh) * 2007-12-20 2013-04-11 Fujitsu Semiconductor Ltd 半導體裝置、用於製造半導體裝置之方法及電腦可讀取媒體

Also Published As

Publication number Publication date
USRE43659E1 (en) 2012-09-11
USRE42302E1 (en) 2011-04-19
KR100437980B1 (ko) 2004-07-02
JP4077141B2 (ja) 2008-04-16
US20020002697A1 (en) 2002-01-03
USRE42294E1 (en) 2011-04-12
US6507931B2 (en) 2003-01-14
JP2002026126A (ja) 2002-01-25
KR20020002323A (ko) 2002-01-09

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