TW504753B - Method for forming a semiconductor device - Google Patents

Method for forming a semiconductor device Download PDF

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Publication number
TW504753B
TW504753B TW088112310A TW88112310A TW504753B TW 504753 B TW504753 B TW 504753B TW 088112310 A TW088112310 A TW 088112310A TW 88112310 A TW88112310 A TW 88112310A TW 504753 B TW504753 B TW 504753B
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TW
Taiwan
Prior art keywords
film
copper
forming
substrate
layer
Prior art date
Application number
TW088112310A
Other languages
English (en)
Inventor
Gregor Braeckelmann
Ramnath Venkatraman
Matthew Thomas Herrick
Cindy R Simpson
Robert W Fiordalice
Original Assignee
Motorola Inc
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Filing date
Publication date
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Application granted granted Critical
Publication of TW504753B publication Critical patent/TW504753B/zh

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    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Description

504753
五、發明說明（1) 太由咬电 A. JL專通1請案 本申凊案曾在—士士 0 9/121，068 )中提出。 月廿一日美國專利（案號 c與半導體裝置有關，並 置中的—個互聯結構及其形成的方法有關。 導體裝 發背景 積體電路持續油姑主道_ 互聯過程發展，特a电：、置製造商縮成更小的尺寸/ 的努力中一個*I聯技術是持續減少電路尺寸 路電流密度的：；；；域並：而，-互，尺寸的減少造成電 可造成電阻及可有關電子移動的問題。此 _ f電路叮罪性無法消^除的變化·。 銅目刖刻進行I呂的替抑σ 所產生的Η % ^ °σ、研九。以克服電流密度提升 的電阻率及改良的電子移動電…而憂：=:較： 使用銅作為替代ο〇σ並〗能完全、、肖/雷羊软ί *技術中 聯尺寸持續地縮小，電子移二：動的問題。當互 慮。 電子移動將持續成為一個可靠性的顧 另外，使用銅形成互聯產生了有關可 與含氧薄膜及諸如多硫亞氨等惰性聚合體的黏著‘。： 不僅在形成互聯時是一個顧慮，而且在 人广 美出有關附者的可靠性問題。其中勹扛钿壯 否區及銅結合區上惰性續· M /、匕括銅、，、口 4诠4膜之間不良附著所導致的失敗。 m 第6頁 i 504753 五、發明說明（2) 圖式簡單說明 本發明經由範例加以說明，並不侷限於附圖，其中同樣 的編號指示類似的物件。其中： 圖1包括一個半導體裝置的部分斷面圖說明，該半導體 裝置曾被部分地處理以定義一個第一互聯階層； 圖2包括在一個附著/障壁層及一個層際電介質薄膜形成 之後，一個圖1中基板的斷面圖說明； 圖3包括在該層際電介質薄膜内形成一個雙嵌入開孔之 一二― 後，一個圖2中基板的斷面圖說明；
圖4包括在該雙後入開孔内沉積一個附著/障壁層、一個 晶種層及一個傳導薄膜之後，一個.圖3中基板的斷面圖說 明； . - 圖5包括一個圖4中基板的斷面郾說明，並進一步說明一 個退火的步驟以重新分配晶種層至傳導薄膜的合金成分； 圖6包括在形成一個雙嵌入互聯結構之後，一個圖5中基 板的斷面圖說明；
圖7包括在沉積一個第二層際電介質薄膜，並形成一個 上雙嵌入開孔及一個單一嵌入開孔之後，一個圖6中基板 的斷面圖說明； 圖8包括在一個附著/障壁層、一個晶種層、一個傳導薄 膜及一個銅合金覆蓋薄膜沉積覆蓋在該雙嵌入開孔及該單 一嵌入開孔之後，一個圖7中基板的斷面圖說明； 圖9包括在形成一個雙嵌入互聯結構及一個結合區結構 之後，一個圖8中基板的斷面圖說明；
第7頁 川4753 五、發明說明（3) 圖1 〇包括在形成一個惰性薄膜及在該暴露出結合區 的惰性薄膜中形成-個開孔之後，一個圖9中基板的斷刀 圖說明； 圖11包括在形成一個大體上完整的裝備之後，一個 中基板的斷面圖說明。 q 1 u 技術純熟的人員欣賞圖中說明簡單清楚並不需按 =物件。例如’在圖中^干物件的尺寸相對於其他。 被绔大，以協助促進對於本發明的具體實施例的了解。 壁iJl之詳細說日月 … 個傳導互聯是覆蓋在一個基板上形成。在一個呈體 ^例中，-個附著/障壁層、一個銅合金晶種層及」個體銅實 4膜在遠基板上沉積並進行退火。在一個替代的呈’° 例中，一個含銅薄 ---- 八 貫知 個具體實施例Ϊ 二基上上並進行退火。在另- 难、# # T 個附者/障壁層、一個晶種層、一個 個銅合金覆蓋薄膜沉積在該基板上 呈 在一般的處理平台上執行。 人乂鄉了 八=L包括一個半導體裝置的說明，該半導體裝置曾被部 處理以定義一個第一互聯階層。曰被:一 導插頭二人 —個電晶體⑴、傳 導插頭112及一個電介質層11〇。電晶體 、-個閘電介質薄膜m及—個枯獲雜£104 ，該丰導@ _ I I j , Λ 個閘電極1 0 8。使用此種規格 Θ牛導體裝置基板丨〇包括一個單結晶 — 絕緣體上半導齅其此+ y 牛導體日日儿、一個 導體基板或任何其他用於形成一個半導體裝置 504753 五、發明說明（4) 的基板。 在-個具體實施例中，該閘電極1〇8是一個多矽層。可 替代的是閘電極1 0 8可以是一個+屬爲 曰 、 A疋個金屬層，例如鎢或鉬，可 以是一個金屬氮化物層，例氡 g. 1ΛΟ 例如鼠化欽、虱化鎢及其混合物 。另外，閘電極108可以是一個由覆蓋在一多矽薄膜上 金屬矽化物所組成的多物薄膜，例如矽化鎢、矽化鈦及矽 化錄。
在閘電極108形成之後’一個第一層際電介質層η〇在該 ，板10上形成，並定型以形成一個接觸開孔。在一個具體 ，施例中:第一層際電介質層丨丨〇是二個WTE〇s作為來源 氣體沉積氧等離子體的薄膜。可替.代的是，第一層際電介 質層110可以是一個氮化矽薄膜、一$磷矽酸鹽玻璃薄膜 、一個硼鱗矽酸鹽玻璃薄膜、一個，氮氧化矽薄膜、一個多 物薄膜、一個低介電常數電介質或其混合物。 在定型之後，一個接觸開孔便在電介質層J丨〇中形成。
該接觸開孔包括一個傳導插頭11 2，其是使用一個附著/障 壁層11 4 ’例如鈦/氮化鈦及組·/氮化鈕，及一個傳導填充 材料11 6所組成，例如鎢。沉積之後，使用傳統的蝕刻或 化學機械磨光技術將該傳導填充材料丨丨6的部分及其下面 的附著/障壁層11 4移除，以形成該傳導插頭11 2。可替代 的是’如同一個傳導填充材料具有或不具有該附著/障壁 層11 4，該傳導插頭11 2可使用攙矽加以形成。 在形成該傳導插頭11 2之後，便在該傳導插頭11 2 .及電介 質層110之上形成一個第二附著/障壁層122及一個第二傳
第9頁 JU4/53
m是H4丄個具體實施例中，該第二附著/障壁層 鋼、銘或類似：=::成，：傳導薄 第二傳形成。该苐二附著/障壁層122及該 處理過P由古t的合成形成了一個第一互聯階層1 2。在 形成該^置。到廷裡，如圖1中所顯示是使用傳統方法來 惰性：L所1V月的’接著在該第一互聯階層12上形成-個 氣心以體=體實施例中’惰性層21是-個沉積-的 沉積的氮氧化心；的是；惰性層21可以是一個 料。惰性声21 β用於：4 —個鼻化硼薄膜或類似材 性，以避低該互聯階層12中金屬原子的可能 薄膜。^ s，進入1^後在該互聯層1 2上沉.積的電介質 作為钔二t沾右互聯階層1 2由銅所'组成’那麼惰性層21便 怍為銅擴散的障壁層。 - ^ =2尚說明一個在該第二附著/障壁層122上所形成的層 二電質層2G。在—個具體實施例中，層際電介質層^。曰 括電介質薄膜22、中間蝕刻阻.止薄膜23 硬遮罩薄膜25。 |負存膜24及 電介質薄膜22可以是一個使用TE〇s作為來源氣體 沉積氧等離子體薄膜。可替代的是，電介質薄膜U可^曰 一個磷矽酸鹽玻璃薄膜、一個硼磷矽酸鹽玻璃薄膜、—广 SOG薄膜、一個低介電常數絕緣體或類似材料。詳細地…固 ，個低w電$數絕緣體是一個介電常-數約小於3 5的/ 料。中間蝕刻阻止薄膜23可以是一個沉積氮氧化矽等離才子
504753 I II ------- 五、發明說明（6) 體薄膜。可替代的是，中間餘刻阻止薄膜23可以是一個沉 積氮化矽等離子體薄膜、一個氮化硼薄獏或類似材料。電 介質薄膜以是-個以TE0S作為來源氣體以形成沉積| 等離子體的溥膜。可替代的是’電介質薄膜24可 」 磷矽酸鹽玻璃薄膜、一個硼磷矽酸鹽玻璃薄膜、一個s〇G 薄膜、一個低介電常數絕緣體或類似材料。該層際 薄膜20不需使用不同的電介值材料加以形成。例如，層際 電介質薄膜20可以使用單一電介值材料，諸如沉積氧‘二 子、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、s〇g、多硫亞 或Γ讀料。覆蓋在，介質薄二△的 疋U 體實施例中，硬遮罩薄膜25是 -個抓積W切轉子體薄膜。可# 膜25可以是-個沉積氮化石夕等離子·體薄膜、一個氮 膜或類似材料。 - w 朋存 圖3中，層際電介質薄賴及惰性層21的_部分定型以 。如圖3中所顯示’雙嵌入開孔3°包括 及一個取道部分32，#中取道部分32暴露 部分。硬遮罩薄膜25利用—個與「取道 4槽最後」過程一致的定型過程來保護電介質薄膜 L4中”電Π薄膜24進錢刻以便在中間兹刻阻止薄膜 23中疋義-取道開孔，而蝕刻阻止薄膜 中形成雙嵌入開孔的互聯部分時保護電介質】二專 在=4且V;個附著/障壁層41在雙後入開孔30中形成。 在一個具體貫施例中，与τ糾基/ jj立m g θ J T該附者/障壁層是一個氮化鈕薄膜 504753 五、發明說明（7) -個氮化2 ^膜附：:气壁層41可以是-個氮化鈦薄膜、 一個鎢鈦薄膜或固氮化矽鈕薄膜、一個氮化鈕薄膜、 傳統喷濺法逸ίΐΐ料。該附著/障壁層41典型上使用 直噴濺、離子二“該附聿壁層41可替代地使用準 一個曰 、；或化學蒸汽沉積過程加以形成。 層4 1上形志。3 ^及個傳導層43接著覆蓋在該附著/障壁 鎂。可ί代的-一個具體實施例中，肖晶種層42包括銅及 括.銦、錫、鉻、鋅、碳、錯、把、鈦、鐵、銳、 上可：Ϊ斗：在替代的具體實施例―中，$晶種層42本質 個單一物件’例如，銅、鎳、錫或類似材料。 :=晶種層4 2的方法呈多樣化。一查，個具體實施例中 士：曰:種層42使用一種物理蒸汽沉積過程加以形成，過程 中的贺濺目標包括約百分之二的原子鎂及約百分之九十八 的原子銅。該晶種層4 2可替代地使用其他的物理蒸汽沉積 ，積過程進行沉積，包括離子化物理蒸汽沉積、長擲物理 蒸汽沉積或準直物理蒸汽沉積·，或是其可使用化學蒸汽沉 積過程或塗佈過程進行沉積，例如非電解塗佈、電^塗佈 或類似的方法。該晶種層42如形同覆蓋在該附著/障壁層· 41上的連續薄膜般地進行沉積，並在該雙嵌入開孔3〇内曰形 成。在一個具體實施例中，該晶種層42以範圍·約15〇至2^ 奈米的厚度進行沉積。然而，本技藝的一般大眾體會到形 成該晶種層的厚度要夠以便適當地塗佈該傳導薄膜，而且 還要夠薄，以避免該晶種層42在該雙嵌入開孔30的角落過
第12頁 五、發明說明（8) 入互聯開孔3 〇的底部產生空 度‘生，及避免稍後在該雙嵌 隙。 、 一個傳導薄膜43覆蓋在該晶種 ㈣具有足以完全填充該雙嵌入；4孔傳導： 體實施例中，該傳導薄膜利用傳 ^ °在—個具 K的塗佈厚度糊G奈米，約為該雙沉積。 J社5、倍。可替代的是，該傳導薄膜43可用1 私加以开》成，包括非電解塗與 士二、、 、 汽沉積或化學蒸汽沉積加上物理蒸汽：=積、物理-蒸 裡層擴放至該傳導薄膜43。合金 ^刀44自该曰曰種層至該傳導薄膜43的擴 層42及該傳導薄膜43中的合金成分:44重新分配。心^ /3之：〔：配可均勻地遍布於該晶種層42及該傳導薄膜 兮德道2 :布於该晶種層42中較高或聚集在該晶種層42及 5亥傳導薄膜43的表面及分界面，端視所使用的合金材料及 退火的狀況而定。 . 退火及隨後將合金成分44併入該傳導薄膜43的結果可能 產生優點，包括該傳導薄膜電阻特性及其附著性能的改進 。該退火改變了該晶種層42及該傳導薄膜43的表面成分、 形態及内部微細結構。維持攝氏3〇〇度以上的溫度促使合 金成分44移往傳導薄膜43的表面及分界面。暴露在氧原子 =，形成了一個氧合金薄膜。該氧合金薄膜提升了該傳導 薄臈4 3與鄰近薄膜間的附著，包括稍後沉積的惰性層。依 504753 五、發明說明（9) 據具體實施 火是在火爐 該退火可 聯的電子移 是使用一個 形成，該基 該基板可替 鐘，以提升 之下實施， 施例中，一 括一個非電 化學蒸汽沉 如同使用 ，該退火步 薄膜整體電 因於退火期 該銅薄膜整 皆與高度相 電子移動的 布更均勻， 實地分布。 由於退火 積該傳導薄 20 0度至400 例，其 中以攝 替代地 動可靠 障壁層 板可在 代地以 生產量 以便將 個本質 解塗佈 積沉積 電阻及 驟結果 阻分布 間該銅 體的顆 異的顆 失效。 而有關 該晶種 膜之前 度的溫 中退火是用於擴散該合金成分44，該退 氏約30 0度至450度執行2〇至3〇分鐘。 在無合金傳導薄膜上實施，以改善該互 性。在具體實施例中，其中該傳導互聯 及本質上包含單一材料的傳導薄膜加以 約攝氏20 0度的溫度下退火約五分鐘。 攝氏250度至40 0度的溫度退火至少逼分 。該退火可用氮、減少氧成分或在真空 暴露表面的氧化降至最低。在本具體實 上包含單一材料的傳導薄膜，其範例包 銅晶種層附一個電解塗佈銅薄膜、一個 銅薄膜或類似材料。. . 電子移動數據進行測量的參數測試顯示 的改良是可達封的。薄膜電阻的降低、 的改良及有關電子移動性能的改良皆歸 薄膜顆粒的增大與綢密。在退火之前， 粒結構及顆粒方位不同。各種失效模 構及方位有關，所有皆歸因於造成 猎者退火該銅，該薄膜内的顆粒結構分 顆粒結構之電子移動的差異亦具有更緊 層及傳導薄膜所達到的優點，可經由 退^該晶種層而獲得 > 此可在約攝" 度範圍下 >儿積該晶種層。此亦可在沉積
504753 五、發明說明（ίο) 該傳導薄膜之前，首先沉積該晶種層’接著在約攝氏2〇〇 度至400度的溫度範圍下退火該晶種層達1至5分鐘。 依據本發明的具體實施例，該退火步驟可使用^個快速 熱退火器、一個熱金屬板、一個加熱器或一個火爐而進行 。一個退火狀態可整合入該處理流程，作為成群工具中的 一部分，在此狀況下，該晶種層沉積步驟、該傳導^膜沉 積步驟、一個「旋轉-清洗_瀝乾」步驟及該退火步驟或^ 些步驟的各種結合皆可在一個單一的處理平台上執行。同 樣地，這些步驟可以單一晶元或一批晶元處理作業執行。 在圖6中，以傳統的化學機械磨患處_理將該傳導薄膜43 、該晶種層42及附著/障壁層41移除，以便在該互聯開孔 30内形成一個互聯60。可替代的是，一矣聯60可使用傳統的 餘刻技術，例如離子碾磨、反作用離子蝕刻及等離子體飿 刻，或是使用鍅刻及磨光技術的I#合加以形成。 在具體實施例中，合金成分44是自該晶種層42擴散至該 傳導薄膜43，該退火可加以替代地於形成該互聯後實施。 在一個替代的具體實施例中，在移除該傳導薄膜43、該晶 種層4 2及該附著/障壁層41等部分以形成該互聯之後，該 基板便在火爐内以攝氏約300度至450度的溫度退火約2〇至 3 0分鐘。在退火期間可使用相當惰性的周遭氣體，諸如氬 、氦、氮及相似氣體，以便降低該電介質薄膜24及該傳導 互聯氡化的可能性。在退火步驟中，該合金成分自該晶種 層4 2擴散至該傳導薄膜4 3。該退火可替代地使用先前所說 明的快速熱退火器、熱金屬板或火爐等退火處理來執行。
第15頁 504753 五、發明說明（11) 本退火步驟與先前所說明的退火不同，後者是在形成該傳 導互聯的步驟之後才被實施。然而，該最後的產物是一個 傳導互聯，其提供了與先前所說明的該互聯60本質上相同 的優點。 圖7進一步說明了該半導體裝置，而目前包括一個惰性 層70、層際電介質層77及硬遮罩層76。層際電介質層77尚 包括一個較低電介質層71、一個中間蝕刻阻止薄膜72及一 個上電介質層73。該惰性層7〇、層際電介質層77及硬遮罩 層76是使用類似於用於形成惰性層2丨、層際電介質層2 〇。及 硬遮罩層25的方法加以形成。一個雙嵌入開孔74被用於形 成該硬遮罩層76、層際電介質層77.及-暴露出互聯6〇部分的 惰性層70。該雙嵌入開孔74是使用g—似於先前所說明用於 形成雙肷入開孔3 0的技術加以形成：。 依據本發明的一個具體實施例一個單一嵌入開孔75 在形成該雙嵌入開孔74期間形成。在一個具體實施例中， 該早一嵌入開孔75是用於形成一個該半導體 〇在蝕刻以定義該單一嵌入„ 3 如日日 1 J口口 £ 入開孔74的互聯槽部分的哕蝕列/二用於疋義該雙嵌 電介質層Π的移動。 ㈣阻止薄膜72亦防止該較低 圖8進一步說明了該半導體 , 附著/障壁層8 1、一個晶種声土 ，而目前包括一個 傳導合金覆蓋薄膜84，其中m固傳導薄膜83及—個 欲入結構並部分地填充該單二導f膜83完全地填充該雙 例中，該附著/障壁層81是—敗入^構在—個具體實施 個虱化鈕薄膜，而且是覆蓋
f硬遮罩層76上及先前於圖7中a 與該單一喪入開孔75内所斤义義的該雙欲入開孔74 f替代的是—個-個氮化鶴該f著/障壁糾可加 個鈕薄膜、一個鎢鈕薄膜 以-個氮化矽鈕薄膜、- 利用傳統喷濺或化學蒸汽沉積技=。附^障壁層81可 覆蓋在附著/障壁層81之上的/了加以沉積。 定的具體實施例中，該晶種層:V—個/曰種曰層8 2。在本特 使用物理篡汽沉籍_ φ— 疋個銅日日種層，並且是 夺米。了沉積，厚度範圍約為15〇至况 替代地如同-個傳導合金般地進行沉 積技術。合金材，料的範例包括麵、錫 U錯、鈀、碳、鈦、鐵、.鈮或類似材料。 -層82之上的是該傳！，.膜83。·典型上使用 種電解塗佈處理以形成該傳導薄:膜83。在本特定的 η】中’該傳導薄膜83是一個—銅薄膜，其經電解塗佈， 厚度範圍約為3 0 0至50 0奈米。該傳導薄膜83可替代地使用 物理蒸汽沉積或化學蒸汽沉積處理加以形成，並可使用其 他的傳導材料諸如鋁及金等加以形成。 ’、 依據本發明的具體實施例，該傳導薄膜具有一個足以填 滿該雙嵌入開孔74但並未完全填滿該單一嵌入開孔75的厚 度。 子 參考圖8，該傳導薄膜83的總厚度部分位於·電介質薄膜 73的最大厚度水準之下。該單一嵌入開孔的橫向尺寸並未 縮小繪製，遠大於該雙嵌入開孔。例如、，該單一嵌入開孔 的尺寸可以是25至50奈米的範圍，而該雙嵌入開孔的尺寸
第17頁 504753 五、發明說明（13) "' 則小於約0· 35奈米。該單一嵌入開孔75僅有部分被充填， 因為它太寬了。' 覆蓋在該傳導薄膜8 3之上的是一個傳導合金覆蓋薄膜84 。依據本發明的具體實施例，該傳導合金覆蓋薄膜84是一 個在該傳導薄膜83之上形成的銅糕合金。該傳導合金覆蓋 薄膜84使用一種物理蒸汽沉積過程加以沉積，過程中使用 一銅鎂噴濺目標，其中包括約百分之二的原子鎂及約百分 之九十八的原子銅。該傳導合金覆蓋薄膜^可替代地使用 其他傳統的沉積技術及其他合金材料加以形成，包括丨姐 、錫、鉻、鋅、鍅、鈀、碳、鈦、鐵二鈮、鎂或類似材料 。如同圖8中所說明的，該傳導合金覆蓋薄膜84完全地填 充該位於電介質薄膜73頂端之下的，—單一嵌入結構部分'。 該銅合金覆蓋薄膜84被沉積以便完-全地填充先前該傳導薄 膜83未填充而餘下的該單一嵌入-開孔部分。 4 該銅合金覆蓋薄膜84可替代地使用先前所說明的該物理 蒸汽沉積處理加以形成，其中該處理溫度的範圍約為攝氏 3^0 0度至450度。該提升的溫度·促使該合金成分擴散·進入該 單一饮入結構及該雙嵌入結構中的該傳導薄膜8 3，以提供 先前所說明的電子移動及附著的優點。該合成的銅合金覆 蓋薄膜84及該傳導薄膜83在稍後的處理步驟中可交替地進 行退火’以便獲得類似的整體優點。 在圖9中’使用傳統化學機械磨光處理該傳導合金覆蓋 薄膜84、該傳導薄膜83、該晶種層82及—該附著/障壁層81 等部分加以移除，以便分別在該雙嵌入開孔74中形成一個
第18頁 504753 五、發明說明（14) 互聯9 1，及在該單一嵌 互聯9 1及 磨、反作 光技術的 該傳導 導薄膜83 81、晶種 部分。 圖1 0進 覆蓋於該 之上的惰 該結合區9 2可 用離子I虫刻及 結合加以形成 互聯9 1包括傳 的剩餘部分。 層8 2、傳等薄 一步說明了該 傳導互聯9 1、 性層1 0 0 1。在 包括一個覆蓋於一個10 之上的2 5 0至3 5 0奈米氮 該惰性層1 0 0 1被餘刻以 結合區9 2的一部分。該 處理技術進行蝕刻。 圖11進一步說明了該 於該惰性層1 0 0 1之上的 施例中，該多硫亞氨薄 並沉積至約2 · 5至3 . 5微 處理在該多硫亞氨薄膜 明的具體實施例以及如 大於該較低的開孔1 0 0 2 計及封裝需求而加以規
入開孔7 5中形成一個結合區9 2。該 使用傳統的钱刻技術，例如離子碾 等離子體蝕刻，或是使用蝕刻及磨 〇 導附著/障壁層81、晶種層82及傳 該結合區92包括傳導附著/障壁層 膜83及傳導合金覆蓋薄膜84的剩餘 半導體裝置，而目前包括一個額外 该硬遮要層7_6及該結合區9 2等部分 一個具體實施例中，該惰性層丨〇 〇 J 至20奈米等子增強·型氮化物薄膜 氧化石夕薄韻。如圖1 〇中所說明的， 形成較低的開孔1 〇 〇 2，後者暴露該 惰性薄膜使用傳統等離子或濕蝕刻 半導體裝置，而目前包括一個覆蓋 多硫亞氨薄膜11 〇 2。在一個具體實 膜使用傳統的旋轉處理加以形成， 米的厚度範圍。之後，使用傳統的 中形成一個上開孔11 〇 3。依據本發 同圖11中所說明的，該上開孔1 1 〇 3 。這些尺寸是—應該半導體·裝置的設 定’而處理及裝備則用於形成該開 II 1_
第19頁 504753 五、發明說明（15) 孔。惰性層1 0 0 1的部分征袖开 — 導合金覆蓋薄膜84。之德^盖於該結合區92中的該傳 膜的部分之上，形成3導ίΐϋ!結合㈣及該惰性薄 塊11 04隨後將自該半導二Μ 1〇2。该傳導互連突 裝。 千V體裝置&供一互聯至一半導體封 該傳導合金覆蓋薄膜8 4的出現改 合區間分界面的附著。F芸 進了名h性溥膜與該結 該傳導互連突塊11 〇4部义二22性薄膜11 01部分之上的 區間分界面處分層。因刀卜，可旎在該惰性薄膜/該結合 出現，小片附著的可靠性得：：傳導合金覆蓋薄膜84的 置的整體可靠性。 …1:7 I此改進了該半導體裝 因此，依據本發明的具體實施例 ^ 的技藝提供了三個上述的彳真里 一很”、、員’、、、、·地至少較先前 電阻分布的改進、金屬互^ 。這些優點包括該傳導互聯 覆蓋和鄰近薄膜間互聯附益二子移動性能的改進以及有關 在上述說明中，已參：；？：的改r 說明。然而，本技藝的一心疋的具體貫施例對本發明加以 圍下，可如同以下申請專利2眾體會到在不偏離本發明範 及變化。因此，規袼及牲M執圍中所述，進行各式的修改 觀念，而所有的此類修改皆八1、^成明有關，而非分立的 優點、其他的長處以及問題二，涵盍在本發明的範圍内。 的具體實施例加以說明。然而解决方法已於上述中以特定 決方法及任何可產生優點、’该優點、長處、問題的解 確的物件，皆不可視其為申^ ^、解-決方法或使其更為明 利範圍中的重要、需要或 第20頁 504753 // π修正间 年月88112310 %年//月，々）日 修正 •曾式簡單說’賢
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Claims (1)

  1. 修正 88112310 % 年，/ 月 日 六、申請專利範圍 1. 一種用以形成一半導體裝置的方法，包括： 在一基板上形成一障壁層； 在該障壁層上形成一晶種層，其中該晶種層包括一 銅合金； 在該晶種層上形成一傳導薄膜；以及 退火該基板。 2. 一種用以形成一半導體裝置的方法，包括·· 在一基板上形成一障壁層，其中該基板在一電介質 薄膜中具有一個第一開孔，而該電介質薄膜具有一第一頂 面； 形成一覆蓋於該障壁層上之傳導薄膜； 形成一覆蓋薄膜覆蓋於該傳導薄膜上，其中該覆蓋 薄膜包括一銅合金；以及 移除部分該障壁層、該傳導薄膜及該覆蓋薄膜，以 便界定一個第一嵌入結構，其中該第一嵌入結構具有一第 二頂面，且其中該第二頂面係實質地平坦於該第一頂面， 並包括部分該覆蓋薄膜。 3. 如申請專利範圍第2項的方法，尚包括一個第二開 孔，其中該第二開孔較該第一開孔小，且其中形成該傳導 薄膜本質上填充該第二開孔。 4. 如申請專利範圍第1項或第2項的方法，其中該銅合 金包括自含鎖、銦*鉻、把、鈦、鐵、碳、銳、錯及錫之 群組中所選擇的物件。 5. 如申請專利範圍第1項或第2項的方法，其中該傳導
    O:\59\59369.ptc 第22頁 M 88112310 年 // 月 JO 日 修正 六、申請專利範圍 薄膜包括銅。 6. 如申請專利範圍第1項或第2項的方法，尚包括將一 合金成分擴散進入該傳導薄膜。 7. —種用以形成一半導體裝置的方法，包括： 在一基板上形成一個大部分含銅之薄膜以便實質填充 一開孔；以及 退火該基板，其中退火係在該大部分含銅之薄膜上形 成一絕緣層之前進行，該退火係均一 2 0 0至4 5 0 °C之範圍中 之溫度，及以一 1至3 0分鐘之時間週期進行。 8. 如申請專利範圍第7項的方法，其中在相同的處理步 驟中形成該大部分含銅薄膜及以一在2 0 0至4 5 0 °C範圍内之 溫度及以一在1至30分鐘範圍'内之時間週期退火該含銅薄 膜。 9. 一種用以形成一半導體裝置的方法，包括： 在一基板上形成一第一大部分含銅之薄膜，其中該 基板在一電介質薄膜中具有一個開孔； 退火該第一大部分含銅之薄膜； 在該基板上形成一第二大部分含銅之薄膜；以及 移除部份該第一及第二大部分含銅之薄膜，以界定 一嵌入結構。 10. 一種用以形成一半導體裝置的方法，包括·· 提供一具有一塗佈室及一退火室的平台； 在該塗佈室中塗佈一材料於基板上；以及 在該退火室中退火該材料。
    O:\59\59369.ptc 第23頁
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