TW501260B - Method for interlayer connection and semiconductor devices manufactured thereby - Google Patents

Method for interlayer connection and semiconductor devices manufactured thereby Download PDF

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Publication number
TW501260B
TW501260B TW090112255A TW90112255A TW501260B TW 501260 B TW501260 B TW 501260B TW 090112255 A TW090112255 A TW 090112255A TW 90112255 A TW90112255 A TW 90112255A TW 501260 B TW501260 B TW 501260B
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Taiwan
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layer
sog
hole
substrate
item
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TW090112255A
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English (en)
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Won-Jin Kim
Jin-Gi Hong
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
    • H01L21/3124—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds layers comprising hydrogen silsesquioxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3125—Layers comprising organo-silicon compounds layers comprising silazane compounds

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

501260
本唤明係關於一種層間連接之 裝置，特別是關於一種开彡杰轨μ 4 /由其製成之半導體 r 、兹_ 裡形成塾片或接觸件之士 a 成之半導體裝置，其使 觸牛之方法及由其製 層。 裝玻璃（S0G)層作為層間絕緣
Jx ^ W ψ 因為裝入半導艚奘罢 所以元件之 度整合之半 定區之接觸 更加嚴重。 在裝置之某 連某層。此 利用光刻法 減少此等問 間絕緣層填 成接觸孔及 並使用。 一種形成硼 溫下進行熱 ’以高度整 以下，所以 一損害元件 〇 出另一種使 大小逐漸減少而货：作之元件被高度整合， 八』k /哥執夕而裝置變得更。 導體裝置内，諸門日§ 49 口此 在兩 杜ϋ 3i ^如滲透線路或元件間之指 件或通孔之長寬比的增 即，由於接觸孔之手；2驟涵盍之擴大會 几4長見比會增加，1眷彳旱 層内形成深與窄孔；5田俏道u ，、支仔更難 .$乍孔及用傳導材料填充窄孔以互 :卜安：裝置下部之壞步驟涵蓋，當裝置之上部 圖乂匕以形成線路或元件時，造成問題。為了 通’使用層間絕緣層之技術，侈tj如，一種用層 充元件如閘極線間之間隙，於層間絕緣層内ς 墊片及平面化層間絕緣層之上部之方法已發展 關於使用層間絕緣層之技術之實例，曾提供 -鱗石夕酸鹽玻璃（BPSG)層，然後在約83(rc之高 處理過程之方法。然而’因為閘極線間之寬度 合=半導體裝置被設計成臨界尺寸（CD)〇2 在南溫下形成層間絕緣層之熱處理過程會歸咎 之問題’例如，半導體裝置内之減少的電晶體 為了解決由於南溫下熱處理過程之問題，提
501260 五、發明說明（2) 用〇3四乙基原矽酸鹽未摻雜矽酸鹽玻璃（03-TE0S USG)或高 密度電漿（HDP)氧化物層之方法。然而，當閘極線間之寬 度設計成C D為〇 · 2 μ m，例如約0 · 1 8 /z m以下時，此等層亦 歸咎一產生空隙或狹縫之問題。 為了解決上述問題’提出為一種使用S〇G層作為層間絕 緣層之方法。S0G材料有利於填充閘極線間之間隙並減少 步驟涵蓋’因為首先呈夜體或氣溶膠狀態。在s〇G材料施 加至基板後，在75 °C-3 0 0 °C之低溫下實施軟烘焙法以除去 溶劑成份如二烷醚，然後在約4〇〇它下實施硬烘焙法以得 最終S0G層間絕緣層。根據需要，在超過70 0 °C藉退火附加 實施致密及固化法以除去s〇G層内之不穩成份並穩定化其 内之晶化結構。 然而’因為在致密及固化法後，雜質成份如有機元素、 氫及氮、無機元素等尚未完全除去而仍留於S〇G層内以劣 化層特性’所以在後續過程中會發生諸問題如於層内形成 污物及多孔晶化結構。特別是.，在具有大長寬比之閘極線 間之間隙的下部或角落，殘留更多雜質成份，因為固化從 SOG層之表面開始，因而減少逸出雜質成份之途徑。 又’在圖案化之蝕刻法及清潔法在s〇G層内者之條件下 =施之情況，有不完全固化部分，其具有雜質成份及多孔 晶化結構，在S0G層之不完全固化部份之蝕刻速率高於其 内無雜質成份及多孔晶化結構之其他完全固化部份之蝕刻 速率。通常，SOG層内之晶化結構利用氧及矽以外之雜質 成份轉換成多孔晶化結構，而具有多孔晶化結構之s〇G層
第6頁 观260
具有極 内，根 藉以增 例如 層間絕 聚石夕氮 閘極線 件或儲 多孔晶 易被含 去離子 刻。結 鄰墊片 無法正 高濕I虫刻速率。此外，A c Λ ^ ^ r ^ .. 在训〇層之不完全固化部分 據…、y脹4產生應力之差異以劣化元素之可靠度， 加較差品質之裝置，比較於完全固化部分。 ’在基板上形成金屬氣# 从成心丄P , 高乳化石夕（M0S)電晶體結構後， 緣層係由無機S 0 G材料士 σ气2^乂立* ρ 可料如氧石夕倍+四氫吡喃（HSQ)或 烷所形成之情況下，多$ θ 紝 孔日日化結構部分適於形成於 ^之S0G層間絕緣層之下部。因此，當位 存節點接觸件之塾片係' 由自行對準法形成時’具有 化結構之S0G層之了部被暴露。s〇G層之暴露不部容 於清潔劑内之極小量蝕刻劑，例如，NH4〇H及 水之混合物稱為sci，或緩衝氧化物蝕刻器（B〇E)蝕 果，管線狀橋件可透過S0G層之暴露下部形成於毗 之間。此等橋件造成線路間之短路，使半導體裝置 常操作。 " 圖1及圖2為其上之墊·片孔未形成於s〇G層間絕緣層内之 垂直及平行於閘極線之縱間所取之傳統半導體裝置之一部 份基板的截面，圖3為其上之墊片孔形成於s〇G層間絕緣層 且填充多晶矽材料之圖2基板之截面。 參照圖1 ’閘極線形成於其上形成有隔離層丨丨之基板i 〇 上。閘極線係藉按序沈積及圖案化閘極絕緣層丨3、傳導層 1 5及氮化矽加蓋層丨7所形成。在閘極線之側壁上，隔片工9 係由氮化矽層形成。然後，必要時，襯墊層（圖未示）被沈 積 而t石夕氮烧S 0 G層21係由旋塗法形成。之後，實施烘 培與退火法。圖2為沿圖1所示之線A-A，平行於閘極線之縱 501260 五、發明說明（4) 間所：之基板，部分之閘極線間之戴面。 之一部分S〇G屛—产$ + $ 4口 #口日日 、、果下方 ㈢顯不在退火過表期間不完全固化之〜卸 分0 外 準m在返火過程後，形成墊片孔23以利用自行對 23後，實施清潔過程，，孔23::“ΐ=ΐ片孔 (CVP)法壌、黑夕 Τ不J用化予相沈積 回蝕法以分’二晶矽層。之後’實施化學機械磨光(CMP)或 中，可局；：每片。因此，可得塾片，然❼，在清潔過程 在最壞情^刻塾片孔間之層以形成不規則側表面。 多晶石夕層沈積於一部分S0G：!21會穿孔。在此情況下，若 與础鄰儲存r /的層21之穿孔部份時，在位元線接觸墊 密；^ 2 ^二要一種當使用S0G層間絕緣層形成於高度整合 在度+導體内時防止墊片間發生短路之方法。 , 發明之概沭 本發明$ "一 法及由复制:目的為提供一種形成塾片或接觸件之改良方 層。”衣成之半導體裝置，其使用S0G層作為層間絕緣 本發明之Η 方法及由甘 目的為提供一種形成墊片或接觸件之改良 孔晶化姓構Ϊ:成之半導體裝置’當墊片形成於適於具有多 發生短: 之训^層間絕緣層内時，其可防止墊片間 此等及J： ^ ^ 供，誃方Γ目的後根據本發明藉一種層間連接之方法提 去包括在具有複數傳導區之基板上形成s〇G層間
第8頁 501260 五、發明說明（5) ' 一~ - 絕緣層，形成孔以藉圖案化S〇G層間絕緣層暴露至少一部 二在形成孔之S0G層間絕緣層上形成襯墊層。， 糟貝口蝕在孔之側壁上形成隔丨，清潔其上形成p片之 J板：整個表面及用傳導層填充孔之步驟。本發明：方法 I於衣造使用無機S0G材料層之半導體裝置，如，/ 層填充窄間隙及在窄間隙内形成孔 可用於ft大u A 7丨 _ +發明之方法 層之sor展南密度形成於欲填滿傳導材料如多晶矽 層内日守，於填孔 < 墊片或栓塞間發生严件。 形i Ξ ΐ ί:之ς半導體裝置包含具有複數傳導區之基板、 一部Ϊ 層間絕緣層，孔連接各傳導區之至少 :填充忒孔之複數導體及插在導體與形成孔之S0G ㈢间之複數隔片。 成孔★月之半導體裝置適於在元件如閘極線間之間隙内形 外，ςπ在閘極線下方之傳導區以高密度形成於基板上。此 成。G層間絕緣層較佳由無機材料如HSQ或聚矽氮烷所形 圖 之簡單說明 間浐1及圖2為垂直並平行於其上之墊片孔未形成於S0G層 =緣層之間極線之縱向所取之傳統半導體裝置之一部分 暴板之截面圖。 圖3氧i μ + # ， 鉍仏两，、之塾片孔形成於S0G層間絕緣層且填滿多晶矽 材料之圖2基板之一部分的戴面圖。 程^ 4A至圖8A為垂直於閘極線縱向所取之一部分基板之流 ^ ’顯不根據本發明之一具體例之層間連接方法之加工
501260 五、發明說明（6) 步驟。 圖4 B至圖8 B為·顯示一部八| 甘η朽令 。卜刀基板之某閘極線間之截而之洎
^流程；別對應於平行於閘極線之縱向所取之圖4Α至圖8A 例之詳細說 以下參照顯示本發明較佳具體例之附圖詳述本發明。然 ^ 日以纤夕不同形式具體化，不應限於本文所示 _彳丨，反而 &供此具體例，使比揭示會徹底並完 全’且完全傳達本發明之範圍至熟悉此技藝者。相同號數 意指整個相同元件。 圖4 A至圖8 A為垂直於閘極線縱向所取之一部分基板之流 程圖，顯示根據本發明之一具體例之層間連接方法之加 工步驟及圖4B至圖8B為顯示一部份基板之某閘極線間之截 面之机私圖，为別對應於平行於閘極線之縱向所取之圖4 a 至圖8A之流程圖。 現參照圖4A及圖4B，隔離層形成於半導體基板上以界定 有源區。然後’閘極絕緣層丨丨〇形成於基板上。此後，多 晶矽層130、金屬矽化物層15〇、氮化矽加蓋層17〇連續形 成分別至厚度為800A，1〇〇〇Α，2000A。將此等層圖案 化以形成閘極線。在閘極線形成後，相配氮化矽層沈積至 厚度為1 0 0 0 A。為了在閘極線之側壁上形成隔片丨9 〇，實 施各向異性姓刻法至基板之整個表面。在形成隔片1 g 〇以 前’進行離子植入法以形成源極/汲極區。或者，在形成 閘極圖案後，可對閘極圖案之側壁實施蝕刻固化之氧化
第10頁 501260 五、發明說明（7) 法’又在形成隔片後’薄氮化矽襯墊層可形成於基板之整 個表面上。 參照圖5A及圖5B，為了形成s〇G層210，利用旋塗法將聚 石夕氮烧塗敷至基板之整個表面，基板上之隔片形成於閘極 線之側壁上。此時，可使用無機s〇G材料如氫矽倍半四氫 口比喃（HSQ)取代聚矽氮烷。為了自聚矽氮烷基獲得最終s〇G 層間絕緣層’在約4〇〇 t下實施除去溶劑成份之硬烘焙法 若干分知’然後實施固化法以在3 5 〇它至8 5 t，較佳為 700 °C至80G°c下藉退火自聚矽氮烷層除去氫及氮成份。進 行固化法1 〇分鐘至2小時，以使聚矽氮烷層具有由氧之飽 和結晶之石夕_氧結構。因此，可得不具空隙或狹缝之平面 SOG層間絕緣層。或者，在塗敷聚矽氮烷後，亦可附加實 施平面化法如CMP法。 然而’因為在高度整合半導體如動態隨機存取記憶體 内，閘極線間之空隙極窄，所以於間隙下部或角落内之欲 除去之雜質成份如氫及氮，在用s〇G層21〇填充間隙後，在 固化過程期間未除去良好。即，因為固化從S〇G層以^之表 面開始，具有硬晶化結構之上固化層212形成於3〇(?層210 之上部。因此，對於固化層2 1 2下方之雜質成份很難徹底 除去。特別是，雜質成份仍留於s〇G層21〇之下部或角落。 因此，在SOG層21 0之下部，例如圖5虛線下方之部分，其 中留有雜質成份，於二氧化矽晶化結構内具有小間隙之多 孔層211會形成。S0G層210之下多孔層211具有極高濕蝕刻 速率使其谷易於清潔過程中利用極小量飿刻劑餘刻。
第11頁 五、發明說明（8) 參照圖6A及圖6B，形成墊片孔23〇以形成自行對準之接 r(SAC)。塾片孔2 3 0係利用-種在基板上形成光阻圖 I ，然後利用光阻圖案作為光罩乾飯刻3〇(；層21()之方法形 f。此時’ t片孔230之上部被形成具有寬大寬度，但塾 片孔23 0之下部被形成僅暴露閘極線間之窄間隙，因為氮 =石夕加蓋層170及覆蓋閘極線之隔片19〇作為姓刻光罩。各 =孔2 3 0之#刀側壁係由形成閘極線之毗鄰隔片】9 〇所 ::各墊片孔2 3 0之另一部分側壁則由s〇G層21〇所組 成。因此，形成各墊j：{子丨 ^ ^ . , ao1 乃孔之另—部分側壁之SOG層210 =夕未m if露。然而，此時，s〇g層210之下多孔 = 211未破㈣而仍如其開始般留下 法以形成墊片孔23 0。 π 1罜退灯祀鄉幻 芙二氮…墊層在其上形成有墊片孔之 ί〇η::厚度為5〇α，〇α，較佳為ι〇“ 辟上步成孔f μ ^ ίΓ各向異性蝕刻法以在墊片孔2 3 〇之側 土上：¾/成孔片250。孔陪吳丄7 物（HTO)、中溫氧化物（MT 由材料層如高溫氧化 示良好步驟涵蓋及小濕蝕刻速二。矽(SlA)所形成，其顯 之後’對其上之孔隔片25〇形成於 面實施濕蝕刻或清潔法墊片孔23〇内之整個表 離子水稱為SU之混合物作，.'/./^係使用關4〇H，HA及去 之目的主要為除去形;/行1 〇分鐘。清潔法 及除去污物如殘留於墊片土1夕表面上之天然氧化物以 必須進行足以完ϋ π 粒子。因此，清潔法 暴路石夕基板100之傳導區。在蚀刻法
第12頁 501260 五、發明說明（9) 中，形成墊片孔2 30之一部分側壁之s〇G層21〇的下多孔層 2 11係由孔隔片2 5 0保護，因此可防止墊片孔2 3 〇因蝕刻形 成不平表面或裂痕等間題。 參照圖8A及圖8B，形成孔隔片25〇之墊片孔23()填滿多晶 矽傳導層。多晶矽傳導層係在植入雜質以增加導電性之條 件下利用CVD法形成。然後，實施CMP法以暴露s〇G層21 〇之 上表面，因而互相分離墊片270。因此，可得墊片270。因 此’因為無多晶石夕傳導層之部分留在墊片2 7 〇間之g 〇 〇層 210之上表面上，所在未發生墊片27〇間之橋件。 由剷述可知，本發明提供一種形成墊片或接觸件之方法 及由其製成之半導體裝置’其使用S〇G層作為層間絕緣 層，且當墊片形成於SOG層間絕緣層俾可具有多孔晶化結 構部分時，可防止墊片間發生短路，因而增加裝置之可靠 度並減少較劣品質之裝置。 在附圖及說明書中，揭示有本發明之典型較佳具體例， 雖使用特定術語’但其僅以一般及說明性意義使用而非限 制之目的，本發明之範圍述於下列申請專利範圍内。
第13頁 501260 圖式簡單說明 第14頁

Claims (1)

  1. 501260
    申5青專利範圍 1·—種層間連接之方法，包括下列步驟： 开3複ί傳導區之基板上形成S0G層間絕緣層； 各該傳i區"^藉圖案化該s〇g層間絕緣層暴露至少一部分 二：：該孔之S0G層間絕緣層上形成襯墊層； =鉍回蝕在該孔之側壁上形成隔片； 成有該隔片之該基板之整個表面;及 用傳導層填充該孔。 2·如申請專利範圍第1項之方法，直中兮ςηΓ厣脊Λ > 機S0G材料形成。 /、中该S0G層仏由然 数取\申明專利乾圍第2項之方法，其中該S0G層係由塗 用350 t至8 5 0 下f二下洪培以除去溶劑成份及利 芏8 bU C下退火之固化所形成。 用門梅安％ 11第1項之方法’其中該傳導區為藉使 談:糸Γ木作為離子植入光罩形成之源極/汲極傳導區， ^ ’、、、觸件用之墊片孔，其係利用自行對準法形成於兮 源極/汲極傳導區内。 取扪’人 積5奇化如々申7專利範圍第1項之方法，其中該襯墊層俜藉沈 清㈣石。日^ ’該清潔步㈣使用包減切银刻^ 6· —種半導體裝置，包含·· 具有複數傳導區之基板； 形成複數孔之S0G層間絕緣層，該孔連接至 各該傳導區； ^ 4分
    第15頁 501260 六、申請專利範圍 複數填充該孔之導體；及 複數插置在該導體與形成該孔之S0G層間之隔片。 7 ·如申請專利範圍第6項之裝置，其中該基板具有複數 閘極線及形成該傳導區之源極/汲極傳導區，該導體為由 自行對準法形成之接觸墊。 8 ·如申請專利範圍第7項之裝置，其中該閘極線間之距 離為0.18 //m以下。 9. 如申請專利範圍第6項之裝置，其中該S0G層間絕緣 層係由選自HSQ與聚矽氮烷之一所形成。 10. 如申請專利範圍第6項之裝置，其中該隔片係由選 自具有厚度為50A—400A之氮化矽層、ΗΤ0層及ΜΤ0層之 一所形成。
    第16頁
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