TW488033B - Method of fabricating a semiconductor device comprising a stack of silicon layers alternating with dielectric material layers - Google Patents
Method of fabricating a semiconductor device comprising a stack of silicon layers alternating with dielectric material layers Download PDFInfo
- Publication number
- TW488033B TW488033B TW089118601A TW89118601A TW488033B TW 488033 B TW488033 B TW 488033B TW 089118601 A TW089118601 A TW 089118601A TW 89118601 A TW89118601 A TW 89118601A TW 488033 B TW488033 B TW 488033B
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- Prior art keywords
- silicon
- germanium
- layer
- combination
- stack
- Prior art date
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 61
- 239000010703 silicon Substances 0.000 title claims abstract description 60
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000003989 dielectric material Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 25
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 24
- 229910052732 germanium Inorganic materials 0.000 claims description 23
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 239000004576 sand Substances 0.000 claims description 14
- 229910000676 Si alloy Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 6
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 241000587008 Pachyphytum oviferum Species 0.000 claims 1
- OPTOQCQBJWTWPN-UHFFFAOYSA-N [Si].[Ge].[Si] Chemical compound [Si].[Ge].[Si] OPTOQCQBJWTWPN-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 239000011014 moonstone Substances 0.000 claims 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 claims 1
- 239000013589 supplement Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002079 cooperative effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
488033 A7 B7 五、發明説明（丨） (請先閱讀背面之注意事項再填寫本頁) 本發明係有關於一種包含由砂層與介電材料層交替形 成之堆疊物的半導體裝置的製造方法。其特別有益於一些 應用例如將邏輯功能整合於一單獨結構、記憶體、閘極環 繞(GAA)電晶體、感測器等之最終互補式金屬氧化半導體 (CMOS)。 標準塊狀結構金屬氧化半導體場效應電晶體（ MOSFET)的一個限制因子在於基板效應（降低電晶體的 工作特性）。在一絕緣層上有砍（SOI)結構的M0SFET 中，該缺點藉由鑲埋一層氧化矽層的方式，將矽薄膜與基 板隔離而被避免。 在完全空乏的薄膜SOI結構MOSFET中消除基板效應 將增加汲極電流。 然而，超薄SOI結構的MOSFET具有高的源極/汲極 (S/D)電阻，因爲淺接面爲矽層厚度與不良的熱導率所限 。製造SOI結構基板的成本亦相當高，其已限制製品進入 市場。 經濟部智慧財產局員工消費合作社印製 結合塊狀與絕緣層上有矽（SOI)結構優點之矽在無 物上（silicon on nothing，SON)結構的電晶體可消除上述 的缺點。第1圖表示一個SON結構電晶體，其包含有以一 薄的閘極介電層4塗佈之頂端表面的矽基板1，以及源極 與汲極區域5，6 (定義位於兩者之間的通道區域la)，與 位在通道區域la上之基材頂端表面上方的聞極7被形成。 在該源極與汲極區域5, 6之間之電晶體的通道區域la更包 含有一個連續的絕緣孔洞2，該孔洞2藉由連接源極與汲 __3___ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公蔆） 488033 A7 B7 五、發明説明（> ) 極區域5, 6，以及位在絕緣孔洞2頂端之薄矽層3而被定 界。閘極7具有間隙壁8, 9於其兩側。接觸1〇，11被設置 於源極與汲極區域5, 6中。 本發明之目的在於提供一種製作基本半導體裝置的方 法，藉此可製作上述的電晶體。 本發明的另一個目的在於提供一種製造最終CMOS的 方法，將邏輯功能整合於一單獨結構、記憶體、閘極環繞 (GAA)電晶體、感測器等，其中在未增加源極與汲極區域 之串連電阻的情況下，消除或至少降低基板效應；該方法 提供高於SOI結構裝置的改良熱逸散，並具有低於SOI結 構的製造成本。 因此，本發明提出一種製造半導體裝置的方法，其包 含有下列步驟： a) 形成包含有連續地至少一個第一組合與一個第二組 合之堆疊物於一個矽基板的主表面上，以基板作參考，各 組合包含一個鍺或鍺與矽的合金鍺化矽（SiGe)之薄底層以 及一個薄的矽頂層； b) 形成一個薄的二氧化矽層於該第二組合的薄矽頂層 .上方，其將在該堆疊物的至少二個相對側邊上支撐該堆疊 物的諸層； c) 形成一個硬式遮罩於該薄的二氧化砂層上，以便形 成二個隔離之相對區域於該硬式遮罩的二相對側邊的各相 對邊上； d) 將二個隔離之相對區域中的該薄二氧化矽層，以及 --- -- 4_ 本紙張尺度適用中國國家標準（CNS ) Μ規格（21〇X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、1Τ MW. 經濟部智慧財產局員工消費合作社印製 488033 A7 _ B7 五、發明説明（）） k % 一組合之砂頂層與至少P卩分的鍺或鍺化砂底層進行触 刻； (請先閲讀背面之注意事項再填寫本頁) 〇將該苐一組合之鍺或鍺化砂底層進行選擇性地橫向 蝕刻，而形成隧道； ^ f) 將該桌一組合的險道以一^固態介電材料塡充； g) 將二個隔離之相對區域中的該第〜組合之砍頂層與 至少部分的鍺或鍺化矽底層進行蝕刻； h) 將該第一組合之鍺或鍺化砂底層進行選擇性地橫向 蝕刻，而形成隧道；以及 ^ i) 依所需而將該第一組合的隧道以〜固態介電材料塡 充。 ^ 適用於本發明的鍺與矽的合金鍺化矽（^(^)包含具有 Sii_xGex (0<χ$1)以及 Sii.x-yGex Cy (〇<χ$〇·95，〇<yg〇.〇5) 化學式的合金。 該硬式遮罩可由對於政、鍺和/或鍺化砂有鈾刻選擇性 的任何傳統材料製作。 經濟部智慧財產局員工消費合作社印製 步驟d)與g)之隔離相對區域的蝕刻偏好電漿蝕刻，其 係爲本技藝所熟知。 步驟e)與h)之鍺或鍺化矽層的蝕刻爲對於矽與介電材 料有選擇性的非等向性電漿蝕刻，或爲使用氧化性溶液的 選擇性化學蝕刻，其係爲本技藝所熟知。以此方式形成於 胃或鍺化矽層中的隧道在步驟f)與i)期間，以一固態的介 «材*料塡充，諸如以二氧化矽（Si〇2)或氧化鉅(Ta2〇5)。特 別地是’其可以熱氧化所形成的二氧化矽塡充。然而，在 度適用石) A4規格（210X297公釐） '~ 488033 A7
發明說明（/ 未損及所獲得之半導體裝置的物理完整性下，第一個組合 的隧道無需以一固態介電材料塡充，在該情況下 ，空氣被 使用爲隧道的介電材料。 本發明亦提供一種半導體裝置，其所包含的矽基材部 分被形成一個介電材料與矽之連續層的堆疊物於其上。 在本發明的一良好實施例中，與矽基材直接相鄰之該 堆疊物的介電材料層爲一個空氣層。較上層則爲延伸超出 堆疊物之位於二個相對側邊上的最終二氧化矽層所良好地 支撐。 圖式簡單說明： 本發明的其他優點及特徵將在硏讀下列對於本發明之 一非限制性的具體實施例之詳細描述並參閱附圖後而變得 淸楚，其中： 第1圖表示一個SON結構電晶體，其包含有以一薄的 閘極介電層4塗佈之頂端表面的矽基板1，以及源極與汲 極區域5, 6，與位在通道區域la上之基材頂端表面上方的 閘極7被形成。 第2a至第2h圖爲表示本發明之各製程步驟的橫剖面 圖，以及 第3圖爲根據本發明之半導體裝置的一實施例的圖式 ，其係爲垂直於第2a至2h圖之剖面的剖面圖式。 一種製造雙層半導體裝置的方法現在將被說明，雖然 本發明並不僅限於雙層裝置。根據本發明之方法可容易地 被應用於具有多於雙層的半導體裝置。 (請先閱讀背面之注意事項再填寫本頁) 裝 訂： 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 488033 A7 '_______Β7______ 五、發明說明（（） -1111------ 11 (請先閱讀背面之注意事項再填寫本頁) 第2a圖表示一個矽基板12，其上半部爲直角剖面圓 柱狀絕緣區塊13所圍繞。在爲絕緣區塊13所定界之矽基 板12的上表面上方，包含一個矽與鍺合金鍺化矽底層Η 以及一個矽頂層15的一第一個組合被形成。接著形成於該 第一個組合頂端的爲也由一個鍺化矽底層16以及一個矽頂 層17所形成的一第二個組合。 這二個組合的該矽層15, 17以及鍺化矽層14, 16係藉 由選擇性地磊晶成長而被形成，以確保由矽基板12至連續 的矽層15, 17以及鍺化矽層14, 16之基板的晶格連續性。 以此方式所形成的堆疊物將覆蓋所有的矽基板12頂端表面 〇 如第2a圖所示，其次的步驟包含首先成長一個薄的二 氧化矽層18於該第二個組合的頂端矽層17上。該薄的二 氧化矽層18並不覆蓋位於堆疊物（由諸層14, 15, 16及17 所組成）之二個主側邊A，A，上的絕緣區塊13。另一方面 ’該薄的二氧化矽層18則延伸超出沿著該堆疊物之二個副 側邊的絕緣區塊13。在第2a至2h圖中，該二個副側邊係 垂直於二個主側邊A，A，，亦即垂直於該剖面。 其K ’如弟2b圖所币，一個硬式遮罩19被形成於該 薄的二氧化砂層18的中心部位上。其亦延伸超出該堆疊物 的二個副側邊。該硬式遮罩19可由對於矽與鍺化矽合金有 選擇性蝕刻的任何材料所製作。例如，在製造M0S電晶體 的情況中’該硬式遮罩19可爲被覆薄硬式遮罩層的複晶矽 柵網所取代。該材料可爲諸如一個氮氧化矽層，其爲本技 本紙張尺度_中0目家標準χ 29f_@ ) """" 488033 A7 _B7_______ 五、發明說明（6 ) 藝所熟知。 該二氧化矽層18、該第二個組合的頂端矽層17以及 該第二個組合的底部鍺化矽層16的上半部接著藉由諸如電 漿方法在二個主側邊A，A’上被蝕刻，如第2c圖所示。該 二氧化矽層18以及該第二個組合的頂端矽層17被蝕刻。 僅該硬式遮罩19底下的部分未被蝕刻。 其次的步驟爲藉由非等向性電漿蝕刻而將底部鍺化砂 層16移除，其將產生頂端以第二個組合的頂層矽層17且 底部爲第一個組合的頂層矽層15所定界的隧道。其亦得以 使用該鍺化矽層的選擇性化學蝕刻，諸如使用標準氧化性 溶液。該第二個組合的頂層矽層17並不會崩落於第一個組 合的頂層政層15上，因爲其係爲二氧化砂層18及硬式遮 罩19 (延伸超過位於二個副側邊上的絕緣區塊13部分） 所支撐。第2d圖表示形成於矽層15與17之間的隧道。 該第一隧道接著以介電質塡充例如熱氧化所形成的二 氧化矽20。 進一步的蝕刻工作接著在該硬式遮罩的二個相對側邊 上進行，以移除用於塡充第一隧道的該二氧化砂20、該第 一個組合的頂層矽層15以及該第一個組合的底層鍺化矽層 14上半部（見第2f圖）。 更進一步的非等向性電漿蝕刻移除該第一個組合的底 層鍺化矽層14。此舉將形成一個第二隧道，如第2g圖所 示。在隧道上的諸層接著爲位在二個副側邊上的二氧化矽 層18與硬式遮罩19 (支撐於該絕緣區塊13的二個側邊部 __ 8___ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 · 488033 A7 _- —_ B7 五、發明說明（；？） 分）所支撐。 第2h圖表示一個可依所需而選擇的最終步驟，其係藉 由以熱氧化所形成的二氧化矽21塡充該第二隧道。因此， 第2h圖表示已完成的半導體裝置。 明顯地得以省略以一介電材料（二氧化砂21)塡充該 隧道的最終步驟。具有一空氣層22位於該第一個組合的頂 層矽層15與矽基板12之間的裝置因而被獲得。第3圖表 示垂直前示圖式剖面之該裝置的剖面。沿著二個副側邊（ B以及B’，第3圖）支撐矽層17、鍺化矽層16及矽層15 的該二氧化矽層18與硬式遮罩層19 (支撐於該絕緣區塊 13的二個側邊部分）可被看見。 所述的半導體裝置包含多層堆疊於一個矽基板頂端表 面上的諸層，並可被良好地使用爲用於製造新穎半導體組 件的基本裝置。 元件對照表 矽基板1 ;絕緣孔洞2 ;薄矽層3 ;薄的閘極介電層4 ;源 極5 ;汲極6 ;通道區域la ;閘極7 ;間隙壁8 ;間隙壁9 :接觸10 ;接觸11 ;矽基板12 ;直角剖面圓柱狀絕緣區 塊13 ;矽與鍺合金鍺化矽底層14 ;矽頂層15 ;鍺化矽底 層16 ;矽頂層17 ;薄的二氧化矽層18 ;主側邊A ;主側 邊A’ ；硬式遮罩19 ;二氧化矽20 ;二氧化矽21 ;空氣層 22 ;副側邊B ;副側邊B’ ---------2_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝
Claims (1)
- 488033 B8 年）月石日修正/更正/補充 D8 六、申請專利範圍 1.一種製造半導體裝置的方法，該方法的特徵在於其 包含有： a) 形成包含有連續地至少一個第一組合（14, 15)與一個 第二組合（16, 17)之堆疊物（14, 15, 16, 17)於一個矽基板（12) 的主表面上，以基板作參考，各組合包含一鍺或鍺與矽的 合金鍺化矽（SiGe)之薄底層（14，16)以及一個薄的矽頂層 (15, 17); b) 形成一個薄的二氧化矽層（18)於該第二組合的薄矽 頂層（17)上方，其將在該堆疊物的至少二個相對側邊（A， A’)上支撐該堆疊物的諸層； 0形成一個硬式遮罩（19)於該薄的二氧化矽層（18)上， 以便形成二個隔離之相對區域於該硬式遮罩的二相對側邊 (A，A’)的各相對邊上； d) 將二個隔離之相對區域中的該薄二氧化矽層（18)， 以及該第二組合之矽頂層（17)與至少部分的鍺或鍺化矽底 層（16)進行蝕刻； e) 將該第二組合之鍺或鍺化矽底層（16)進行選擇性地橫 向蝕刻，而形成隧道； f) 將該第二組合的隧道以一固態介電材料(20)塡充； g) 將二個隔離之相對區域中的該第一組合之矽頂層 (15)與至少部分的鍺或鍺化矽底層（14)進行蝕刻； h) 將該第一組合之鍺或鍺化矽底層（14)進行選擇性地 橫向蝕刻，而形成隧道；以及 1)依所需而將該第一組合的隧道以一固態介電材料(21) 1 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐） f ! (請先閱讀背面之注意事項再填寫本頁) 、一 488033 A8 B8 C8 D8 申請專利範圍 塡充。 ............... ^請先閱讀背面之注意事項再塡寫本頁) 2. 如申請專利範圍第1項之方法，其特徵在於鍺與矽 的鍺化矽合金（14，16)爲鍺與矽所形成的合金，其化學式爲 SikGex (0<x€ 1)或 Si^Gex Cy (0<x€ 0.95，0<yS 0.05)。 3. 如申請專利範圍第1或2項之方法，其特徵在於該 硬式遮罩（19)爲對於矽、鍺和/或鍺化矽可以選擇性地蝕刻 的材料。 4·如申請專利範圍第1或2項之方法，其特徵在於步 驟d)與g)之隔離相對區域的蝕刻爲電漿蝕刻。 5·如申請專利範圍第1或2項之方法，其特徵在於步 驟e)與h)之鍺或鍺化矽層（14，16)的蝕刻爲對於砂（12，15, Π，I8)與介電材料有選擇性的非等向性電漿蝕刻，.或爲使 用氧化性溶液的選擇性化學蝕刻。 6. 如申請專利範圍第1或2項之方法，其特徵在於形 成於鍺或鍺化矽層（14，16)中的隧道在步驟f)與〇期間，以 一固態的介電材料(2〇, 21)塡充。 ’ 7. —種半導體裝置，其特徵在於包含了一矽基材〇2)， 且在該縣材部分上g 了-财電材料卿$連續層的 堆疊物(21，15,20，17)#^ 8. 如申請專__ 7項之半導體類，其特徵在於 與砂基材__之iri#_介電_顚〜個空氣層
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| JPS63278375A (ja) * | 1987-05-11 | 1988-11-16 | Nec Corp | 半導体集積回路装置 |
| US5155657A (en) * | 1991-10-31 | 1992-10-13 | International Business Machines Corporation | High area capacitor formation using material dependent etching |
| EP0799495A4 (en) * | 1994-11-10 | 1999-11-03 | Lawrence Semiconductor Researc | SILICON-GERMANIUM-CARBON COMPOSITIONS AND RELATED PROCESSES |
| DE69609313T2 (de) * | 1995-12-15 | 2001-02-01 | Koninkl Philips Electronics Nv | Halbleiterfeldeffektanordnung mit einer sige schicht |
| FR2799305B1 (fr) * | 1999-10-05 | 2004-06-18 | St Microelectronics Sa | Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu |
| FR2806833B1 (fr) * | 2000-03-27 | 2002-06-14 | St Microelectronics Sa | Procede de fabrication d'un transistor mos a deux grilles, dont l'une est enterree, et transistor correspondant |
| FR2812764B1 (fr) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
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1999
- 1999-06-28 FR FR9908249A patent/FR2795555B1/fr not_active Expired - Fee Related
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2000
- 2000-06-28 EP EP00946029A patent/EP1190454A1/fr not_active Withdrawn
- 2000-06-28 WO PCT/FR2000/001798 patent/WO2001001496A1/fr not_active Application Discontinuation
- 2000-06-28 US US10/019,169 patent/US6713356B1/en not_active Expired - Fee Related
- 2000-09-11 TW TW089118601A patent/TW488033B/zh not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI732256B (zh) * | 2019-05-22 | 2021-07-01 | 南亞科技股份有限公司 | 半導體結構及其製造方法 |
| US11094578B2 (en) | 2019-05-22 | 2021-08-17 | Nanya Technology Corporation | Semiconductor structure and method for manufacturing the same |
| US11482445B2 (en) | 2019-05-22 | 2022-10-25 | Nanya Technology Corporation | Method for manufacturing semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2795555B1 (fr) | 2002-12-13 |
| WO2001001496A1 (fr) | 2001-01-04 |
| US6713356B1 (en) | 2004-03-30 |
| EP1190454A1 (fr) | 2002-03-27 |
| FR2795555A1 (fr) | 2000-12-29 |
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