TW472327B - Dual-die integrated circuit package - Google Patents
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- TW472327B TW472327B TW089124874A TW89124874A TW472327B TW 472327 B TW472327 B TW 472327B TW 089124874 A TW089124874 A TW 089124874A TW 89124874 A TW89124874 A TW 89124874A TW 472327 B TW472327 B TW 472327B
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/0001—Technical content checked by a classifier
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
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Description
五、發明說明α) 細說明 【技術領域】 本發明係關於積體電路封 ^ (晶粒)之積體電路封裝。 ’尤指具有多重半導體晶片 【背景技術】 晶片封裝係用來保護積體 並可用來提供一耐久及實質雷a B曰片免於文污染及誤用, 片連接至外部印刷電路板或=接系統,將積體電路晶 戟/、上提t、一夕日曰片積體 早—日曰 將多晶片直接裳置於—基封f ’具有許多優點。 線之間的連接,低電感與低電容:u二=號/電力 内接網路,封裝密度及改善系 七、應非常密集的 ㈣顧最二及覆晶 ^ :SP- ί : i - ::卜晶粒路徑來取代晶粒 '線接合一接腳一 ^ - ::2較印刷電路板内接者少很多。通常將多重她電 刷電路板的有限空間。 小致佔用印 圖6中’ 一通用的先前技藝方法係將IC晶片組合於單— 封裝内,即使用堆疊晶粒IC封裝5〇,其中上面κ晶片“比 底下I C曰曰片1 4小,以便使底下I c晶片1 4可供線接合引線2 6 進出。若兩晶片大小相同,如圖7堆疊I c晶粒封裝6 〇所 示,則上面I C晶片1 6須與底下IC晶片偏置,以便讓線接合 ml 第6頁 \\312\2d-code\90-02\89124874.ptd 472327 五、發明說明(2) :二=ί下的1 C晶片14。如此會展H鱗 ν^ν·Ά八·尤、’但在裝配貫務上並不需要此種進出。另一 :習=技f用來組合尺寸相同“晶片的通用方法H曰曰 之下,如圖8示。在圖8丨c封f ^ 1 片片丨16係堆疊於晶片封裝引線框18上面,而底下的 缺^曰^配接於引線框18之下.。圖8在晶粒下方方法的 造步驟彼^•異^^象,®此需要兩個完整的IC製 3R〇stoker專利號碼5, 3 9 9’ m揭示在單 置於上述圖6盥7佔祕》址* 彳衣^置 k些配置係配 5, 656, 5 53揭;;—的種堆擊豐^方\上/人美國LeaS專利號碼 數# 種製iS方法及合成單片模組,包含一多 疊晶粒配置係利雨、息 3 3專利所示的堆 曰柄* ΐ利邊緣連接,將較上層粒層連接扒籽丁 a 曰曰粒。此種堆疊多重丨 曰逑接於杈下層 情況,但此方法沒有 :'午、兩相同晶粒堆疊的 下,若有任何;:有?因為電路傳達係垂直由上至 本發明目的在提供:多二業。 半導體I C晶片。 封义’具有兩或多個相似 相似IC曰=目的在提供—多晶片IC封裝,且有 相似1C曰曰片,但並不限制僅 /、有兩或多個 兩個完整的Ic製造步驟。b線接5於曰曰片一側,且無需 本發明另—目的在提供—多日片 彈性。 片1c封裝具有電路傳逹的
W \\312\2d-code\90-02\89124874.ptd 472327 五、發明說明(3) 【發明概述】 q t述目的可由雙晶粒積體電路封裝達成,具有由一晶圓 f : I: ί相同構成的兩晶片(晶粒)’似八城為我奂尨 尾應X像...應泰晶V片真樣彼專配考。第一晶片 2 =特定角度與第二角度對齊,使各晶片表面上至少一接 二墊片保持露出,供連接至標準晶片封裝内。在本發明一 :1 2 ’兩矩形晶片對齊使其中-晶片相對另-晶片轉 太I2度,使未重疊表面露出而致能晶片封裝裝配。在 實施例中’日日日片對齊角度小於9。度,使各晶片 尤^ &兩口日^刀,如角洛,露出供晶片封裝裝配。此實施例 中卞二:二皆ί正方形的情況。在本發明另-實施例 上,並轉動-角度,使ί下“配置於較小晶片之 制較小晶粒設計,;晶片上的能力,對僅控 很有利用價值。 处彳木蹲較大晶粒的1C製造商來說 本龟明可加倍晶片封裝的处“ 。口 相同大小的封裝尺寸,且僧此或圮憶體,而使用單晶片 電路封裝在㈣1傳達方= 設計。本發明” Μ射’夫、舰足讓Ic製'^^ ’ ..ί口!的 #/,即在同f 能力,且無需對,晶片作顯;;内使用多個相同晶片的 【實執本發明的最佳模式】' °又计改變。 圖1係本發明積體電路(丨 J封裝1 0第一實施例,包括
472327 五、發明說明(4) 日晶片14’彼此互以⑼度關係對 上6係配置於一弓丨線框18扁平晶粒配接表面12 :引線框18係由單片金屬製成,自晶粒配接表面Μ延伸 2〇 Ϊ下丈封裝1〇周®的外側引線2〇,及該外側引線 2〇向下延伸供IC封裝10裝設於外部印刷電路板。 r垃° f 1不’上面iC晶片U係利用"倒裝晶片"方法盥標準 曰曰片16與14的連接係經由各晶片上 成,可配置成對角或” X"式樣。 Λ 要凸/22形 造程序的部刀或利用電氣軌 ° σ形成原始製 說明使用再分配程跡;:=加入。_ 周圍。在圖2中,接合墊片49係配乂置虛/表二’配置… 1 7及底下晶片〗4的頂側J 5。接人 、面日日片1 6的底側 接至晶片封裝内的電I端子接:以^ 特別電路,如電源輸入,接地 :應曰曰片中的 夂首先,將-系列•接對 於曰曰片層的表面上,若僅需少數 成對角式樣置 成於晶片的角落,以減少晶片中問 L則銲接凸部可形 因為中間部分是記憶體陣列及心靈:::凸部的數量, .接著,提供傳達軌跡24於各晶 破電路放置的地方。 接接合墊片49至銲接凸部22。兩曰4 ’16表面上,以便連 如接地,電源輸入及時脈信號;;磁16共用的電路, 合嶋達至各晶“的特別銲以應
[W U\ \\312\2d-code\90-02\89124874.ptd
472327 五、發明說明(6) ί I!:引線ϋ :接至外部電路用,外部電路可提供電源及 其他輸入與輸出信號至晶片封裝j 〇。 圖4中’弓丨線框18晶粒配接表面12支持線接合⑼於 =與引線2G底下以片14。上面IG晶片16係以銲接凸部 連接於下1C晶片14。因為晶片係互為轉動9〇度,底下ic 晶片任一端部分係露出供線接合引線26連接用。一 再蓋在κ封裝1()的上面,包括兩晶片14,16及晶ς配 接表面1 2上面,使引線框1 8引線2〇保持至少部分露出。在 圖4中,已將覆蓋材料28切除,可見到丨c封裝丨〇的内部, 但在製造晶片封裝時,覆蓋材料2 8須完全的蓋在晶片丨4, 1 6上。覆蓋材料2 8以環氧樹脂外層或塑膠模製為佳。 圖5為本發明另一實施例。第二實施例的丨c晶片封裝3 〇 顯示上面1C晶片36係與底下1C晶片34以小於90度的角度對 齊。此種架構對正方形I C晶片很有用,但亦可用在矩形晶 片 上面1C晶片36與底下1C晶片34偏置一角度,以便露出 底下晶片34的區域38,供晶片34線接合至引線40。 本發明亦可施行於不同尺寸的兩晶片。在與圖5相似的 另一實施例中,上面I C晶片3 6較底下I C晶片大。由於上面 1C晶片36與底下1C晶片34相對轉動,即使較大的ic晶片36 係在上面,底下晶片34仍有一區域38露出供線接合進出。 這對僅控制較小IC晶片設計,自別處採購較大I C晶片,的 製造商來說頗為有用。 雖然本發明雙晶粒丨C封裝以上述PLCC (塑膠無引線晶片 載具)類型的封裝來說明,本發明雙晶粒I C晶片封裝亦可
五、發明說明(7) ::其他習知技藝類型的封梦— :蚌接凸部作為 設計,如 除了晶片封f鱼!陣列封裝及其他類J:片封裝連接至 外’其構成晶片封裝::“連接的特別方式不同 ic封裝利用上述相沾/白/、上述相同。本發明雙晶粒 如扁早白壯问的構造技術’可應用於薄封裝類型’ 亓杜绝A衣,或小型IC (SOIC )。 10 封裝 12扁平晶粒配接表面 14底下I C晶片 頂側 16 上面I C晶片 17 底侧 18 引線框 1 9 内側引線 2〇 外側引線 21 新純化層 2 2 焊接凸部 23 原始製造晶片層 24 傳達軌跡 θ 26 線接合引線 28 覆蓋材料 29 接合墊片 第12頁 \\312\2d-code\90-02\89124874.ptd 472327
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\\312\2d-code\90-02\89124874.ptd 第14頁
Claims (1)
- 472327 六、申請專利範圍 1. 一種雙晶粒積體電路封裝,包含: 一扁平雙晶粒配接表面,具有一多數外部電氣接觸,將 封裝連接至外部電路, 一第一 1C晶片,具有一第一表面及一第二表面,及具有 有一多數接合墊片於第一表面上,該第二表面係裝置於晶 粒配接表面上, 一第二1C晶片,具有一第一表面及一第二表面,及由其 第二表面機械與電氣連接至該第一 I C晶片之該第一表面, 其中苐·一 I C晶片係與苐一 I C晶片以斜向關係的特定角度對 齊,形成一覆蓋關係,使該第一 I C晶片之該第一表面上,之 接合墊片保持未覆蓋及電氣連接至晶粒配接表面的外部電 氣接觸,及 一覆蓋材料,包覆該第一與第二I C晶片及覆蓋一部分晶 粒配接表面,使多數電氣接觸保持至少部分未覆蓋。 2. 如申請專利範圍第1項之積體電路封裝,其中該第一 與第二I c晶片有相同的晶圓製造構造。 3. 如申請專利範圍第1項之積體電路封裝,其中該第一 與第二晶片有一矩形形狀。 4. 如申請專利範圍第1項之積體電路封裝,其中該對齊 之特定角度係9 0度。 5. 如申請專利範圍第1項之積體電路封裝,其中該對齊 之特定角度係小於9 0度。 6. 如申請專利範圍第1項之積體電路封裝,其中該第二 1C晶片之第二表面及該第一 1C晶片之第一表面包括一系\\312\2d-code\90-02\89124874.ptd 第15頁 47232? 、、申請專利範圍 曰曰片與該第-ic晶片之間的電 列銲接凸部,致能該第 氣與機械連接。 7.如申請專利範圍第!項之積體 配接表面係—引線框一部分,其中—夕$衣,其中該晶粒 晶粒配接表面的周圍上。 夕數引線係露出於該 8•如申請專利範圍第7項之積體電 引線係電氣連接於該第一與第二Ic曰$扁,其中該多數 於 間 該第〆I C晶片之該第—表面 ^ ,即以線接合連接 。 币^ ϋ亥多數接合墊片與引線之 9·如申請專利範圍第丨項之積體電 第〆1C晶片係以環氧樹脂装置於晶板配接、,其中”以 1曰。·Λ申二專/二圍第1項之積體電路封裝面其中該第二 I C晶片係大於ϋ玄第一 I C晶片及传梦罢+Λ ” , 日 你忒置於該第一 IC晶片上 面。 配接 凸部於晶片封裝底表面上。…並包括-系… 12.如申請專利範圍第6項之積體系列 銲接凸部係配置成對角式樣。 封滅其中 1 3.如申請專利範圍第6 β ^ ^ 銲接凸部係配置成π X形1'式樣。貝豆電路封裝,其中該糸, 1 4.—種雙晶粒積體電路 一引線框,具有一扁平^裝,包含: 於其周圍上, 曰曰粒配接表面,具有多數弓丨線置 U.如申請專利範圍第i項之積體電該晶粒 表面係球柵陣列型構造的— 接 於晶片封裝底表面卜。 並包括一糸歹J\\312\2d-code\90-02\89124874.ptd 第16頁 472327 六、申請專利範圍 一對1C晶片,各具有一第一表面與一第二表面及一周圍 包括兩平行相對寬度與兩平行相對長度,該I C晶片對之第 一 1C晶片具有一多數接合墊片於該第一表面上及其第二表 面係裝設於該引線框扁平晶粒配接表面,及該I C晶片對之 第二IC晶片係以其第二表面裝設於該第一 I C晶片之該第一 表面上,其中該第二1C晶片之該第二表面及該第一 1C晶片 之該第一表面包括一系列銲接凸部,該第一與第二I C晶片 係藉銲接凸起及銲接凸部的復流而電氣與機械耦合,其中 第二I C晶片係與該第一 I C晶片以斜向關係的特定角度對 齊,使該I C晶片長度偏置於該第一 I C晶片長度,其中該第 一 I C晶片之該第一表面上多數接合墊片至少一個保持未覆 蓋, 一多數線接合引線,電氣與機械耦合於該多數引線及該 第一 I C晶片之該第一表面上的多數接合墊片,及 一覆蓋材料,包覆該第一與第二I C晶片及覆蓋一部分晶 粒配接表面,使該引線框多數引線保持至少部分未覆蓋。 1 5.如申請專利範圍第1 4項之積體電路封裝,其中該第 一與弟二1C晶片有相同的晶圓製造構造。 1 6.如申請專利範圍第1 4項之積體電路封裝,其中該對 齊之特定角度係9 0度。 1 7.如申請專利範圍第1 4項之積體電路封裝,其中該對 齊之特定角度係小於9 0度。 1 8.如申請專利範圍第1 4項之積體電路封裝,其中該第 二I C晶片係大於該第一 IC晶片及係裝置於該第一 I C晶片上\\312\2d-code\90-02\89124874.ptd 第17頁 472327 六、申請專利範圍 面。 1 9. 一種雙晶粒積體電路封裝,包含: 一扁平晶粒配接表面,具有多數電氣接觸置於其上面, 一第一 1C晶片,具有一第一表面與一第二表面,其中一 多數接合塾片係配置於該第一表面上及其中該第二表面係 裝設於該晶粒配接表面上, 一第二1C晶片,具有一第一表面與一第二表面,及具有 一與該第一 I C晶片相同之晶圓製造構造, 其中該第二I C晶片該第二表面與該第一 I C晶片該第一表 面包括一系列銲接凸部,該系列銲接凸部係藉銲接凸起與 復流連接,使其電氣與機械耦合於該第一 I C晶片與該第二 I C晶片,其中該第二I C晶片係以一特定角度關係對齊該第 一 I C晶片,讓該第一 I C晶片該第一表面上多數接合墊月未 經覆蓋, 電氣耦合裝置,可用以電氣耦合該晶粒配接表面上的電 氣接觸與該第一 IC晶片之該第一表面上之多數接合墊片, 及 一覆蓋材料,包覆該第一與第二I C晶片,及覆蓋一部分 晶粒配接表面,使多數電氣接觸保持至少部分露出。 2 0.如申請專利範圍第1 9項之積體電路封裝,其中該晶 粒配接表面組成一部分引線框,多數引線係置於該晶粒配 接表面的周圍上。 2 1. —種雙晶粒積體電路封裝的形成方法,包含: 配一多數鮮接凸部於一第一 1C晶片之第一表面上及一第\\312\2d-code\90-02\89124874.ptd 第18頁 -----— 六、申請專利範圍 人=日日片之第一表面上 合軌跡配置於其上面, 夕* 配置一列值、查4 夕數 ,該傳達執i::於該第一與第二ic晶片之,笛 上將-鈍化層加於接凸部與接合藝片,表面 該銲接λ °〆弟—與第二晶片之言亥& Τ设凸#與接合 〆第—表 將該第··曰y !片保持穿過鈍化層露出,表面上’ , 斜向關係的特定角度鱼γ ,、垓第〜曰 經由么且μ扣. 日日片對 Ic晶片具有多 數接 上 齊 經由各晶片銲接凸 接於該第一晶片, 蚌接復流配接,將謗第二 將該第一晶片配接於你 〜晶片迷 之扁平晶粒配接表s:r多數電氣接觸機械與電氣接、 以覆蓋材料覆蓋該第—血 B 通 内側部分。 /、乐一日日月及該晶粒配接表面的 22.如申請專利範圍第 成方法,其中連接該第二二之二粒—積體電路封裝的形 一異向性環氧樹脂進行。 以—晶片的步驟係利用
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US09/458,264 US6376914B2 (en) | 1999-12-09 | 1999-12-09 | Dual-die integrated circuit package |
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EP (1) | EP1238430A2 (zh) |
JP (1) | JP2003516637A (zh) |
KR (1) | KR20020055603A (zh) |
CN (1) | CN1408125A (zh) |
CA (1) | CA2392975A1 (zh) |
MY (1) | MY135947A (zh) |
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-
1999
- 1999-12-09 US US09/458,264 patent/US6376914B2/en not_active Expired - Lifetime
-
2000
- 2000-10-23 WO PCT/US2000/041466 patent/WO2001043193A2/en not_active Application Discontinuation
- 2000-10-23 JP JP2001543781A patent/JP2003516637A/ja not_active Withdrawn
- 2000-10-23 CA CA002392975A patent/CA2392975A1/en not_active Abandoned
- 2000-10-23 EP EP00986833A patent/EP1238430A2/en not_active Withdrawn
- 2000-10-23 KR KR1020027007245A patent/KR20020055603A/ko not_active Application Discontinuation
- 2000-10-23 CN CN00816866A patent/CN1408125A/zh active Pending
- 2000-11-23 TW TW089124874A patent/TW472327B/zh not_active IP Right Cessation
- 2000-12-01 MY MYPI20005650A patent/MY135947A/en unknown
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CA2392975A1 (en) | 2001-06-14 |
WO2001043193A2 (en) | 2001-06-14 |
CN1408125A (zh) | 2003-04-02 |
US20010003375A1 (en) | 2001-06-14 |
WO2001043193A3 (en) | 2002-03-28 |
NO20022736L (no) | 2002-06-07 |
WO2001043193B1 (en) | 2002-05-30 |
EP1238430A2 (en) | 2002-09-11 |
MY135947A (en) | 2008-07-31 |
JP2003516637A (ja) | 2003-05-13 |
US6376914B2 (en) | 2002-04-23 |
NO20022736D0 (no) | 2002-06-07 |
KR20020055603A (ko) | 2002-07-09 |
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