TW201007920A - Memory package module - Google Patents

Abstract

Disclosed is a memory package module, primarily comprising a first semiconductor package and a second semiconductor package. The manufacture of the first semiconductor package is Chip-On-Board packaging on an inner surface of a module substrate to deposit a controller chip and to form a molding compound. The module substrate has a plurality of external fingers on its outer surface. The second semiconductor package is mounted on the outer surface without capping the external fingers by SMT technology. Therein, the molding compound covers the entire inner surface of a module substrate to make the external fingers and the second semiconductor package be supported above the molding compound.

Description

201007920 IX. Description of invention: [Technical field to which the invention belongs]

The present invention relates to a semi-thin composite. The B dry conductor device is particularly related to a memory package module. [Prior Art] The development of semiconductor memory devices towards miniaturization and capacity continues to grow at the same level of storage requirements as the 'susages, such as usb flash drives, record cards and solid state drives, etc. The increase in memory capacity is almost multiplied. In the past, the solution was to use a semiconductor process to produce a smaller diameter and a higher density of the dragon circuit, so that the memory capacity of the semiconductor chip was doubled, and thus the module substrate of the packaged semiconductor memory device had to be reworked. Line design. During the transition to the next __ generation, a five-replica package module known to increase the memory capacity but not yet change the semiconductor wafer is provided with a memory package structure on the upper and lower surfaces of the module substrate. The memory package module disclosed in US Pat. No. 7,074,052 has a memory package structure on the upper and lower surfaces of the module substrate by surface bonding (SMT), and the module substrate is provided on one side of the upper surface thereof. There are multiple external fingers. At the same time, the control chip is also disposed on the upper surface of the module substrate. Therefore, the two memory package structures and the control chip are all carried on the module substrate, and the material of the module substrate must be hard enough, otherwise the problem of bending deformation is easy. In addition, when the product is used, the module substrate must be subjected to repeated friction and compression on one side of the external finger. Therefore, a special housing with a support strip is required to be coupled with the module substrate. And covered with a memory package structure. This type of snap-in combination 201007920 will also have a problem of looseness after repeated use. In addition, the lower surface of the module substrate corresponding to the position of the external finger and the control wafer is not supported by the outer casing, so that space is wasted. SUMMARY OF THE INVENTION The main object of the present invention is to provide a memory package module that can select whether to increase the memory capacity after packaging. The second object of the present invention is to provide a memory package module, which can package different sizes of memory chips on the φ-module substrate, so that it is not necessary to redesign the module substrate and reduce the load-bearing inventory. Wafer risk. The object of the present invention and the technical problem thereof are to implement the following technical solutions to realize the memory package module according to the present invention, the main package 3, the fifth memory package structure and the second memory package structure. The first memory package structure includes a __module substrate, a first memory chip and a first sealant, wherein the module substrate has an inner surface and an outer surface, and the first memory chip system The inner surface of the module substrate is disposed on the inner surface of the module substrate and sealed by the first sealing body. The outer surface of the module substrate is provided with a plurality of external fingers. The third memory package structure is surface-bonded to the outer surface of the module substrate but does not cover the external fingers H. The first sealant system completely covers the inner surface of the module substrate to make the external contacts The second memory package structure is carried on the first encapsulant. In the above memory package module, the first memory package structure can further control the sweet sheet, which is disposed on the inner surface of the module substrate and sealed by the first gel. In the above memory package module, the module substrate is not covered by the second memory 201007920 body package structure, the m & I position and the corresponding portion of the first sealant are two plugged parts, wherein Some external fingerings are located on the plug portion. In the memory package module, the control chip can be located in the USB gold finger of the plug in the memory package module. The external fingerings may be arranged in parallel. In the memory package module, the module substrate is disposed on both sides of the plug portion to be covered by the first sealing body. In the above-mentioned memory package module, the outer surface of the module substrate may further include a plurality of bonding pads, and the second memory package structure includes a plurality of external terminals, which are coupled to the bonding pads. . In the above-mentioned memory module, the external terminals may be pins other than the lead frame, and the connecting wires may be arranged in a double row, and the arrangement direction thereof is parallel to the arrangement direction of the external fingers. . In the above memory package module, the first memory package structure may be in the shape of a block and have equal and parallel first and second sides, and the external fingers are adjacently arranged in parallel The first side. In the above memory package module, the second memory package structure has a width 'slightly larger than the length of the first side. In the above memory package module, the second memory package structure may include a first CMOS film and a second seal. In the above memory package module, the position of the second memory chip can be longitudinally corresponding to the first memory chip. In the above memory package module, the line density of the module substrate can be substantially concentrated on the inner surface of 201007920. The module substrate is attached to the inner surface of the module substrate in the memory package module. The first memory chip can be electrically connected directly to a plurality of bonding wires to the memory module package. The first semiconductor package structure can lack any memory chip, and the memory package module can be The memory chips required for the group are collectively packaged within the second semiconductor package structure. Xin❹ It can be seen from the above technical solution that the 'memory package module of the present invention has the following advantages and effects: using the module substrate to integrate the first-semiconductor package structure and carrying the second semiconductor package structure with the sealant The module substrate is externally connected, so that the plurality of memory chips are dispersed in different memory package structures. After the shock is sealed, whether the surface of the inner and outer surfaces of the module substrate can be fully increased by surface bonding is used. Using a plurality of memory chips> a first semiconductor package structure that can be integrated into the module substrate and a second semiconductor package structure that can be surface-bonded, and can be packaged on the same-module substrate for packaging different sizes of memory chips. There is no need to redesign the module substrate' and the risk of carrying the stock wafer is reduced. 0. The portion of the module substrate that is not covered by the second semiconductor package (4) and the corresponding portion of the first sealing body can be formed into one. The plug portion, under the structural support of the first sealing body, makes the fishing substrate more (four) and the first sealing body of the insertion portion can seal other wafers and seal the body, effectively utilizing the module space. 8 201007920 IV. The line density of the module substrate can be roughly concentrated on the inner surface to avoid line damage. 5. The first and second memory chips in different package configurations are longitudinally corresponding to each other so as to shorten the trace length difference between the module substrate and the memory chip. 9: utilizing the first memory chip which is indispensable in the first semiconductor package structure, and concentrating the memory chip required for the S-recovery package module in the second semiconductor package structure, The advantage is that the first semiconductor package structure having no memory capacity but having a control function can be separately fabricated from the second semiconductor package structure having only the memory capacity, and shortening the production of the memory package using the memory package module during the manufacturing process. The cycle is to increase the inventory turnover rate of the memory chip. [Embodiment] Hereinafter, the specific embodiment of the present invention will be described in detail with reference to the accompanying drawings. In order to explain the basic architecture or implementation method of the present invention, only the components related to the present invention are shown. The related components shown therein may not be in accordance with the actual number, shape, and size ratio, and some size ratios and The relevant size ratios may be modified or simplified to provide a clearer description of the actual implementation of the number, shape and size ratio It is an optional design and the detailed component layout can be more complicated. According to an embodiment of the present invention, a memory package module is illustrated in a cross-sectional view of Fig. 1 and a plan view of Fig. 2. The memory package module 10 mainly includes a first semiconductor package structure 100 and a second

The inner surface ln of the module substrate U is mounted and sealed by the first sealing body. In addition, the passive components (not shown) required for the sufficiency package module 1 can also be set. The inner surface of the module base no. 1U is sealed by the first sealing body 130. In the embodiment of the present invention, the control chip 14 can be directly attached to the inner surface m of the module substrate 11 and electrically connected to the module substrate no by a plurality of recording lines 160. Inscribed 塾201007920 semiconductor package construction 200. First, the semiconductor package structure 100 and the second semiconductor package structure 200 are different package types, and the memory package module 10 requires the memory chip to be mainly packaged in the second semiconductor. The package structure is internally packaged or packaged in a first semiconductor package structure, wherein the package is widely used (>° and the module required for the second semiconductor a 5 hidden package module 10 = board m, control) The chip 14A is integrated with the passive component or the like in the first semiconductor package structure 100. The length of the second semiconductor package structure is slightly smaller than the length dimension of the first semiconductor package structure (10) and the first semiconductor package structure (10) Upper portion to expose a plug portion. As shown in FIGS. 1 and 6, the first semiconductor package structure (10) includes a s-die, a base, a & 110, at least one control wafer 14A, and a first sealant 130. The first semiconductor package is a package type of an on-wafer ((5) P_〇nB〇ard, C〇B). The module substrate has an inner surface m and an outer surface 112. In the specific embodiment, the inner surface 111 is like As shown in Fig. 3, the outer surface 112 is as shown in Fig. 4. The inner surface 111 is referred to as the surface of the module substrate 11 which is sealed by the first sealing body; The module substrate no is not exposed by the first sealing body 130. The control wafer 14 is provided with 201007920 116. In different embodiments, the control wafer 14 can be flip-chip bonded (not shown in the figure) More specifically, except for a partial number or more than half of the number

In addition to the memory chip, the first semiconductor package structure 1 〇〇 already includes the active and passive components substantially required by the μ & body package module 10, such that before the second semiconductor package structure is bonded The first semiconductor package structure 100 can perform an active function of memory storage. The first semiconductor package structure 100 further includes at least one first memory chip 120 disposed on the inner surface 1U of the module substrate 11 and sealed by the first sealing body 130. . Typically, the first memory chip 12 is a flash memory or other non-volatile memory. In this embodiment, the first memory chip 120 can be directly attached to the inner surface 111 ′ of the module substrate 11 , and electrically connected to the module substrate 11 by a plurality of bonding wires 150 . First-inner pad 115. In various embodiments, the first memory wafer 120 can also be a flip chip bond (not shown) or a multi-wafer stack. For example, when the first memory chip 120 includes the first memory chip 120, the first semiconductor package structure (10) can be normally operated and has a certain memory storage capacity (for example, a coffee or a dish). When the memory package module 10 has twice or more memory storage capacity (such as a survey or a bias), the package may be selected after the package. The memory capacity is increased by surface bonding, and the area of the inner and outer surfaces of the module substrate UG is fully utilized. The outer surface of the module substrate U0 is provided with a plurality of external fingers 113 from the 112 system. The external terminals of the memory package module (4) are generally arranged in a certain order on the outer surface 112. The module 11 201007920 substrate 110 should have the line structure required for the memory package module 1 . So that the external fingers 113 can be electrically connected to the memory chips ^0 and 220. Further, the second semiconductor package structure 2 is bonded to the outer surface 112 of the module substrate no but not cover Refers to the plurality of external ιΐ3. 'Engages the front surface of said methods may utilize a solder 300 or other electrically conductive connection element' More specifically 'h shown in FIG. 4, the outer surface of the module substrate 11〇

The 112 series may further include a plurality of bonding pads 114 on the same surface as the external fingers but in different regions. Further, as shown in Figs. 2 and 5, the second semiconductor package (four) 200 series including a plurality of external terminals + 21 结合 can be bonded to the bonding pads 114 via solder. The external terminals 2'1" may be - 5 feet outside the lead frame or may be selected from a connection port of a substrate or a fresh ball or the like. The second semiconductor package structure 2 can include the second memory chip 220 and a second encapsulant 23A. Preferably, the position of the second memory chip (10) is longitudinally corresponding to the first memory chip 12 以 to shorten

The distance between the external fingers 113 of the module base & 11G to the memory chips 12 and 220 is different. In the present embodiment, as shown in FIGS. 2 and #, the second semiconductor package structure 200 is a TSOP' Thin Small Outline Package, and the lead pins of the lead terminals are connected to the external terminals. Attached to one of the active surfaces of the second memory chip 22, and electrically connected to the plurality of pads 221 of the second memory chip 22 and the leads of the lead frame by a plurality of bonding wires 240, thereby electrically Sexually connected to the external dice 210. However, the second semiconductor package structure 2 (10) may also be selected from a BGA package, a LGA package, and a small-sized appearance without an external package structure. 12 201007920 (SON package) One of the semiconductor package structures such as a quartet flat package and a bump package carrier structure (BCc package, Bump Chip Carrier package). The first encapsulant 130 completely covers the inner surface 111 of the module substrate, so that the external fingers 113 and the second semiconductor package structure 200 are carried on the first encapsulant 130. (As referred to in Figure ii, "bearing" as used herein means that the force applied to the external finger 3 and the second semiconductor package structure 2 during the use of the product or during the surface bonding process is passed through The module substrate 110 is conducted to the first encapsulant 13〇 to prevent the module substrate 110 from being separately stressed. The first encapsulant 13 can be a molding compound (EMC) with good hardness and electrical insulation. And the covering property can make the external finger H3 and the second semiconductor package structure 2 〇〇 get a good 2 ′′. There is no need to separately design a special outer casing with a support strip, and there is no problem of looseness. Therefore, there is no problem of f clock and deformation during the surface bonding process of the second semiconductor package structure 2 (10) or the use of the product. Generally, the total thickness of the first sealing body m and the module substrate 11 () is approximately Provides good strength support for 1 3_ j. The second semiconductor package structure 200 includes the thickness of the first semiconductor package structure (10) after surface bonding (that is, the thickness of the memory package module is 2.6 mme. Further, preferably the first cover (four) (four) of the external fingers 113 The other components, such as the control wafer U0', can be sealed to effectively utilize the limited space of the memory package module. Second, the control wafer 140 and at least the memory chip 22 are used to reach the first semiconductor capable of integrating the module substrate 110. Package structure 〇〇 〇〇 可 13 201007920 σ second semi-conductive package structure is fine. - semiconductor package structure · semiconductor package structure size can be modularized, applicable on the same - module substrate m In order to package the memory chips of different sizes, it is not necessary to redesign the module substrate, and the risk of carrying the stock wafer is reduced. In the embodiment, the module substrate 11G is not covered by the second semiconductor package structure 200. And the corresponding portion jr of the first sealing body (10) is formed as a plug portion 1G1, wherein the external fingers ι 3 are located on the plug portion 1〇1. In the first sealing body 1 The structural support of 30 makes the module substrate no more pluggable, and the gel portion 13 located in the plug portion 101 (4) can seal other wafers and be sealed, effectively using the module space. Preferably, the control The wafer 140 can be located in the plug portion 1〇1 to be sealed by the first sealing body 130, and can shorten the electrical transmission path of the control chip 140 and the external fingers (1) and effectively utilize the inside of the first sealing body 13G. In the embodiment t, the external fingers 113 can be parallel-arranged gold fingers (as shown in FIG. 2) for use as a communication interface, so that the memory package module U) becomes - There are different packaging methods (4) and the following is deleted. Preferably, as shown in FIG. 2, the module substrate m is cut on both sides of the plug portion 101 and can be cut from the side of the first sealing body 130. The module substrate 110 can be arranged in a plurality of matrix rows in a substrate strip to form a large-sized sealant in a matrix array package (MAP, Mold Array Packaging). The first colloid 13〇 is combined with the module substrate 110 Things. In a preferred embodiment, as shown in FIG. 3, the module substrate 11 is replaced by 201007920

Most of the required lines 117 are formed on the inner surface m, so that the line density of the module substrate 11 can be substantially concentrated on the inner surface ill. Under the cover protection of the first sealing body 130, the circuit of the module substrate can be prevented from being damaged. In addition, the portion of the line 117 is connected to the first inner pad 115 or the second inner pad 116 to the corresponding via hole 118, and is electrically connected to the external fingers 113 or the bonding pads 114. Therefore, by using the circuit structure of the module substrate 11 , the external fingers 113 can be electrically connected to the control chip 140 first, and then electrically connected to the first memory chip 12 and the different package types. - A s memory wafer 220, which has practicality. In the detailed description of the second embodiment, the external terminals 21 of the second semiconductor package structure 200 may be pins other than the lead frame, and may extend beyond the two sides of the second sealing body 230. (As shown in FIG. 5), if the surface bonding relationship on the first semiconductor package structure 1 is not considered, the first semiconductor package structure 100 cannot carry the second semiconductor package structure 2GG with a limited width. Therefore, as shown in Fig. 4, the mats m can be arranged in a double row, and the direction of the column and the direction of arrangement of the external fingers are parallel to each other. When the width of the second semiconductor package structure 2 is slightly greater than or equal to the first semiconductor package structure 1 , the external terminals can still be bonded to the bonding pads 114 to make the second semiconductor package structure effective. The first semiconductor package structure (10) is limited in width. More specifically, the reason why the first semiconductor package structure 1GG requires a limited width is based on the fact that the first plug portion (8) (for example, a USB plug) on which the external fingers 113 are provided has a fixed specification limit and is expected to be It achieves the effect of miniaturization and easy singulation. Preferably, as shown in FIG. 2, the first semiconductor package structure 100 may be brick-shaped and have equal and parallel first sides 102 and second sides 1〇3, The external fingers ι 3 are arranged adjacent to each other in parallel to the first side 102. In the fabrication of this preferred structure, the first semiconductor package structure 100 can be obtained by straight sawing after extensive area camination. In the present embodiment, the length of the first side 1〇2 and the length of the first side 103 are each about 12 3 mm. More preferably, the second semiconductor package structure 200 has a width 201 slightly larger than the first side by using the above-mentioned arrangement of the bonding pads 114 and the shape of the first semiconductor package structure 1 . The length of the side 102, the side terminals parallel to the width 2〇1 are arranged with the external terminals 21G, and even if so, can be effectively carried by the first semiconductor package structure 1厚度 with limited thickness (such as 2 is shown). In the present embodiment, the width 2 〇 1 is about 12.4 mm. Therefore, the second semiconductor package structure 200 can adopt a fixed package specification, such as Ts〇p48 or ts〇P5. In the preferred structure, the present invention can make the Ts〇p package specification second. The semi-conducting package structure 2 is carried by a first semiconductor package 351 of a monumental shape with a width limited and encapsulated in 0 COB, and the first plug portion 101 is exposed by the first semiconductor package structure 1 The specifications of the brain plug (as shown in Figures ! and 2) can be packaged, such as the control chip 14 ,, and the use of the limited space of the module substrate 110 to achieve miniaturization and modularization, and has practical value. The first semiconductor package S(10) can be directly shipped (as shown in FIG. 6). 'The module factory selects whether to surface-bond the second semiconductor package structure 200, and the second semiconductor is not surface-bonded in the same-size. The package structure 200 can provide a memory package module with a specific memory capacity. When the surface is bonded to the second semiconductor package structure 2, the memory package module of the memory 16 201007920 髅 capacity expansion can be provided. In the first semiconductor package structure, the first memory chip 12 缺乏 can be lacking, and the memory chip required for the memory package module 1 can be collectively packaged in the second semiconductor package structure 2 . In the case, the first semiconductor package structure 100 having no memory capacity but having a control function can be pre-fabricated, and the second semiconductor package structure 200 having only the memory capacity can be standardized and mass-produced. Because the price fluctuation of the φ memory chip is quite large, it can wait for the price to be better. It can be mass-produced by surface bonding, shortening the production cycle of the memory chip using the memory package module (7). That is to say, in the process of fabricating the memory chip from the wafer state to the memory package module, the manufacturing process of the first semiconductor package structure (ie, the fabrication of the first semiconductor package structure) does not require the addition of a memory chip. Therefore, it is possible to increase the inventory turnover rate of the memory chip and reduce the number of stocks to be manufactured. As described above, it is only a preferred embodiment of the present invention. The present invention is not limited to the scope of the invention. The scope of the present invention is subject to the scope of the appended claims. Any one skilled in the art can make a few modifications or modifications using the technical contents disclosed above. Any simple modifications, equivalent changes and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solutions of the present invention. A cross-sectional view of a memory package module according to one embodiment of the present invention. 17 201007920 FIG. 2 is a top view of the memory package module according to an embodiment of the present invention. According to an embodiment of the present invention, a schematic diagram of an inner surface of a module substrate of the memory package module: a fourth circle: an external surface of the module substrate of the memory package module according to an embodiment of the present invention .

Figure 5 is a top plan view of a second semiconductor package structure of the memory package module in accordance with an embodiment of the present invention. Figure 6 is a cross-sectional view showing a first semiconductor package structure of the memory package module in accordance with an embodiment of the present invention. [Main component symbol description] 101 plug portion 112 outer surface 115 first inner pad 118 via hole 121 pad 150 wire bond 10 memory package module 100 first semiconductor package structure 102 first side 103 second side 110 Module substrate 111 inner surface 113 external finger 114 bonding pad 116 second inner pad 117 line 120 first memory chip 13 〇 first encapsulant 140 control wafer 160 bonding wire 200 210 230 201 width body wafer 221 pad second Semiconductor sealing structure external terminal 220 second memory second sealing body 240 bonding wire 300 solder 18

Claims (1)

201007920 X. Patent application: 1. A memory package module comprising: a semiconductor package structure comprising a module substrate, at least one control chip, and a first encapsulant, wherein the module substrate has an inner The surface and the outer surface are disposed on the inner surface of the module substrate and are sealed by the first sealing body. The outer surface of the group substrate is provided with a plurality of external fingers; The second semiconductor package structure is bonded to the outer surface of the module substrate but does not cover the external fingers; the first capping system completely covers the inner surface of the module substrate to make the The external finger and the second semiconductor package structure are carried on the first encapsulant. The memory package module of claim 1, wherein the first semiconductor package structure further comprises at least one first memory chip disposed on the inner surface of the module substrate and configured by the first A gel is sealed. 3. The memory package module of claim 1, wherein the portion of the stencil module that is not covered by the second semiconductor package structure and the corresponding portion of the first sealant are formed as a plug portion The external fingers are located on the plug portion. 4. The memory package module of claim 3, wherein the control chip is located in the plug portion. 5. The memory package module of claim 3, wherein the external fingers are parallel gold fingers. The memory package module of claim 3, wherein the module substrate is located on both sides of the plug portion and is flush with the side surface of the first sealant. 7. The memory package module of claim 1, wherein the outer surface of the module substrate is further provided with a plurality of bonding pads, and the second semiconductor package structure comprises a plurality of external terminals, It is bonded to the bonding pads. The memory package module of claim 7, wherein the external terminals are pins outside the lead frame, and the bonding pads are arranged in a double row, and the arrangement direction is The alignment directions of the external fingers are parallel to each other. The memory module module of claim 1, wherein the first semiconductor package structure is brick-shaped and has equal and parallel sides-side and second side 彡, The external fingers are arranged adjacent to each other in parallel on the first side. The memory package module of claim 9, wherein the second semiconductor package structure has a width that is slightly larger than a length of the first side. The memory package module of claim 7, wherein the second semiconductor package structure comprises at least a second memory chip and a second seal. The memory package module of claim 2, wherein the first semiconductor package structure comprises at least a second memory chip and a position of the first encapsulant 'the second memory chip No. 20 201007920 The memory chip corresponds to the vertical direction. 13. The memory package module of claim 1, wherein a line density of the module substrate is substantially concentrated on the inner surface. The memory package module of claim 2, wherein the first memory chip is directly attached to the inner surface of the module substrate, and is electrically connected to the plurality of bonding wires. Module substrate. 15. The memory package module of claim 2, wherein the second semiconductor package structure is a thin small outline package structure (TSOP). The memory package module of claim 1, wherein the second semiconductor package structure is selected from a BGA package, a planar array package structure (L(3A package), The small-size appearance has no external package structure (s〇N package), square flat no-pin package structure (QFN package) and bump wafer carrier package structure (BCC package). The memory package module of claim 1, wherein the first semiconductor package structure lacks any memory chip, and the memory chips required by the memory package module are collectively packaged in the second semiconductor package structure. The first semiconductor package structure of a memory package module, comprising a module substrate, at least one control chip, and a first seal body, wherein the module substrate has an inner surface and an outer surface, the control chip The sigh is placed on the inner surface of the module substrate and sealed by the first sealant, and the outer surface of the module substrate is provided with a plurality of external fingers and is available for 21 201007 920. Surface bonding—a second semiconductor package structure. 19. The semiconductor package structure of the memory package module according to the above-mentioned claim, further comprising at least one first memory chip, The inner surface of the module substrate is sealed by the first encapsulant. The semiconductor package structure of the memory package module according to claim 18, wherein the module substrate is not The second half The portion covered by the body package structure and the corresponding portion of the first seal body are formed as a plug portion, wherein the external finger fingers are located on the plug portion. The first semiconductor package structure of the memory package module of claim 20, wherein the control chip is located in the plug portion. The invention relates to a first semiconductor finger of a memory package module according to the second aspect of the invention, wherein the external fingers are parallel arranged USB gold fingers. The first semiconductor package structure of the memory package module according to the patent application 帛20 #, wherein the module substrate is located on both sides of the plug portion and is aligned with a side surface of the first sealant. The semiconductor package structure of the memory package module of claim i, wherein the outer surface of the module substrate is further provided with a plurality of joints 并且 and the joint rafts are arranged in a double row. The alignment direction is parallel to the arrangement direction of the external fingers. Apply for patent coverage! The memory package module of claim 8 or 24, wherein the first semiconductor package structure is brick-like and has equal and parallel first sides and a second side 22 201007920 side The first external semiconductor package structure of the memory package module according to claim 18, wherein the external density of the module substrate is substantially parallel to the first side of the first semiconductor package Focus on the inner surface. The first semiconductor package structure of the memory package module according to claim 19, wherein the first memory chip is directly attached The inner surface of the module substrate is electrically connected to the module substrate by a plurality of bonding wires. 28. The first-bump conductor package structure of the memory package module of claim 4, wherein the first semiconductor package structure lacks any memory chip. twenty three