TW461071B - Semiconductor device and method of producing the same - Google Patents
Semiconductor device and method of producing the same Download PDFInfo
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- TW461071B TW461071B TW089122958A TW89122958A TW461071B TW 461071 B TW461071 B TW 461071B TW 089122958 A TW089122958 A TW 089122958A TW 89122958 A TW89122958 A TW 89122958A TW 461071 B TW461071 B TW 461071B
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Description
461071 五、發明說明(1) 【發明之背景】 技術箱 jg 本發明有關於半導體裝置及其製造方 層具有LSI之半導體晶 去’尤-有關於積 製造方法。矛屋生電逯接之半導體裝置及其 前技输 ^年來為著使LSI半導體裝置低成本 詖案有半導體裝置其中以面向下之方式人且化,所以处 之LSI或具有由不同之處理所形成之⑻之;“::功此 置下面:參照圖1 6用來說明上述之習知之LSI A"體裝。 夕二百先,在第1半導體晶片110之上形成第1半導月 之内部電極(第1内邻雷杌、·Μ1_ί驻μ ' 乂弟1牛―體日曰片 内邻雷搞η Γ )和裝片觀塾112,另外在第1 邻電和111上形成第!半導體晶片之障壁金 屬)113,和第2半導體晶片之内部電極(第2内部電極^21’ 上之第2半導體晶片之障壁金屬(第2障壁金屬 接塊123與第2半導體曰ηι?π μ夕屬)22、丄由知 、击社^:牛導體阳片120上之第2内部電極121互相電 第1半導體晶片U〇和第2半導體晶片120之 間充填有絕緣性樹脂丨30,第!半導體晶片11〇和第2半導體 晶片120經由焊接塊;[23和絕緣性樹脂丨3〇形成一體。 肢 第1半導體晶片11 〇被裝片樹脂! 3 2固定在引線框架之裝 片襯墊1 3 1,和第1半導體晶片1 j 〇之合接襯墊j j 2和引線框 架之外部引線1 3 3經由合接線1 3 4產生電連接。第1半導體 晶片110,第2半導體晶片120·,合接線133,裝片襯墊131 和外部引線1 34之一部份被密封用樹脂1 35封裝。 C:\2D-03DE\90-01\89122958.ptd 第4頁 461071 五、發明說明(2)
下面將參照圖m〜17D用來說明上述之半f 造方法。首先,如圖】7A所示體裝置之I 。片120之内部電極⑴形成焊接塊123 :第:導 金屬_,利用抗_成焊 鍍:來形成焊接塊123。其次以焊接塊123作為逆/齊;電田 濕式蝕刻溶解除去第2障壁金屬122之後,使焯H,利用 打逆流成為半球狀。《次如圖j 7β所示:在第、曾* =3進 110為晶圓狀態時,在第}半導體晶 上 ¥晶片 :使第2半導體晶麵之焊接調和第;以 110之内部電極m-致。其次如圖17C所示H曰曰片 晶月120設置在扪半導體晶片11〇。然後:第2 +導體 接塊1 23熔融,利用焊接用來使第2半導體曰曰=熱使焊 電極121和第i半導體晶片u。之内部電極u曰進J2 =内, 次如圖17D所示,將第丄半導體晶片11〇從晶 口 。二 為個別狀態。最後如圖1 6所示,將第i半導 L为割成 在引線框架之裝片襯墊131,利用線合接使第/半片 11 0之合接襯墊j丨2和引線框架之外部引線丨33 a曰曰 以密封用樹脂1 3 5進行封裝。 订連接’ 但是,依照上述之習知之半導體裝置之構造和 時,因為第1半導體晶片和第2半導體晶片之 二^方法 接塊進行焊接,所以會有下面所述之問題。 疋用焊 (1)因為以面向下方式將第1半導體晶片積層 體晶片’所以晶片只能積層2段。 牛導
C:\2D-CODE\9O-0l\89122958.ptd 第5頁 461071 五、發明說明(3) 使用金屬:塊,:::::T層,第2半導體晶片時,因為 (3…妾合時因 尺寸變化,所以Λ 焊接塊依橫方向擴散產生 ^所以要微細化會有困難。 (4)因為通常之半導難 行焊接接合時如牛導體曰曰:之内部電極為Ai,戶斤以要進 如形成Ti—⑸一“等=:成容易擴散之金屬膜’例 μ 2 \因為η微細化困難,所以第1和第2半導體晶片之内部電 诚ί t! π *此電負载容量變大,第1半導體晶片和第2半導 曰曰S之彳§號傳送其延遲會變大而且電力消耗亦變大。 【發明之概要】 因,^發明之目的是解決上述之問題,提供容易微細連 接之问此之半導體襞置及其製造方法,不會使晶片受損 而且可以積層多片之晶片。 本t月.之§申_清專利範圍第1項是一種半導體裝置,具備 有1半導體晶片’具有外部電極和内部電極;和第2半 導體晶片,具有内部電極;在第1半導體晶片,具有間隙 :f層第^半導體晶片’和使内部電極互相電連接;其特 被疋·在第2半導體晶片之内部電極内設置穿通孔,在該 穿通孔内壁以與其他電極絕緣之狀態形成可無電解電鍍之 電極’和以使第1和第2半導體晶片之内部電極之間成為對 f之方式’利用接著劑將第2半導體晶片固定在第1半導體 晶片之外部電極和内部電極以外之部份,第2半導體晶片 之内部電極和穿通孔内壁之電極與第1半導體晶片之内部
C:\2D-C0DE\90-0]\89122958.ptd 第6頁 461071 五、發明說明(4) 電極,經由相同成分之連續金屬產生電連接。 依照此種方式,經由在第2半導體晶片之内部 y
穿通孔’ f口以接著劑積層第!和第2半導體晶片電可以積層 多Ϊ Ϊ晶片而不會使晶片受損。$外,形成在穿通孔内ΐ 之可無電解之電極為Cu、Ni、Au、Pt、Ag .、Sn、Ph、P :導ί 2曰'導體晶片之内部電極和穿通孔内壁之電極與。第1 ::體:片之内部電極’經由相同成分之連續金屬產生電 連,。因此,不使用習知方式之以焊接塊接合,因為利用 鍍直接析出在内部電極之金屬進行接合,所以 生擴散之金屬。 嫩上預先形成使焊劑產 I請專利範圍第2項之半導體裝置是在申請專 H第2半導體晶片之内部電極内之穿通孔之直經小$ +導體晶片和第2半導體晶片之間隙之1/2。依照此種 "式,因為第2半導體晶片之内部電極内之穿通孔之直 裣、小於第1半導體晶片和第2半導體晶片之間隙之i 2 , =以I,確貫的連接。亦即,通常為著使無電解電鍍膜成 長進1等方成長’所以使穿通孔直徑成為間隙之丨/2以 上、’當成長之金屬之電鍍膜接觸在電極上時,因為穿通孔. 未被埋沒’所以電鍍液會殘留在電鍍電極内部。該殘留之 電鍍液成為造成腐蝕之原因,所以上述方式之設定用來使 電鍍液不會殘留在電極内部。 μ申請專利範圍第3項和第4項之半導體裝.置是在申請專利 Ιϋ圍第1項中’將第2半導體晶片積層2個以上之晶片。依
4 6 1 07 1 五、發明說明(5) 照此種方式,因為將第2半導體晶片積層2個以 所以可適於應用在多接腳Ls I。 日日月 申請專利範圍第5項是一種半導體裝置之製造 包含之工程有:在積層於第1半導體晶片之第2半導 之内部電極内設置穿通孔;在穿通孔内壁和背面 = 膜;利用無電解電鍍或蒸著,在穿通孔内壁^益電解 電鍍之電極;以使第i和第2半導體晶片之内部U 為對應之方式’在對第1半導體晶片具有間隙之狀能間將 第2半導體晶片接著固定在第i半導體晶片之外部電:内 部電極以外之部份;和利用無電解電鑛使第曰^ 電極產生電連接。 騷日日片之内部 J照此種方式,因為在第2半導體晶片之 4 置穿通孔,接著固定第j和第2丰導鲰曰 電極内6又 ,5 #,J ^^« I电極和穿通孔内壁之雪&故1 半導體晶片之内部電極產生電連接,戶斤以可 ,、第 =不會使晶片受損。另夕卜,因為利用無電解;; 者在穿通孔内壁形成可無電解電鍍之電極 H ^ 知方式之以焊接塊接合,不需要在晶 形成使焊劑產生擴散之金屬。作為電 =二員先
Cu、Au、Pt、Ag、Sn、pb、c〇 等。另夕,::使用 接塊之擴散,戶斤以微細之連接變為容易,可 接腳LSI。另外,LSI晶片間之接合為單側之、,應^在多 晶圓狀態進行連接,可以使成本降低。 ',,坐由以
C:\2D-〇®E\90_01\89122958.ptd
461071 五、發明說明(6) 申請專利範圍第6、7、8項之半導體裝置之製造方法分 別具有與申請專利範圍第2、3、4項同樣之效果。 【較佳實施例之說明】 下面將根據圖1〜圖1 5用來說明本發明之實施形態。圖1 是本發明之實施形態之半導體裝置之剖面圖,圖2是圖1之 主要部份擴大圖,圖3〜圖1 5是工程別剖面·圖,用來表示 本發明之實施形態之半導體裝置之製造方法。 在圖1和圖2中,元件編號1是第1半導體晶片,2是半導 體晶片之保護膜,3是第1半導體晶片之外部電極,4是第1 (. 半導體晶片之内部電極,5是接著劑,6是穿通孔,7是第2 I 半導體晶片,8是第2半導體晶片之内部電極,9是第3半導 體晶片,1 0是第3半導體晶片之内部電極,1 1是第2半導體 晶片之氧化膜,1 2是第3半導體晶片之氧化膜,1 3是第2半 導體晶片之電鍍電極(第2電鍍電極),14是第3半導體晶片 之電鍍電極(第3電鍍電極),15是電鍍電極(第2金屬),16 是裝片樹脂,1 7是引線框架之引線,1 8是引線框架之裝片 襯墊,1 9是合接線,2 0是密封樹脂,2 1是由第2半導體晶 片形成之晶圓,2 2是由第3半導體晶片形成之晶圓,2 3是 無電解電鍍液,24是無電解電鍍槽,25是電鍍金屬膜(第1 (I 金屬),2 6是抗蝕劑,2 7是蝕刻液,2 8是蝕刻槽,2 9是第1 半導體晶片之晶圓,3 0是彈性夾,3 1是彈性夾之真空孔, 3 2是切片之溝,3 3是絕緣樹脂,3 4是氧化膜。 如圖1所示,具有外部電極3和内部電極4之第1半導體晶 片1和第2、第3半導體晶片7、9,以具有間隙以狀態,除
C:\2D-CDDE\90-01\89122958.ptd 第 9 頁 461071 、發明說明(7) :外Π極3 =電極4、8、10之部份外,被接著劑5固 μ . ^ '第3半導體晶片7、9在第2、第3半導體曰 ::電極8、1。内具有穿通孔6達曰曰 匕穿3Γ二和Λ2、第3半導體晶片7、9之背面形成有 件互相H 氧化膜11、12,用來保持與内部元 進行::圖1和圖2所示,在穿通孔内壁形成有可以 二:無,_之電極13之〜,了以 孔6盥〇證·! i第2、第3半導體晶片之内部電極8、1 0和穿通 電铲電: f Γ晶片之外部電極4,'經由相同成分之連續 电緩電極15產生電連接。 貝 圖=:明上=;之半導體裝置之製造方法,首先如 曰A 3B所不,利用雷射在由第2、第3半導體晶片構成之 直徑1 〇 22之第2 «1第3半導體晶片之内部電極8、1 0進行 二// m程度之穿通孔6之開孔。内部電極之尺寸可以為 由s ϋ道其次曰如圖4a、4B所*,在穿通孔6之側面和 2 % 第3半導體晶片構成之晶圓21、22之背面,形成第 用、導體晶片之氧化膜11、12。該氧化膜11 42在利 :無::電鑛法形成電極時’成為用來與半導體晶片之内 4凡件產生絕緣之絕緣膜。 =如圖5A、5B所示’在由第2、第3之半導體晶片構成 :am ' 22和穿通孔6 ’利用無電解電鍍在晶圓全面形 鑛金屬膜25。例如’當利用無電解電鍵所形成之電鑛 至屬膜25為Ni之情況時,將纟第2、3 +導體晶片構成之晶 圓21、22浸潰到氯化紅之溶液,纟晶圓全面附著作為無電
C:\2D-00DE\90-01\89122958.ptd 第10頁 461071
解電鍍核之鈀後,浸潰到無電解N i電鍍液,用來形成 為程度之Ni電鍍金屬膜25。其次如圖6A、6b 、 由第2、第3半導體晶片構成之晶圓21、22之第2、第^车道 體^曰片之内部電極8、1 0和穿通孔6,形成抗蝕劑圖型萨 經由抗飯劑除去電鍍金屬膜25。 θ
士其次,如圖7Α、7Β所示,將由第2、第3半導體晶 抗蝕劑26形成有蝕刻圖型)構成之晶圓21、22浸漬到蝕 槽28中之蝕刻液27,用來對電鍍金屬膜25進行溶解蝕刻。 例如在電鍍金屬膜為N i之情況時,利用2 〇 %鹽酸溶液用 ==其次如一 第3半導體晶片構成)之抗蝕劑2 6,藉以形 成第、苐3電鑛電極13、14。其次如圖9A、9B所示,對由 第2、第3半導體晶片構成之、22 割成各個晶片。 ^ ^ 其次如圖1 0所示,在由第丨半導體晶片j構成之半導晶圓 29之後,塗布環氧樹脂、聚醯亞胺樹脂、.丙
成為在裝載第2半導體晶片7之位置不會阻二 一曰曰片之内部電極4和外部電極3之方式。其次如圖j J 所示在由第1半導體晶片構成之晶圓2 9之塗布有接著劑5 之區域、’以使内部電極4、8之間成為一致之方式,利用彈 )生夾3 0以真空吸著之狀態,面向上的設置第2半導體晶片 7 ° ’利用彈性夾3()之加熱用來使接著劑5硬化藉以將 第2丰V體晶片7固定在由第】半導體晶片構成之晶 上。加熱溫度為1 〇 〇 °c〜3 〇 〇它程度。内部電極4、8之大小
C:\2D-CODE\90-01\89]22958.p td 第11頁 461071 五、發明說明(9) --- 為數□〜100 □程度’小於用以連接第2半導體曰 7和由第1半導體晶片構成之晶圓29所用之電極。另外阳〜 時之第1半導體晶片丨和第2半導體晶片7之表面間之間隙= 數// m到1 00 # m。另外,接著劑5被配置成不會流到^部電 極4、8之表面。經由重複進行此種工程,可以在由第半 導體晶片構成之晶圓29上利用接著劑5固定多個之第2本 另外,如圖1 2所示,在第2半導體晶片7上塗布環氧樹 脂、聚醯亞胺樹脂、丙烯酸樹脂等之接著劑5,.使其' 以裝載第3半導體晶片9之位置不會阻塞内部電極8。其次 如圖1 3所示,在第2半導體晶片7之塗布有接著劑5之^久 域,以使内部電極8、】〇之間成為一致之方式,利用^ 夾30以真空吸著之狀態而向上的設置第3半導體晶片9。麸 後利用彈性夾30之加熱使接著劑5硬化,用來將第 ^ 晶片9固定在第2半導體晶片7上。 等體 其次如圖14A、14B所示,將由第1半導體晶片構成之曰 圓29浸潰到無電解電鍍槽24 ’用來使從形成在第j半: 晶片之内部電極4和第2、第3半導體晶片之内部電極8、i 之第2、第3電鍍電極】3、14析出之電鍍金屬,成為— 形成電鍍電極15。利用電鍍電極15使第2半導體晶片丄 電極4和第2、第3半導體晶片7、9之内部電極8產 電連接。這時,使無電解電鍍液23浸入到由第i半導 片構成之晶圓2 9和第2、第3半導體晶片7、9之間隙 孔6。例如,在第1半導體晶片之内部電極4為乂丨,進行無
461071 五、發明說明(ίο) - 電解電鑛析出之金屬為N i之情況车 酸等之溶液,在除去第!半導月體兄曰時片’夕首先浸潰到石肖酸、破 之氧化膜後,以鋅等替換以面曰日。片之内部電極4之Μ表面 2、第3半導體晶片7、9之第2、面另外,使用與形成在第 無電解電鍍液’在第2、第3第鍍電極13、U相同之 解電鍵之金屬,可以以相同 、!4上亦析出無電 3半導體晶月之内部電極4、8 ^鐘金屬連接第1、第2、第 表面更進行金屬之無電解 。這時在電鑛金屬Ni之 合接線等接合到外部電極3上又日、^以用來提高可靠度,和使 浸潰到各種溶液之處理之 夺了以大幅的提高良率。在 然後,實施下一個i處理'利水等之溶液進行洗淨, 之以焊接塊接合,而是利用:此種方式,不是習知方式 極之金屬進行接合,所以 …、電解電鍍直接析出在A1電 成用以使焊劑產生擴散之々^要習知方式之在A1電極上形 之晶片之接合一起進行接人 和在晶圓狀態可以使全部 率,和以低成本實現高二=以可以大幅的提高生產效 其次如㈣所示;=之連接。 行切片使其分離成為第j丰2導體晶片構成之晶圓2 9進 第1半導體晶片1之前,對第片1。其巾,在分離成為 檢測,第i半導體晶片體晶片之外部電極3進行( 片上可以以接合之狀態進行特:晶:7及第3半導體晶 3 3设在側部。 、 取—。另夕卜,將絕緣樹脂 其久’如圖1和圖2所_ 2、第3半導體晶片7 J哲利用裝片樹脂16使接合有第 第1半導體晶片"妾著在引線框架 461071
五、發明說明(π) 電極3和引線框 也、封和封裝。這 A 1 入到第1半導體 之裝片襯墊1 8,利用合接線1 9連接第1外部6 架之引線1 7,最後利用密封樹脂2 〇進行密封 時,密封樹脂2 0在樹脂之注入模型時,注 晶片1和第2半導體晶片7及第3半導體晶片9之 =$ -外,樹脂之注入到第1半導體晶片i和第2半導^曰二 半導體晶片9之間隙之進行亦可以在以與封裝之g封 不同之絕緣樹脂16進行密封之前。另外,在第i 二曰曰 片1和第2半導體晶片7及第3半導體晶片9之間隙亦可二= 為未注入有樹脂之狀態。另外’在積層之半導體晶片中, 對於第1半導體晶片’内部電極之位置關係假如電路上 沒有問題時,則面向上或面向下之任何„方约可。 依照上述方式之實施形態時,在第2、第3半導體晶片之 内部電極8、1 〇内設置穿通孔6,對第1和第2、第3之% 半導 體晶片1、7、9進行接著固定,因為利用無電解電鑛用來 電連接第2、苐3半導體晶片之內部電極8、和穿通孔内 壁之第1金屬25(電鍍電極13)與第1半導體晶片之内部電極 4 ’所以可以積層多片之晶片而不會使晶片受損。另外, 因為在穿通孔内壁利用無電解電鍍或蒸著形成可無電解電 鍍之第1金屬2 5 (電.鍍電極1 3 ),所以不使用習知方式之以 悍接塊接合,不需要在晶片之内部電極上預先形成使焊劑 產生擴散之金屬。另外,因為沒有焊接塊之擴散,所以微 細之連接變為容易’可以適於應用在多接_LS I。作為第1 金屬25(電鍍電極13)者例如可以使用Cu、Ni、Au、Pt、Ag 、Sn、Pb、Co 等。
C:\2D.00DE\90_Gl\89122958.ptd 第14頁 461071 五、發明說明(12) 亦5 iU 2笛t導體晶片之内部電極8内之穿通孔6之直徑 ' ;第1半導體晶片1和第2半導辨曰g 7夕鬥隙之 1/2。亦即,在圖2中,日哲0弟2牛導體日日片7之間隙之 穿通孔之直徑,b是第第2半導體晶片之内部電極内之 隙。當^/2時曰片和第2半導體晶片之間 6之前,因為與其他電極//屬(電鍍電極⑸埋沒穿通孔 之電鍍電極13等)接觸,所屬(第2半導體晶片 液。當a Sb/2時,在盥並仙在穿通孔6之内部殘留電鍍 之前,穿通孔被電鍍金屬埋:電=成J之電鑛金屬接觸 殘留電鍍液,可以確實的連接。因此,在穿通孔6内不會 另外,以上所示者是積層第2、 但是亦可以將第2半導體 =曰曰片之情況, 連接有第2半導體晶片 積日雕2 =上之晶片。另外, 外,亦可以構成為電路基板^導肢日日片,除了晶圓之狀態 【元件編號說明】 1 :第1半導體晶片 半導體晶片之保護膜 第1半導體晶片外部電極 第1半導體晶片内部電極 接著劑 穿通孔 第2半導體晶片 第2半導體晶片之内部電極 第3半導體晶片
C:\2D-C0DE\90-0J\89122958 ntd 第15頁 461071
五、發明說明(13) 10 第3半導體晶片 之 内 部 電 極 11 第2半導體晶片 之 氧 化 膜 12 第3半導體晶片 之 氧 化 膜 13 第2半導體晶片 之 電 鍍 電 極 14 第3半導體晶片 之 電 鍍 電 極 15 電鍍電極 16 裝片樹脂 17 引線框架之引 泉 18 引線框架之裝 片襯墊 19 合接線 20 密封樹脂 21 .22 、 29 :晶圓 23 無電解電鍍液 24 無電解電鍍槽 25 電鍍金屬膜 26 抗餘劑 27 餘刻液 28 餘刻槽 30 彈性夾 31 彈性夾之真空孔 32 切片之溝 33 絕緣樹脂 34 氧化膜 C:\2D-CODE\90-01\89122958.pld 第16頁
Claims (1)
- 461071 六、申請專利範圍 1,一種半導體裝置,具僙有:第丨 部電極和内部電極;和第2丰遂辦 日日 八有卜 在上述之第1半導體// = = :部電極; 體晶片、,、和使内部電極互相電連接;其特徵是:+導 f上述之第2半導體晶片之内部電 该穿通孔内壁以與其他電極絕 芽通孔,在 之電極,和以使上述之第!和第2半導日曰:片:内、::電鍍 =為對應之方式’利用接著劑將上述:第2 °極之 固疋在上述第1半導體晶片之外導體曰曰片 部份,上述之第2半導體曰σ電極以外之 卞守脰日日片之内部電極和穿 上述電極與上述之第!半導體晶片之内部電極,土之 成分之連續金屬產生電連接。 >,二由相同 2 ·如申》月專利範園第【項之半導體, 體晶片之内部電極内之穿通 、具中將弟2.半導 導體晶片和第2半導體Λ通 3. 如申明專利範圍第i項之半導體裝置,复 J體晶片同樣構造之第3半導體晶片同樣的積層:二半 第2半導體晶片。 w增在上述之 4. 如申料利範圍第!項之半導體裝置, 導體晶片同樣構造之多個半導體晶片字,、第2半( 第2半導體晶片。 J谓層在上述之、 5. —種半導體裝置之製造方法,其特徵是所人 有:在積層於第1半導體晶片之第2半導體曰 3之工種 内設置穿通孔;在上述之穿通孔内壁和背:形成::】極 她 第19頁 C: \2D-C0DE\90-01 \89122958.ptd 4 6 107 -------- — 六、申請專利範園 利用無電解電铲 — 電鍍之電極;g著在上述之穿通孔内壁形成可無電解 之間成為對應=使上述之第1和第2半導體晶片之内部電極 隙之狀態,^上方式’在對上述之第1半導體晶片具有間 導體晶片之外邱述之第2半導體晶片接著固定在上述第1半 解電鑛使上述之H和/9部電極以外之部份;和利用無電 之上述電極愈 ¥體晶片之内部電極和穿通孔内壁 接。 〇上述之第1半導體晶片之内部電極產生電連 丄6 ·如申清專利範圍第5項之半導體裝置之制1 甘 中將第2半導體a ΰ々如广千¥肽装置之衣造方法,其 為小於第1丰ί: 電極内之穿通孔之直徑設定成 7 Υ ί +蛉體晶片和第2半導體晶片之間隙之1 /2。 .。申請專利範圍第5項之半導體裝置之製造 I 層:Ϊ ί2半:體晶片同樣構造之第3半導體晶片同樣的積 層在上述之第2半導體晶片。 8,如申請專利範圍第5項之半導體裝置之製造方法,其 ::與第2半導體晶片同樣構造之多個半導體晶片同樣: 積層在上述之第2半導體晶片。
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JP31222299A JP4245754B2 (ja) | 1999-11-02 | 1999-11-02 | 半導体装置 |
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JP (1) | JP4245754B2 (zh) |
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US6900549B2 (en) * | 2001-01-17 | 2005-05-31 | Micron Technology, Inc. | Semiconductor assembly without adhesive fillets |
JP2002373957A (ja) * | 2001-06-14 | 2002-12-26 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP4917225B2 (ja) * | 2001-09-28 | 2012-04-18 | ローム株式会社 | 半導体装置 |
JP2003258196A (ja) * | 2002-02-27 | 2003-09-12 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP3972813B2 (ja) * | 2002-12-24 | 2007-09-05 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
KR100497111B1 (ko) | 2003-03-25 | 2005-06-28 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법 |
KR100621617B1 (ko) * | 2003-08-27 | 2006-09-13 | 삼성전자주식회사 | 메모리 모듈 구조 |
JP4580730B2 (ja) * | 2003-11-28 | 2010-11-17 | ルネサスエレクトロニクス株式会社 | オフセット接合型マルチチップ半導体装置 |
US7239020B2 (en) * | 2004-05-06 | 2007-07-03 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Multi-mode integrated circuit structure |
KR100570514B1 (ko) * | 2004-06-18 | 2006-04-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스택 패키지 제조 방법 |
US7202554B1 (en) * | 2004-08-19 | 2007-04-10 | Amkor Technology, Inc. | Semiconductor package and its manufacturing method |
KR100708887B1 (ko) * | 2005-05-27 | 2007-04-17 | 디엔제이 클럽 인코 | 리드 프레임이 포함된 칩 적층 패키지 소자 |
JP4910512B2 (ja) * | 2006-06-30 | 2012-04-04 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
KR100845006B1 (ko) | 2007-03-19 | 2008-07-09 | 삼성전자주식회사 | 적층 칩 패키지 및 그 제조 방법 |
US7977155B2 (en) * | 2007-05-04 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level flip-chip assembly methods |
KR101052867B1 (ko) * | 2008-01-08 | 2011-07-29 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조 방법 |
KR101478247B1 (ko) | 2008-03-12 | 2014-12-31 | 삼성전자주식회사 | 반도체 패키지 및 이를 이용한 멀티 칩 패키지 |
EP2104138A1 (de) | 2008-03-18 | 2009-09-23 | EV Group E. Thallner GmbH | Verfahren zum Bonden von Chips auf Wafer |
JP5489512B2 (ja) * | 2009-04-06 | 2014-05-14 | キヤノン株式会社 | 半導体装置の製造方法 |
JP5748198B2 (ja) * | 2010-12-20 | 2015-07-15 | 株式会社ディスコ | 積層デバイスの製造方法及び積層デバイス |
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KR100214562B1 (ko) * | 1997-03-24 | 1999-08-02 | 구본준 | 적층 반도체 칩 패키지 및 그 제조 방법 |
JP3920399B2 (ja) * | 1997-04-25 | 2007-05-30 | 株式会社東芝 | マルチチップ半導体装置用チップの位置合わせ方法、およびマルチチップ半導体装置の製造方法・製造装置 |
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US6122187A (en) * | 1998-11-23 | 2000-09-19 | Micron Technology, Inc. | Stacked integrated circuits |
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-
2000
- 2000-10-17 US US09/688,816 patent/US6534874B1/en not_active Expired - Lifetime
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KR20010060223A (ko) | 2001-07-06 |
JP2001135776A (ja) | 2001-05-18 |
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