1305116 九、發明說明： 【發明所屬之技術領域】 插斂—種喪埋半導體元件之電路板結構及其製法，尤指-種正合半導體元件及電容元件之電路板結構及其製法。 _【先如技術】 案，現代各式電子產品輕薄短小化之發展趨勢，半導體 業界係將電子元件埋入封裝基板中以因應此一趨勢。例 半導體業界大多數採用將諸如半導體晶片等主動元 ’及諸如電阻、電容、電感等被動轉嵌埋於基板中， =該基板上製作線路增層結構以形成具有鼓埋主、被 =^電路板結構。然’由於前料路增層結構係於具 埋主、被動元件之—側表面進行增層製程，故 單項增層則會有應力不均問題；又或如 不：門題而’則兩側增層層數差距過大亦會有應力 不均問碭，而產生電路板整體結構彎麵 >可靠度及生產良率的等問題。 4導致成扣 |y法因:避種嵌埋半導體元件之電路板結構及 路板結構電::π::路增層時所產生之電 元件之電路板結構板中直接形成電容 【發明内容】 w成爲目4界轉克服之課題。 鑒於上述習知技術之種種缺點，本發 於提供一種嵌埋半導體主要目的在 -金屬板之二相電:板結構及其製法，得於 面之形成乳化金屬層，藉以增加電路 19639 1305116 板結構之抗彎曲剛性強度。 本發明之又一目的在於提供— 電路板結構及其製法，得於電 ^半導體元件之 俾以簡化習知之電路板結構、製法：：中形成電容元件’ 性功能。 θ加電路板結構之電 為達上述及其他目的，本發 件之電路板結構之製法m —種嵌埋半導體元 板係於一金屬板 八、·共—承載板，該承载 屬板之兩表面为別形成有第—及第二氧 二’且於該承載板中形成有至少—貫穿該承載板之第一： 二：亥承載板之第一開口中容置一半導體元件，且於： :半導體元件固定於該第-㈣心第 未貫穿之第二開口以露出部分之金屬板心 於該弟二開口中之金屬板上依序形成—高介電材料及電 『反’藉由該承載板中之金屬板、高介電材料及電極板以 構成一電容元件。 該金屬板係為鋁，並進行氧化製程以形成具有氧化鋁 之第一及第二氧化金屬層。 依上述之製法，本發明復提供一種歲埋半導體元件之 =路板結構，係包括：—承載板，係於—金屬板之兩表面 分別形成有一第一及第二氧化金屬層，且該承载板具有至 少—貫穿該承載板之第一開口，又該第—氧化金屬層具有 至少一第一開口以露出部份之金屬板；至少一半導體元 件，係容置於該承載板之第一開口中；一黏著材料，係填 19639 6 1305116 充於該承载板之第—開口與 以將該半導體元件固定於該承件:間:間隙中’ 高介電材料及電極板，係之第—開口中；以及一 可討及電極板，係形成於該第一氧化 開口中，並與該金屬板構成—電容元件。 《之弟一 有-=結構之進一步實施係為該半導體元件具 —有 〃該主動面相對之非主動面，於該主動面旦 有被數電極塾，且辞主遒躺-^ 八 电u且該丰導體兀件之主動面與該第 屬層同侧，依此結構上述之製法 層、半導體元件之主動面及電容元件之=第一氧化金屬 線路增層結構，且該線路增紗 形成一 s ^ L ^ a^、、°構中具有導電結構以電性 妾^半¥體兀件之電極墊及該電容元件之電極板又 於該第二氧化金屬層及半導體元件之非主動㈣ 構，並形成有至少—⑽導通孔貫穿該承载板以 電性連接該些線路增層結構。 上述製法及結構之另一進一步實施係為該半導體元 籲件具有一主動面及與該主動面相對之非主動面，於該主動 面具有複數電極墊，且該半導體元件之主動面與該第二氧 化金屬層同側，另依此結構，前述之製法復包括於該第一 氧化金屬層、半導體元件之非主動面及電容元件之電極板 表面形成一線路增層結構，且該線路增層結構中具有導電 結構以電性連接至該電容元件之電極板；又於該第二氧化 金屬層及半導體元件之主動面形成另一線路增層結構，且 該線路增層結構中具有導電結構以電性連接至該半導體元 件之電極墊，並形成有至少一電鍍導通孔貫穿該承載板以 19639 7 1305116 電&連接該些線路增層結構。 該線路增層社槿& 線路層"電層、疊置於該介電層上之 路增層結構外夺面β&女、 之蜍電結構，又於該些線 B ^ 卜表面形成有禝數電性連接墊，指於兮始找说 層結構外表面形H連㈣谈於该線路增 以露出咳後技揭t / 該防焊層中具有複數開孔 ^線路增層結構外表面之電性連接墊。 本發明之嵌埋半導體晶片之 製法，係包括：提#__# β板,、.。構之另一實施 ^ χ 承载板，该承載板係於一金屬板之 兩表面分別形成有第H _板之 全屬β由：α/ Α 士 及弟一虱化金屬層；於該第一氧化 I屬層中形成有至少一未貫穿 ^ 屬軛., 禾貝牙之苐二開口以露出部分之金 '形忐一古人+ 弟―開口中之金屬板上依序 .!：成電材料及電極板，藉由該承載板中之金屬板、 尚介電材料及電極板以構成一電 屬板 成$小一I办士 電谷兀件，於該承載板中形 成至夕一貝牙該承載板之第一開. 矛阀口，於該承载板之第一開 中谷置一半導體元件； ^ u ± ^ Α _ 久％項第一軋化金屬層、電極 #板及半導體元件表面形成一介電 ^ ^ ;丨电潛，且使該介電層填充於 -該承載板之弟一開口與該半導體元件之間的間隙中，俾以 將該半導體元件固定於該承載板之第一開口中。 該金屬板係為！呂，並進行氧化製程以形成具有氧化铭 之第一及第二氧化金屬層。 依上述之製法，本發明復提供一種嵌埋半導體元件之 電路板結構，係'包括··-承載板，係於—金屬板之兩表面 分別形成一第一及第二氧化金屬層，且該承載板具有至少 -貫穿該承載板之第-開π，又該第―氧化金屬層具有至 19639 8 1305116 ^、一第二開口以露出部 一 板，係形成於該第—氧化金=:第：=材料及電極 屬板構成一電容元件；一半 並與该金 ::開口中，-介電層，係形成於該戰： pe 使該；1電層填充於該承載板之篦 開口與該半導體元件之間的間隙中，以將該4::: 定於該第一開口中。 體70件固 上述製法及結構之谁--牛-每> 乂么从 古_ + & 。 進纟貝施係為該半導體元件且 有一主動面及與該主動面相 八 有複數電極塾，且該半導體元面’於該主動面具 /干等體7L件之主動面與該第一 :層同側，於該介電層表面形成—線路增層結構，且^ 電有導電結構以電性連接至該半導體元件之 = = r 第二一 F ^㈣成另—線路增層結構，並形成有 ^ 一電鍍導㈣貫㈣承餘以紐連㈣些線 結構。 ^ 杜1古Γ及結構之另—進―步實耗為該半導體元 m動面及與該主動面相對之非絲面，於該主動 面具有複數電極墊，且該半導體元件之主動面與該第二氧 化金制同側，於該介電層表面形成—線路增層結構，且 該線路增層結構中具有導電結構以電性連接至該電容元件 之電極板’復於該第二氧化金屬層及半導體元件之主動面 形成另一線路增層結構，且該線路增層結構中且有導電妗 構以電性連接至該半導體元件之電㈣，並形成有至少二 19639 9 1305116 電錢V通孔貝牙s亥承載板以電性連接該些線路增層結構。 線路層結構係包括有介電層、疊置於該介電層 上之線路層’以及形成於該介電層中之導電結構，復於該 些線路增層結構外表面形成有複數電性連接塾，又於該線 ·=增層結構外表面形成__防烊層，且該防焊層中具有複數 開孔以露出該線路增層結構外表面之電性連接墊。 本發明之嵌埋半導體元件之電路板結構及製法，主要 之金屬板增強該承載板之結構強度，藉以提 中可能產生變形之抗f曲強度。又本發明之承 金屬爲!^屬板之二相對表面分別形成第一及第二氧化 口以露出部分金屬板，金屬層形成第二開 成高介電材料及電_ I開口中之金屬板上依序形 金屬板、介電層及第二1該承载板中直接形成由該 電路板結構金屬板構成之電容元件侧 【實施方式】 式，實施例說明本發明之實施方 瞭解本發明之其他優點與功2明書所揭示之内容輕易地 請參閱第1A至〗F同, 之電路板結構之製@ ’係為本發明之嵌埋半導體元件 如第圖戶ί示首Γ實施例之剖面示意圖。 係於-金屬板IG之 ’提供―承載板卜該承載板1 化金屬層11及帛-Z、經氧化製程以分別形成第一氧 及第…金屬層⑶其中，該金屬板10係 19639 10 1305116 一氧化金屬層11 為铭’並進行氧化製程以形成氧化紹之第 及第二氧化金屬層12。 至少一貫穿 如第1δ圖所示，於該承载板1中形成有 該承载板1之第一開口丨a。 一半圖:示，於該承載板1之第-開…容置 之門的門隙中畲且於該第一開口1&與該半導體元件13 ::::隙中填充黏著材料14以將該半導體元件13固定 及U中。該半導體元件13具有一主動面13a 舍、以主動面相對之非主動面13b，於該主動面ΐ3&且有 複數電㈣131，且該半導體元件η之主動面13a與該第 一氧化金屬層11同側。 一=第1D圖所示，於該第一氧化金屬層n中形成至少 -未貫穿之第二開口 lla以露出部分之金屬板1〇。 如第1E圖所示，於該第二開口 lu中之金屬板】〇上 依序形成一高介電材料151及電極板，藉由該承載板1 攀中之金屬板10、高介電材料151及電極板152以構成一電 容元件15。 如第1F圖所示，於該第一氧化金屬層u、半導體元 件13之主動面13a及電容元件15之電極板152表面形成 線路增層結構16，該線路增層結構1 ό係包括有介電層 161、登置於該介電層上之線路層162，以及形成於該介電 層中之導電結構163，且該導電結構163電性連接至該半 導體疋件13之電極墊131及該電容元件15之電極板152, 並於該線路增層結構外表面形成有複數電性連接墊 11 19639 1305116 二4,又於該線路增層結構16外表面形成— 具有複數開孔170以露出該 16外表面之電性連接墊ι64。 再 :::閱第2圖’於前述製法中，復可同時於該第— .氧化金屬層Η及半導體元件13之主動面&形 層結構16，以及於兮筮-与人m 夕稱μ及於該第一乳化金屬層12及半導 =主動面m形成另一線路增層結構16，，並形成有至 J電鍍導通孔18貫穿該承載板丨電 層結構16，16，。 U連接4些線路增 透過前述製法，本發明提供一種嵌埋半導體元件 路板結構，係包括··-承載板i，係於—金屬板10之兩表 面/刀別形成有-第一氧化金屬層u及第二氧化金屬層 12 ’且該承載板1具有至少-貫穿該承載板1之第一開口 la，又該第-氧化金屬層n具有至少—第二開口 Ha以泰 :料之金屬板10;至少一半導體元件13，係容置於該: ，反1之第-開口 la中；—黏著材料14，係填充於該承 載板】之第—開口 la與該半導體元件13之間的間 以將該半導體元件13固定於該承載板1之第一開口 la 中；以及一高介電材料⑸及電極板152，係形成於該 „層U之第二開口 lla中，並與該金屬板:〇構 成一電谷7L件15，俾於一以金屬板10兩表面形成有第— 氧化金屬層11及第二氧化金屬層12之承載板卜而可提 南電路板結構之強度，以避免後續製程造成彎曲變形的情 況，並於該承載板1中形成有電容元件15以簡化結構。月 19639 12 1305116 依上述之結構，復於該承載板1之第-氧化金屬層 :卜半導體元件13之主動面13a及電容元件15之電極板 ⑸上形成-線路增層結構16，該線路增層結構16係包括 有介電層161、疊置於該介電層上之線路層162，以及形成 =該介電層中之導電結構163，且該導電結構⑹電性連 描ft半^體凡件13之電極塾131及該電容元件15之電 連:墊結構16外表面形成有複數電性 結構Μ外表面之電性連接墊線路增層 -主動^二該第二氧化金屬们2及半導體元件13之非 動面⑽可形成有另—線路增層結構16， 孔Μ貫穿該承載板1〜該些線路增 • 閱第3圖，係為該半導體元件之主動面鱼Μ- '元株二： 該第—氧化金屬層Η、半導 , Ρ主動面Ub及電容元件15之電極板152表 面形成-線路增層結構16，且該線路增層 ^ 導電結構163電性連接5兮念—- 中八有 及於兮第一气妾至该電容疋件15之電極板152，以 、以弟一虱化金屬層12及半導體元件U之主 :成另 '線路增層結構16，， ：：： ⑶，並形成有至少-電/導^件13之電極塾 ^電鍍導通孔18 性連接該些線路增層社槿貝牙及承載板1以電 盾、、，。構16，16，且於該線路增層結構 19639 13 1305116 路;^ L表㈣麵複數㈣接墊i64，164,，又於該線 ::=广16,外表面形成-防焊層1…該防 構！6 16，外^有複數開孔m，17G，以露出該線路增層結 ^外表面之電性連接墊164,164,。 之電：：:】I至4〇圖’係為本發明之嵌埋半導體元件 卢 、、'°之跛法的另一實施例，與前一實施例之不同 ^於該半導體元件細介電制定於該承餘之第-開 如第4A圖所示，提供一承載板，該承載板係於一金 屬板1〇之兩表面分別形成有第-氧化金屬層11及第1 :金屬”2,於該第一氧化金屬層„中形成有至；:； 貝穿之第二開口 lla以露出部分之金屬板10。 如第4B圖所示，於該第一氧化金屬層u之第二開口 ua中之金屬板10上依序形成一高介電材料⑸及電極板 152 ’藉由該承載板1中之金屬板1〇、高介電材料151及 電極板152以構成一電容元件！ 5。 如第4C圖所示，於該承載板！中形成至少—貫穿之 第一開口 la，並於該第一開口 1&中容置有—半導體元件 ⑶該半導體元件13具有—主動面13a及與該主動面相對 之非主動面13b，於該主動面13a具有複數電極墊13卜且 忒半導體το件13之主動面13a與該第一氧化金屬犀u 側。 θ 如第4D圖所示，於該第一氧化金屬層j丨、電極板m 及半導體元件13之主動面13a上形成一介電層19，且使 19639 14 1305116 充於該承載板1之第 兀仵3之間的間隙中，俾 导 承載们之第-開Dlat。 體心化固定於該 表面^Γ5Α圖’依上述之製法，復可於該介電層Η .咐二:、Γ:增層結構16,且該線路增層結構μ ㈣确MU之電極塾 屬#]… 52;同時於該第二氧化金1305116 IX. Description of the invention: [Technical field to which the invention pertains] A circuit board structure and a method for manufacturing the same, particularly a circuit board structure of a semiconductor element and a capacitor element, and a method of manufacturing the same. _ [First as technology], the trend of modern light-weight and short-term electronic products, the semiconductor industry embedded electronic components in the package substrate to meet this trend. For example, most of the semiconductor industry adopts passive conversion of active elements such as semiconductor wafers and such as resistors, capacitors, inductors, etc. into the substrate, and the circuit is formed on the substrate to form a circuit-embedded structure to form a circuit with a buried main body. Board structure. However, because the front-growth layer is structured on the side surface with the buried main and passive components, the single layer will have uneven stress; or if not: the door will be If the gap between the number of layers is too large, there will be problems such as uneven stress, resulting in the overall curved surface of the board, reliability, and production yield. 4 leads to the buckle|y method: avoiding the circuit board structure and the circuit board structure embedded in the semiconductor component:: π:: directly forming a capacitor in the circuit board structural plate of the electrical component generated when the layer is added. 】 w became the subject of the 4th boundary. In view of the above various shortcomings of the prior art, the present invention provides a two-phase electric: plate structure and a manufacturing method thereof for the purpose of embedding a semiconductor, thereby forming an emulsified metal layer on the surface, thereby increasing the circuit structure of the circuit 19639 1305116. Resistance to bending rigidity. It is still another object of the present invention to provide a circuit board structure and a method of fabricating the same, which are used to simplify the conventional circuit board structure and method: forming a capacitive element. The electric circuit of the θ plus circuit board structure achieves the above and other purposes, and the method for manufacturing the circuit board structure of the present invention is a type of embedded semiconductor element board which is attached to a metal plate VIII, a common carrier plate, and the carrier plate The surface is formed with the first and second oxygen bis and is formed in the carrier plate at least - the first through the carrier plate: the first opening of the second carrier plate houses a semiconductor component, and is: a semiconductor element is fixed to the second opening of the first (fourth) core, and the exposed metal plate is sequentially formed on the metal plate in the second opening - a high dielectric material and an electric "reverse" The metal plate, the high dielectric material and the electrode plate in the carrier plate form a capacitive element. The metal sheet is aluminum and is subjected to an oxidation process to form first and second oxidized metal layers having alumina. According to the above method, the present invention provides a circuit board structure for a semiconductor device, comprising: a carrier plate, wherein a first and a second metal oxide layer are respectively formed on both surfaces of the metal plate, and the carrier The plate has at least one first opening extending through the carrier plate, and the first metal oxide layer has at least one first opening to expose a portion of the metal plate; at least one semiconductor component is disposed in the first opening of the carrier plate Medium; an adhesive material, filled with 19639 6 1305116 to fill the first opening of the carrier plate and to fix the semiconductor component to the carrier: between: gaps 'high dielectric material and electrode plate, the first opening And an electrode plate is formed in the first oxidation opening and forms a capacitance element with the metal plate. "The younger one has a -= structure further implementation of the semiconductor component - there is a non-active surface of the active surface, the active surface has a number of electrodes, and the resignation is lying - ^ 八电 u And the active surface of the abundance conductor element is on the same side as the first layer, according to the structure of the above-mentioned method, the active surface of the semiconductor element and the capacitor element = first oxide metal line build-up structure, and the line is formed An electrode pad having an electrically conductive structure and having an electrically conductive structure in the structure of the s ^ L ^ a ^ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , And forming at least—(10) via holes through the carrier plate to electrically connect the line build-up structures. The further implementation of the above method and structure is that the semiconductor element has an active surface and an inactive surface opposite to the active surface, the active surface has a plurality of electrode pads, and the active surface of the semiconductor component and the first The metal oxide layer is on the same side, and according to the structure, the method further comprises forming a line build-up structure on the first metal oxide layer, the inactive surface of the semiconductor element, and the surface of the electrode plate of the capacitor element, and the line is added The structure has an electrically conductive structure electrically connected to the electrode plate of the capacitive element; and the second metal oxide layer and the active surface of the semiconductor element form another line build-up structure, and the line build-up structure has a conductive structure The electrode pad of the semiconductor component is electrically connected to the electrode pad, and at least one plated via hole is formed through the carrier plate to electrically connect the line buildup structure with 19639 7 1305116. The circuit is formed on the surface layer of the circuit layer and the electric layer, and the circuit layer layered on the dielectric layer, and the electric structure of the female surface is formed on the surface of the line B ^ Bu There are a number of electrical connection pads, which refer to the outer surface shape of the layer structure. (4) Talk about the increase of the line to expose the cough technique. / The solder mask has a plurality of openings and lines. Electrical connection pads on the surface. The method for fabricating the embedded semiconductor wafer of the present invention comprises: a #__#β plate, . Another implementation of the structure is: 承载 a carrier plate, the carrier plate is formed on both surfaces of a metal plate, respectively, and the entire genus of the H-th plate is formed by: α/ Α士和弟一虱化金属层; At least one non-penetrating yoke is formed in the oxidized I genus layer, and the 开口 开口 开口 以 以 以 以 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 露出 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾 禾And the electrode plate, wherein the metal plate, the dielectric material and the electrode plate in the carrier plate form an electric plate into a small-sized one-segment electric grid element, and the outer plate is formed in the carrier plate. a first open. spear valve port of the carrier plate, a semiconductor component is disposed in the first open valley of the carrier plate; ^ u ± ^ Α _ long % of the first rolled metal layer, the electrode # plate and the surface of the semiconductor component a dielectric layer, and the dielectric layer is filled in a gap between the opening of the carrier plate and the semiconductor element, to fix the semiconductor component to the first of the carrier board In the opening. The metal plate is! Lv, and an oxidation process is performed to form first and second oxidized metal layers having oxidation. According to the above method, the present invention provides a circuit board structure in which a semiconductor component is embedded, which is a 'including ·--bearing plate, and a first and a second oxidized metal layer are respectively formed on both surfaces of the metal plate, and the The carrier plate has at least - a first opening π extending through the carrier plate, and the first oxidized metal layer has a thickness of 19639 8 1305116 ^, a second opening to expose a plate, formed in the first oxidation gold =: : = material and electrode plate constitute a capacitive element; half and the gold:: opening, - dielectric layer, formed in the battle: pe to make; 1 electrical layer filled in the opening of the carrier plate and the In the gap between the semiconductor elements, the 4::: is defined in the first opening. 70 pieces of the body Who is the above-mentioned method and structure - cow - every > 乂 from ancient _ + & The 纟 施 为 is the semiconductor element and has an active surface and a plurality of electrode 与 with the active surface, and the semiconductor element surface 'the active surface of the active mask/dry body 7L is the same as the first layer a side, forming a line build-up structure on the surface of the dielectric layer, and electrically conducting a conductive structure to electrically connect to the semiconductor element == r second one F ^ (four) into another line build structure, and formed ^ An electroplating guide (four) through (four) with a balance of New Zealand (four) some line structure. ^ Du 1 Γ Γ and the structure of the other - step is actually the semiconductor element m moving surface and the non-filament surface opposite the active surface, the active surface has a plurality of electrode pads, and the active surface of the semiconductor component and The second side of the second gold oxide is formed on the surface of the dielectric layer to form a line build-up structure, and the line build-up structure has a conductive structure electrically connected to the electrode plate of the capacitor element to repeat the second oxidation The metal layer and the active surface of the semiconductor element form another line build-up structure, and the line build-up structure has a conductive structure electrically connected to the semiconductor element (4), and is formed with at least two 19639 9 1305116 The V through hole bei s hai carrier plate electrically connects the line buildup structures. The circuit layer structure includes a dielectric layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, and a plurality of electrical connections are formed on the outer surface of the circuit-added structure. Further, a __an anti-mite layer is formed on the outer surface of the line-adding layer structure, and the solder resist layer has a plurality of openings therein to expose the electrical connection pads of the outer surface of the line build-up structure. In the circuit board structure and the manufacturing method of the embedded semiconductor device of the present invention, the main metal plate enhances the structural strength of the carrier plate, thereby improving the anti-b-bending strength which may cause deformation. Further, the metal bearing body of the present invention forms first and second oxidation ports respectively on the opposite surfaces of the second plate to expose a part of the metal plate, and the metal layer forms a second open high dielectric material and a metal plate in the electric opening The capacitor element side formed by the metal plate of the circuit board structure is directly formed in the metal plate, the dielectric layer, and the second carrier. The embodiment of the present invention explains the other aspects of the present invention. Advantages and advantages of the work disclosed in the book 2, please refer to the 1A to 〗 〖F, the circuit board structure of the @ ' is the embedded semiconductor component of the present invention, such as the figure of the first embodiment schematic diagram. Attached to the 'metal plate IG' to provide a carrier plate, the carrier plate 1 metal layer 11 and 帛-Z, through an oxidation process to form a first oxygen and a ... metal layer (3), respectively, the metal plate 10 is 19639 10 1305116 The metal oxide layer 11 is etched and subjected to an oxidation process to form a second and second oxidized metal layer 12. At least one through is formed as shown in the first δ diagram, and the first opening 丨a of the carrier plate 1 is formed in the carrier plate 1. Half of the figure: in the gate gap of the first opening of the carrier board 1 and the adhesive material 14 is filled in the first opening 1& and the semiconductor element 13 :::: The semiconductor element 13 is fixed and U. The semiconductor device 13 has an active surface 13a opposite to the active surface 13b, the active surface ΐ3& and a plurality of electric (four) 131, and the active surface 13a of the semiconductor element η and the first oxidized metal layer 11 The same side. As shown in Fig. 1D, at least a second opening 11a which is not penetrated is formed in the first metal oxide layer n to expose a portion of the metal plate 1''. As shown in FIG. 1E, a high dielectric material 151 and an electrode plate are sequentially formed on the metal plate in the second opening lu, and the metal plate 10 and the high dielectric material are climbed by the carrier plate 1. 151 and electrode plate 152 to form a capacitive element 15. As shown in FIG. 1F, a line build-up structure 16 is formed on the surface of the first metal oxide layer u, the active surface 13a of the semiconductor element 13, and the electrode plate 152 of the capacitor element 15. The line build-up structure 1 includes a dielectric layer An electrical layer 161, a circuit layer 162 disposed on the dielectric layer, and a conductive structure 163 formed in the dielectric layer, and the conductive structure 163 is electrically connected to the electrode pad 131 of the semiconductor device 13 and the An electrode plate 152 of the capacitor element 15 is formed with a plurality of electrical connection pads 11 19639 1305116 2 on the outer surface of the line build-up structure, and is formed on the outer surface of the line build-up structure 16 - having a plurality of openings 170 to expose the The electrical connection pad of the outer surface of 16 is ι64. Re::: see Fig. 2' in the above-mentioned manufacturing method, the same can be applied to the first - the oxidized metal layer and the active surface & layer structure 16 of the semiconductor element 13, and the 兮筮-and the person s μ and the first emulsified metal layer 12 and the semiconducting = active surface m form another line build-up structure 16, and the J-plated vias 18 are formed through the carrier 丨 electrical layer structures 16, 16. U is connected to the four lines to increase the transmission through the foregoing method. The present invention provides a buried semiconductor device board structure, which comprises a carrier plate i, which is formed on both surfaces of the metal plate 10 and is formed with a first metal oxide metal. a layer u and a second metal oxide layer 12 ′ and the carrier plate 1 has at least a first opening 1a extending through the carrier plate 1 , and the first oxidized metal layer n has at least — a second opening Ha a plate 10; at least one semiconductor component 13 is disposed in the first opening - 1a of the reverse; - an adhesive material 14 is filled between the first opening - 1a of the carrier and the semiconductor component 13 The semiconductor element 13 is fixed in the first opening 1a of the carrier board 1; and a high dielectric material (5) and an electrode plate 152 are formed in the second opening 11a of the layer U, and the metal The plate: 〇 constitutes an electric valley 7L member 15 , and the strength of the south circuit board structure is formed by forming a carrier plate of the first oxidized metal layer 11 and the second oxidized metal layer 12 on both surfaces of the metal plate 10 Avoiding the bending deformation caused by the subsequent process, and forming in the carrier board 1 The capacitor element 15 has a simplified structure. According to the above structure, the first metal oxide layer of the carrier board 1 is formed on the active surface 13a of the semiconductor element 13 and the electrode plate (5) of the capacitor element 15 to form a line increase. The layer structure 16, the line build-up structure 16 includes a dielectric layer 161, a wiring layer 162 stacked on the dielectric layer, and a conductive structure 163 formed in the dielectric layer, and the conductive structure (6) is electrically The electrical connection between the electrode 塾131 and the capacitive element 15 of the splicing structure 135: the outer surface of the pad structure 16 is formed with a plurality of electrical structures 电 the outer surface of the electrical connection pad line layer-active ^ two The second oxidized metal 2 and the non-moving surface (10) of the semiconductor element 13 may be formed with a further wiring layer-increasing structure 16 through which the apertures extend through the carrier board 1 to 3, which are the semiconductor components. Active surface fishing rod - 'Yuanzhu 2: the first - oxidized metal layer Η, semi-conductive, Ρ active surface Ub and the surface of the electrode plate 152 of the capacitive element 15 form a line build-up structure 16, and the line build-up layer ^ conductive structure 163 electrical connection 5 mourning --- Zhong Ba and Yu 兮 first gas to the electricity The electrode plate 152 of the capacitor member 15 is formed by the metal layer 12 and the semiconductor element U: into another 'line-addition structure 16,, ::: (3), and is formed with at least - electricity / conduction ^ The electrode of the piece 13 is electroplated and the through hole 18 is connected to the line to increase the layer of the shellfish and the carrier plate 1 to the electric shield, and the structure 16 and 16, and the layered structure of the line is 19639 13 1305116; L table (four) face plural (four) pads i64, 164, and in the line:: = wide 16, the outer surface is formed - solder resist layer 1 ... the anti-structure! 6 16, outside ^ have a plurality of openings m, 17G, The electrical connection pads 164, 164 of the outer surface of the line build-up junction are exposed. The following is another embodiment of the embedded semiconductor component of the present invention, which is different from the previous embodiment, and is finely dielectric to the semiconductor device. As shown in FIG. 4A, the carrier is provided with a carrier plate which is formed with a first-oxidized metal layer 11 and a first metal layer 2 on both surfaces of a metal plate 1 Forming a second opening 11a in the first oxidized metal layer to expose a portion of the metal plate 10. As shown in FIG. 4B, a high dielectric material (5) and an electrode plate 152' are sequentially formed on the metal plate 10 in the second opening ua of the first metal oxide layer u by the metal plate in the carrier plate 1. 1 〇, high dielectric material 151 and electrode plate 152 to form a capacitive element! 5. As shown in Figure 4C, on the carrier board! Forming at least a first opening 1a therethrough, and accommodating the semiconductor element (3) in the first opening 1& the semiconductor element 13 has an active surface 13a and an inactive surface 13b opposite to the active surface The active surface 13a has a plurality of electrode pads 13 and an active surface 13a of the semiconductor τ member 13 and the first oxidized metal rhinocerum side. As shown in FIG. 4D, a dielectric layer 19 is formed on the first metal oxide layer j, the electrode plate m, and the active surface 13a of the semiconductor element 13, and the 19639 14 1305116 is charged to the carrier board 1 In the gap between 兀仵3, the 承载 guide carries the first-open Dlat. The body is fixed on the surface ^ Γ 5 Α ' ' according to the above method, can be applied to the dielectric layer 咐 : : Γ 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 增 MU MU MU MU #]... 52; at the same time as the second gold oxide
Si:，半導體元件13之非主動面㈣成另一:路： Γ以成有至少—電鐘導通孔18貫穿該承· 处構1 =卜=些線路增層結構16，16,，且於該線路增層 、、、。構，16外表面形成有複數電性連接墊164 164,， 該線路增層結構16，16,外表面形成-防焊層η 17,，且兮 二 中具有複數開孔17G，17G，以露^ 、（構16，16外表面之電性連接墊164，164，。 請參閱第5B圖，係為該半導體元件13之主動面⑸ 春與該第二氧化金屬層12同側之實施例；於該介電層⑺表 面形成線路增層結構16，且該線路增層結構〗6中且 導電結構163電性連接至該電容^件15之電極板152、，而 於該第二氧化金屬層12及半導體元件13之主動面…形 成另一線路增層結構16，，且該線路增層結構16，中具有導 電結構163,電性連接至該半導體元件13之電極塾⑶，並 形成有至少-電鍍導通孔18貫穿該承載板1以電性連接該 些線路增層結構16,16，，且於該線路增層結構l6，i6，外表 面形成有複數電性連接墊164，164，，又於該線路增層結構 15 19639 1305116 i6、16’外表面形成一防桿層17，17，，且該防焊層叩7,中 具有複數開孔17〇，170,以露出該線路增層結構16，16，外表 面之電性連接墊164，164,。 此外，該等電性連接墊164，164，上可植設有導電元件 ·(圖式中未表示），藉由該導電元件以與外部電子元件設備 電性連接。 依上述之製法，本發明復提供一種嵌埋半導體元件之 #電路板結構，係包括：一承載板卜係於一金屬板1〇之兩 表面分別形成一第-氧化金屬層n及第二氧化金屬層 12’且該承載板！具有至少一貫穿之第一開口 又該第 一氧化金屬層η具有至少一第二開口 Ua以露出部份之金 -屬板1〇; —高介電材料151及電極板152，係形成於該第 -二氧化金屬層1之第二開σ11〇,並與該金屬板1〇構 成二電容元件15; —半導體元件13，係容置於該承載板1 =第一開口 la中；一介電層19，係形成於該承載板丨、電 籲容元件15及半導體元件13上，且使該介電層19填充於該 承載板1之第一開口 la與該半導體元件13之間的間隙^ 中，以將該半導體元件13固定於該第一開口 } a中。 復請參閱第5A圖，該介電層19表面具有一線路增層 結構16，且該線路增層結構16中具有導電結構163以曰電曰 性連接至該半導體元件13之電極墊131及該電容元件} 5 之電極板152;又於該第二氧化金屬層12及半導體元件η 之非主動面13b具另一線路增層結構16,，並具有至少一 電鍍導通孔18貫穿該承載板1以電性連接該些線路增層結 19639 16 1305116 構，且於該線路增層結構16，16，外表面具有複數電 性連接塾164，164,，又於該線路增層結構i6，i6，外表面且 一防焊層17,17’，且該防焊層I? 17，士曰各 八 卞θ !7，17中具有複數開孔 華，以露出該線路增層結構16，16，外 •墊164,164,。 电Γ玍連接 請參閱第5B圖，該介雷s 1Π 士 - ，丨電層19表面具一線路增層έ士槿 16,且該線路增層結構16中 曰構 、方V %結構163電性遠接5 該電容元件15之電極板152，又 連接至 半導體元件u之主動…二12及 Ί 線路增層結構16，，Η 該線路增層結構16,中具有導電結構⑹ 導體元件U之電極墊131 連接至斜 孙办分$潘』， ι八令主）一電鍍導通孔18 貝牙該承她1以電性連接該些線路增層結構16，16，，且 於該線路增層結構16，16，外# 且 卜表面具有稷數電性連接墊 164、164，又於該線路增層 展17 17， 日層、·、。構16，16,外表面具有一防焊 :二，且該防焊，〗7，17,中具有複數開孔170，170,以 •路出該線路增層結構16，16，外表 164，164,。 文饮艾 相較於習知技術，士 & αη , ,.^ .. '月之甘入埋半導體元件之電路板 結構及製法，主要係由承 扳 度，藉以提供後續製程有^ 至屬板1〇提高結構強 承載板中，該金屬板10:之抗f曲強度。又本發明之 氧化金屬層η,12，而對表面分別形成第—及第二 可於该第一或第二氧化金屬屉丨丨 二開口以露出部分金屬㈣，以於該第：開口中 板上依序形成高介電材料⑸及電極板】52，俾可 19639 17 1305116 於該承載板1中直接形成由該金屬板10、高介電材料151 及電極板152構成之電容元件15，因而可克服習知採用陶 瓷基板作爲承載板所引起的種種缺失。 上述實施例僅為例示性說明本發明之原理及其功 •效，而非用於限制本發明。任何熟習此項技藝之人士均可 在=違背本發明之精神及範疇下，對上述實施例進行修飾 與變化。因此，本發明之權利保護範圍，應如後 專利範圍所列。 甲。月 【圖式簡單說明】 元件之電路板 第1Α至1F圖係為本發明之嵌埋半導體 結構之製法之第一實施例之剖面示意圖； 元件之電路板結構另 元件之電路板結構又 弟2圖係為本發明之傲埋半導體 一實施例示意圖； 弟3圖係為本發明之嵌埋半導體 一實施例示意圖； 第4 A至4D圖係為本發明之嵌埋半 板結構之製法另一實施例之剖面示意圖. 之電路 —第5A圖係為本發明之嵌埋半導體元件 设一實施剖面示意圖；以及 板結構 第5B圖係為本發明之嵌埋半導體元件 再一實施剖面示意圖。 電路板結構 【主要元件符號說明】 1 承載板 la 第一開口 19639 18 1305116 . · 10 金屬板 11 第一氧化金屬層 11a 第二開口 12 第二氧化金屬層 13 半導體元件 13a 主動面 13b 非主動面 131 電極墊 _ 14 黏著材料 15 電容元件 151 南介電材料 152 電極板 • 16、 165 線路增層結構 161 、19 介電層 162 線路層 • 163 > 163? 導電結構 164 、164’ 電性連接墊 17、 175 防焊層 170 、17(T 開孔 18 電鍍導通孔 19 19639Si: the inactive surface (four) of the semiconductor element 13 is formed into another: the path: Γ has at least the electric clock via 18 penetrates the support structure 1 = 卜 = some of the line buildup structures 16, 16, and The line is layered, , and . The outer surface of the structure 16 is formed with a plurality of electrical connection pads 164 164, the line build-up structures 16, 16 having an outer surface forming a solder resist layer η 17, and having a plurality of openings 17G, 17G in the second layer to expose ^, (the structure of the outer surface of the 16, 16 electrical connection pads 164, 164, see Figure 5B, is the embodiment of the semiconductor element 13 active surface (5) spring and the second metal oxide layer 12 on the same side; A circuit build-up structure 16 is formed on the surface of the dielectric layer (7), and the conductive build-up structure 163 is electrically connected to the electrode plate 152 of the capacitor 15 and to the second oxide metal layer. 12 and the active surface of the semiconductor component 13 form another line build-up structure 16, and the circuit build-up structure 16 has a conductive structure 163 electrically connected to the electrode (3) of the semiconductor component 13 and formed at least The electroplating vias 18 are electrically connected to the line build-up structures 16 , 16 , and the plurality of electrical connection pads 164 , 164 are formed on the outer surface of the line build-up structure 16 , i6 , And forming an anti-bar layer 1 on the outer surface of the line build-up structure 15 19639 1305116 i6, 16' 7,17, and the solder mask layer 7 has a plurality of openings 17〇, 170 therein to expose the line build-up structures 16, 16 and the electrical connection pads 164, 164 of the outer surface. The electrical connection pads 164, 164 can be provided with a conductive element (not shown), and the conductive element is electrically connected to the external electronic component device. According to the above method, the present invention provides an embedded The circuit board structure of the buried semiconductor component includes: a carrier plate is formed on a surface of a metal plate 1 to form a first oxidized metal layer n and a second oxidized metal layer 12 ′, respectively, and the carrier plate has at least a first opening through which the first oxidized metal layer η has at least one second opening Ua to expose a portion of the gold-plate 1 〇; a high dielectric material 151 and an electrode plate 152 formed on the first The second opening of the metal oxide layer 1 is σ11〇, and forms a two-capacitor element 15 with the metal plate 1〇; the semiconductor element 13 is placed in the carrier plate 1 = the first opening 1a; a dielectric layer 19 Formed on the carrier board, the electrical component 15 and the semiconductor component 13, and The layer 19 is filled in the gap between the first opening 1a of the carrier board 1 and the semiconductor element 13 to fix the semiconductor component 13 in the first opening}a. Please refer to FIG. 5A, The electric layer 19 has a line build-up structure 16 on the surface thereof, and the line build-up structure 16 has a conductive structure 163 electrically connected to the electrode pad 131 of the semiconductor element 13 and the electrode plate 152 of the capacitor element 5; Further, the second metal oxide layer 12 and the inactive surface 13b of the semiconductor device η have another line build-up structure 16 and have at least one plated via 18 extending through the carrier plate 1 to electrically connect the lines. a junction 19639 16 1305116, and on the line build-up structure 16, 16, the outer surface has a plurality of electrical connections 塾164, 164, and on the line build-up structure i6, i6, the outer surface and a solder resist layer 17, 17', and the solder resist layer I? 17, gentry each 卞 θ ! 7, 17 has a plurality of openings, to expose the line build-up structure 16, 16, outer pads 164, 164,. For the connection of the electric raft, please refer to Fig. 5B. The sigma s 1 - 丨 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The electrode plate 152 of the capacitive element 15 is further connected to the active component of the semiconductor element u, the second 12 and the 增 line build-up structure 16, Η the line build-up structure 16, having a conductive structure (6) the conductor element U The electrode pad 131 is connected to the oblique sun branch (pan), ι八令主), an electroplated via 18, the beard is electrically connected to the line build-up structures 16, 16, and is layered on the line The structures 16, 16, the outer # and the surface have a plurality of electrical connection pads 164, 164, and the layer is also layered 17, 17 day, .... Structures 16, 16, the outer surface has a solder mask: two, and the solder resist, 7, 17, has a plurality of openings 170, 170, to the way out of the line build-up structure 16, 16, appearance 164, 164 ,. Compared with the conventional technology, the literary drink Ai is a circuit board structure and a manufacturing method for the embedded semiconductor components of the month, mainly by the bearing degree, so as to provide a follow-up process. The plate 1〇 increases the tensile strength of the metal plate 10 in the structurally strong carrier plate. Further, the oxidized metal layers η, 12 of the present invention are formed on the surface, respectively, and the second and second openings may be formed in the first or second oxidized metal trays to expose a portion of the metal (4) for the first: open middle plate A high dielectric material (5) and an electrode plate 52 are sequentially formed, and a capacitor element 15 composed of the metal plate 10, the high dielectric material 151, and the electrode plate 152 is directly formed in the carrier plate 1. It is possible to overcome the various defects caused by the use of a ceramic substrate as a carrier plate. The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent scope. A. [Simplified illustration of the drawing] The circuit board of the component is a cross-sectional view of the first embodiment of the method for fabricating the embedded semiconductor structure of the present invention; the circuit board structure of the component and the circuit board structure of the other component are 2 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic view showing an embodiment of an embedded semiconductor of the present invention; FIG. 4A to FIG. 4D are diagrams showing another embodiment of the embedded half-plate structure of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5A is a cross-sectional view showing an embodiment of an embedded semiconductor device of the present invention; and FIG. 5B is a cross-sectional view showing another embodiment of the embedded semiconductor device of the present invention. Circuit board structure [Main component symbol description] 1 Carrier board la First opening 19639 18 1305116 . 10 Metal plate 11 First oxide metal layer 11a Second opening 12 Second oxide metal layer 13 Semiconductor element 13a Active surface 13b Inactive surface 131 electrode pad _ 14 adhesive material 15 capacitive element 151 south dielectric material 152 electrode plate • 16, 165 line build-up structure 161, 19 dielectric layer 162 circuit layer • 163 > 163? conductive structure 164, 164' electrical connection Pad 17, 175 solder mask 170, 17 (T opening 18 plating via 19 19639