TW454283B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW454283B
TW454283B TW089109587A TW89109587A TW454283B TW 454283 B TW454283 B TW 454283B TW 089109587 A TW089109587 A TW 089109587A TW 89109587 A TW89109587 A TW 89109587A TW 454283 B TW454283 B TW 454283B
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Taiwan
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mentioned
connection
frequency
electrical
patent application
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TW089109587A
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English (en)
Inventor
Shinji Hara
Hiroyuki Asano
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Sharp Kk
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Publication of TW454283B publication Critical patent/TW454283B/zh

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Description

五、發明說明（ϊ) 士政 發明之領域
本發明係關於一種可良好铪姓A 帶動作的高頻半導體B M L W ，特別是在千兆赫頻 手導體θ日片的兩頻特性的半導體裝置。 發明之背景 近幾年隨著PHS(個人手持式電^ =式電話)等移動體通信 於材科的電晶體開發進展，開發 =次坤化鎵用 放大器或混頻器、低雜訊放大 電晶體的功率 微波積體電路）。 積集度间的MMIC(單片 f處理這些南頻頻帶的積體電路 寄生電感，有時會因上述寄生電 視在配線上的 別是千兆赫（GHz)級體電路特性，特 例如將包含高頻電二域= 基板上時，為了將上述體或電路 感成分影響變成非常大，只要不減低===有的電 會使上述半導體晶片具有的本路能^成分’就 性）惡化。 丨祐〈特別是高頻特 即，作為來自上述半導體晶片的 分雖然因利用連接於外部的負載電路；：電感ί 2特別是接地的接合線電感成分不能取ί;:;;影ϊ 起作用作為反饋電路。藉此，因上 =種整合，會 片内的放大電路择器牲刀而半導體晶 電路增益特別是在南頻頻帶減低，產生特性惡 第6頁 4 5 4¾ 8 3 五、發明說明（2) 化。 曰因此’例如封裝以珅化鎵（GaAs)等構成的高頻用半導體 曰曰片時’使半導體晶片内的接地線如何以小的電感成分連 接於封裝體或電路基板這種外部接地線或接地面，成為大 的問題。 以往為了減低這些電感成分，主要採取兩個方法。一個 方法是盡量縮短接合線長度以減低電感成分。 "作為此代表例，可舉下述封裝··記載於Cindy 613卜的 LDMOS Devices Provide High Power for Digital PCS"
Applied Microwave & Wireless pp.84-88, October (1988) 〇 f =封裝，特別是為了使接地用的接合線長度成為最短 主道抽體晶片設於接地電極上，並且各接合線對於高頻用 一邊垂直且互相平行配置。模式地顯示此封裝 若對於這種封裝更詳細說明，則如圖5所示，在封裝 f i Γ°的接地電極81和接近該接地電極81設置封 電極(輸入端子用引線框架)85及封裝_ 面’在設於上述接地電極81上的半導體晶片71上 地端子84及半導體晶片71的各輸入端ί +導體日日片71的各輸入端子76。 =且，設置分別電氣連接半導體晶片71的各 、84和封裝體8。的各電極85，，之間的各接：=76 4 5 够 8 3 'ο-
83 '82 〇 此外，作為縮短接合線長度的另外方法，例如如特開平 2- 1 070 0 1號公報（公開日1 990年4月19日）或特開平 3- 262302號公報（公開日1991年11月22日）所揭示，已知的 是比周邊降低在晶片的小晶片接合（die bond)位置，使曰 片上的焊接區和基板的圖案面高度成為相同，縮短為了 $ 接上述兩者間的接合線長度，藉此小地設定取決於接合 的電感成分。 ^ 再者，就縮短接合線長度這種配線長度的方法而言’也 知道下述方法.在南頻用半導體晶片開一極小的孔，將晶 片内的接地線通過此孔和半導體晶片背面的外部接地面2 ( 接。 作為和縮短這些接合線的方法另外減低彼此電感成分的 方法，也知道下述方法：將高周波用半導體晶片裝載於封 裝體，利用金屬線接合進行電氣連接時，從半導體晶片内 的接地線盡量引出多條接合線，將此接合線連接於引線框 架或晶片正下面的塊（slug)。這是多數互相並排連接具有 電感成分的接合線，以使全體電感成分減低。 且說咼頻用半導體晶片積集度變大，並且電路小型化及 低成本化的要求’所以以往成為作為個別高頻用半導體晶 f ’分別封裝於封裝體的結構的電路已被單晶片作為一個（ 面頻用半導體晶片。例如模式地顯示使被丨c化的高頻用功 率放大器（以下稱為放大電路）21及放大電路22單晶化之例 的為圖6。如圖6所示’高頻用半導體晶片23由放大電路21
及放大電路22構成（在圖6中只圖示輸出級的雙極電晶體） 放大電路21的輸出用焊接區2γ、放大電路21的接地用焊 接區26及放大電路21的輸入用焊接區以設於放大電路21。 ^述輸出用焊接區27例如連接於高頻用雙極電晶體的集極 鈿子上述的接地用焊接區26例如連接於高頻用雙極電晶 體的特極端子。 另一方面，同樣地放大電路22的輸出用焊接區24、放大 電^2 2的接地用焊接區25及放大電路“的輸入用焊接區μ 也設於放大電路22。上述輸出用焊接區24例如連接於高 用雙極電晶體的集極端子。上述的接地用焊接區25例如（ 接於高頻用雙極電晶體的特極端子。 而且，分別接收來自各放大電路21、22的輸出的封裝體 1之各輪出端子32、33、到各放大電路21、22的封裴體31 ^ =輸入端子3 5、37，並且為裝載高頻用半導體晶片23的 匡/、’成為接地面的接地電極3〇設於作為電路基板的封 體3 1。 衣 而且’為了電氣連接半導體晶片23和封裝體3〗之間，八 別6又置和半導體晶片23上的各焊接區34、36、27、24、& 带=及封裝體31之各端子（引線框架）35、37、32、33、 f連接的各接合線50、41、38、39、28、29。特別是各（ 接口線28、29為各放大電路21、22的接地用接合線。而且 如對於半導體晶片2 3 一邊垂直且互相平行般地分 各接合線28、29。
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Z 五、發明說明（5) 以下說明這種高頻用半導體晶片23的電路動作。首先， 兩個放大電路2 1及22使放大電路2丨動作時關閉放大電路22 ，反之使放大電路22動作時使放大電路21成為關閉而使用 。因此，在理想狀態，放大電路21動作時，放大電路Μ 切斷狀態’即直流電流不用說，高頻電流也不流 體 31之輸出端子33。 策篮 人，而，在上述以往’特別是輸出所放大的輸出信號的接 ° 8和接合線29互相接近時，例如各焊接區26、μ間隔 為140 ym，各接合線28、29長度為728 時，使用^售 電磁場模擬器進行模擬，算出其電感成分的耦合係數κ， 則其電感成分的耦合係數K成為j( = 〇 . 1 6。 因此電磁耦合而放大電路22的晶片上的焊接區25的接地 立（射極電位）會高頻地引起變動。此變動層次變大，本 而=可動作的放大電路22有時會因先前的高頻（間歇）變 ，2。此結果，發生下述問題：從輸出端子33電流流動 沾二言之，放大電路21的輸出信號漏到連接於放大電路22 不勒，端子33 1來。在此情況，最壞引起振盪，動作不良 用5兒’也招致破壞高頻用半導體晶片23的問題。 ，，決此問題’可以下述構成：將各放大電路21、22以 ,1向頻半導體晶片構成，使其以不互相干擾的間隔動 或者即使形成於同一晶片上時，也使在晶片内的配 乃分開。 ι尤 然而，根據此解決方法，封裝製程增加或招致總晶片 、增加，在低成本化及小型化有問題。
第10頁 五、發明說明（6) 此外’如在習知技術所述’為了更縮短接合線長度，也 有下述方法··比周邊降低高頻用半導體晶片的小晶片接合 位置，使半：的焊接區和電路基板的圖案面高度 成為相同，或者在尚頻用半導體晶片開一極小的孔而將半 導體晶片内的接地線通過此孔和晶片背面的接地面連接， 但製程變成複雜，成本增高。 而且’ ^前述，也有利用多數接合線的 隨此、焊—數或封裝體端子U線框架）增加 所以違反日日片尺寸縮小化或封裝體小型化。 發明之概述 :::之目的係提供—種不伴隨 要變更高頻用半導體晶片 無需 等設計、小型又低成本並且J路基板的外部端子 的高頻用半導體裝置》 特別疋两頻特性佳的可靠性高 本發明之半導體裝置為 具備高頻用半導體晶片7勺2 =以亡課題，其特徵在於： 板；裝載半導體晶片.及匕多數尚頻電路部件；電路基 半導體晶片之各高頻電路部件：=:··分別電氣連接 如比在各高頻電路部件的二氣連接機構 變寬般地設置者。 連接機構的各第二連接點間隔 根據上述結構，由 裝體的電路基板尺寸'用半導體晶片尺寸一般比為封 導體晶片的各第一、赴^以電氣連接機構的在高頻用半 各位置不？文變而容易可擴大在電 4 5 4g 8 3 五、發明說明（7) 路基板侧的各第二連接點間隔。 藉此’在上述結構藉由在電路基板側 各第-連接點間隔擴大電氣連接機構 = 電氣連接機構的互感成分。此仕果 二低起因此上述 柄认方成4·、八 此、-°果在上述結構，因所減 低的互感成分而可使可靠极 &主丨3 提高。 j使』罪性，特別疋在尚頻區域的可靠性 -電氣連接機構分別為接地用。 般由於電氣連接機構的互感成分有時可㈣連接於外部 的匹配電路減低，&電氣連接機構為接地氣時，使用這種 匹配電路的互感成分減低困難。 ^而，根據上述結構’即使電氣連接機構分別為接地用 掖，由，電路基板侧的各第二連接點比各第一連接點間隔 擴大電氣連接機構，亦可減低起因於上述電氣連接機構的 互感成分。 此、'·〇果’在上述結構’因起因於接地用電氣連接機構的 互感成分減低而可以簡單的結構實現可靠性，特別是在高 頻區域的可靠性提高。 在上述半導體裝置，電氣連接機構也可以是具有電氣導 電性的接合線。根據上述結構，由於接合線具有延性，柔 軟f ’所以比在相鄰各電路部件的接合線的各第一連接點 間隔’在基板的接合線的各第二連接點間隔變寬般地可容 易設定作為電氣連接機構的接合線。 在上述半導體裝置，最好在前述相鄰各電氣連接機構之 間和上述各電氣連接機構分別離間配置設定於接地電位的
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五、發明說明（8) ^體。根據上述結構，藉由設置設定於接地電位的導體 可變成更大般地設定互感成分減低。 夏在上述半導體裝置，最好設定於前述接地電位的導體為 ς有電氣導電性的金屬線。在上述結構，由於金屬線具有 陡，即柔軟性，所以可使上述金屬線的電氣連接容易化 4在上述半導體裝置，最好設定於前述接地電位的導體和 2述相鄰各電氣連接機構分別成為略等間隔般地配置。根 灰^述結構，藉由將設定於接地電位的導體設於相鄰各電 亂連接機構的中間位置，可使變成更大般地設定互感成分 減低更加確實化。 本發明之另外其他之目的、特掛只欲s 一々~ # a ^符徵及優異之點根據以下所 不之》己載S可十分了解。此外，本發 圖的以下說明當可明白。 纟發月之優點根據參照附 附圖之簡單說明 明實施形態1的半導體裝置概略平面圖。 圖2為上述半導體裝置要部說明圖， 圖，圖2(b)為概略平面圖。 圖2(a)為概略侧面 圖3為關於本發明實施形態2的半 圖3(a)為概略侧面圖，圖3(b)為概略 說明圖， 圖4為顯示在上述各半導體裝 的情況的圖表。 $置的以往可減低電感成分 圖5為習知半導體裝置概略平面圖。 圖6為習知其他半導體裝置概略平面圖。
454|83 五、發明說明（9) =7為和本發明各半導體裝置比較的習知半導體裝置要 部說明圖， 圓Ka)為概略侧面圖，圖7(b)為概略平面圖c 具體實例說明 就本發明實施形態1根據圖1、圖2、圖4及圖7說明如 下0 [實施形態1 ] &將關於本發明半導體裝置的實施形態1模式地顯示於 圖1。如圖1所示’半導體裝置具有作為電路基板的封裝體 11和對於該封裝體丨丨所裝載、電氣上也被連接的略長方體 形狀的高頻用半導體晶片3。 此半導體晶片3例如在半導體晶片3内部分別具有高頻放（ 大用放大電路1及高頻放大用放大電路2作為高頻電路部件 。又，雖然為了說明而舉具有兩個放大電路i、2之例，桓 其放大電路數為多數即可，並不特別限定。又，在圖丨中 ，就各放大電路1、2而言，只圖示輸出級的高頻用雙極電 晶體（bipolar transistor)。 在這種半導體晶片3，放大電路丨的輸出用焊接區 (bonding pad)(例如連接於高頻用雙極電晶體之集極端 子）7、放大電路1的接地用焊接區（例如連接於高^用雙極 電晶體之射極端子，第一連接點）6露出半導體晶片3上面 ’沿著上面的長邊方向一侧邊部設置。 （ 此外，在半導體晶片3，放大電路！的輸入用焊接區“露 出半導體晶片3上面’設於上面的長邊方向他侧邊部（和長 邊方向一侧邊部短邊方向的相反侧）。
454^83 五、發明說明（10) 4· ^ 一方面，放大電路2也和放大電路1同樣，分別設置放 路2的輸出用焊接區（例如連接於高頻用雙極電晶體之 、Μ電路2的接地料接區（例如連接於高頻 射極端子，第一連接點)5、放大電路2的 翰入用焊接區1 6。 12在if 31設置來自放大電路1的封裝體11之輸出端子 2^封裝體11之輸入端子15、來自放大電路2的封裝體 之輸出端子13、封裝w. 柄曰p。. 釘哀體11之輸入端子17，並且是裝載半導 片3而支持的框架且成為接地面的接地電極ι〇設於 裝體11表面（外面）上。 、 因此，上述接地電極10如比半導體晶片3底部面 是大2~3倍程度般地設定其表面積。在這種接地電極 /圍如包圍上述接地電極1〇般地分別設置前述各輸入 如接各輸出端子12、13。此外，前述半導體晶片3 地電極10周邊露出半導體晶片3周圍般地 上 上。又’上述各焊接區、端子或電極係、、由鋼等 良導電體構成的板狀者。 』寻 :且，冑用為金、銀、銅、鋁等金屬的良導電體的 ，汉置分別電氣連接半導體晶片3的各放大電路丨、2 知接£14、16、7、4、6、5和封裝體11之久她工， 架『)15、17、12、13」。的各接合線(電氣連接機構弓;二框 ϋ思 19、8、9。由於這種各接合線2〇等將延性佳的 金屬形成金屬線形狀，所以用微小的力量就可折彎自如。 特別是彼此相鄰的接地用接合線8(關於放大電路丨）和接 4 5 4^8 3 五、發明說明（π) 5^9 ^2} ^ ^ ^ ^ ^ ^ ^ ^ ^ 6, 焊接位置（第I11所接地的框架，即接地電極1(3上的各 焊接。 —連接點）間隔，對於上述接地電極1 0被分別 連接更詳細說明’則各接合線8、9從半導體晶 ί大Λ 2 地電極1G依次如無變化地增加如直線地 擴=般地设置這些接合線間的間隔。 ㈣這1 ί接合線8、9對於離包含半導體晶片3上的各焊接 :互；t I的中央點的半導體晶片3長邊方向一端邊的垂直 以是二】：稱般地擴大設置，可有效擴大上述間隔，所 在ί:方：ϊ ί接合線8、9的一方從半導體晶片3 -端邊 互相對m Α旎引出的情況亦可如這些接合線間隔盡管不 :對稱也向接地電極10擴大般地設 而: :=,、Γ雙方從半導體晶片3 一端邊在度= 互相對ϋ 情況亦可如上述各接合線8、9間隔盡管不 # ί稱也向接地電極10擴大般地設定即可。 心丄L擴比例越大，柄合係數越小，但這種情況 1此：：士;度變長，所以結果電感成分有時會變大 流、要步二 比例的最適當值根據動作頻率或動作電 設定即、封裝體11的全體佈局或金屬線接合的規則 ，1.3件？ 尤上述比例而言，1,2倍〜3倍的範圍内較佳 。 w〜2. 5倍的範圍内更佳，1.4倍〜2.2倍的範圍内最佳
五、發明說明（12) 其=接合線18、19、20、2〇,分別和相鄰的接地用接合 線8、9或信號用接合線18、19、2〇、2〇,平行配置 從半導體晶片3上的各焊接區14、16、7、4 隔 而焊接於各端子15、17、12、13上亦可。 傾穴間隔 這種高頻用半導體晶片3的電路動作和先前說明的 技術相同，兩個放大電路丨及2使放大電路丨動作時關 大電路2，反之使放大電路2動作時使放大電路^為關閉 而使用。 1 茲將利用現有（市售）電磁模擬器模擬根據本發明的相 接地用各接合線8、9間的互感的結果顯示於下。 就這 成為 則上 在圖2(a)的側面圖顯示用於模擬的接合線形狀等 種接合線形狀之例而言，藉由使用金屬線接合 山形狀。 若就這種山形狀以一方的接合線9為例加以說明上 述接合線9互相連續具有上升部9a:從高度2〇〇的半 體晶片3上面的焊接區5向在接地電極1〇的烊接位置斜上方 (從接地電極1 0離間的方向）地延伸；水平部9b :從此上升 部9a水平方向（即和接地電極10表面平行的方向）延伸；及 ，下降部9c :從此水平部9b斜下方（接近接地電極1〇的方 向）地延伸。 上述上升部9a例如從半導體晶片3 一端邊的焊接區5以高 度180 /zm設定於長度（從半導體晶片3 一端邊垂直方向的 長度）25 上述水平部9b設定於長度75 μιη，上述下 降部9c設定於長度6 0 0 em、高度3 80以m(18〇 ym+2⑽
4 5 4¾ 8 3
// m) 〇 圖2係_為了將關於圖i之本發明半導體裝置之特徵部分簡 化而顧示之圖《如圖2所示，在有半絕緣性砷化鎵基板的 半導體晶片3表面設置例如以9〇 "m四角形的理想金屬形 成的焊接區5及焊接區6，利用接地用各接合線8、9分別連 接框架形狀的接地電極10間，使各放大電路i、2分別接地 此外，為了簡化计算，各接合線8、9假設是寬度25以^ 且無厚度的長方形理想金屬。此外，使用頻率以2千兆赫 (GHz)進行。 模擬，纟以往和本發明分別求出兩條接地用接合線 ίΪΐϊ數’…較。在以往’如圖7所示，對於高頻 用”體晶片23垂直且互相平行地配置接地用接合線⑼、 官Ιίΐ發明，比在半導體晶片3上的各輝接區5、6間隔 寬也议定接地電極1〇上的各焊接位置間隔。 二以往的接地用各接合線28、29的各焊接區Μ、25 4隔為W，另一方面連接本發明的各接合線8、9的各 區隔也使其和Μ。將其㈣結果分別顯示於圖4 數Κ使各焊接區間隔W分別變化’分別求出其等時的輕合係 在圖4之X記號，實線為根據習知技術者，從1〇 :二改變焊接區26、25晴。隨著這種間隔W變化， ，。係數K從0.245變化到0 03。根據習知技術的手法
454^83 2 五、發明說明（14) 然而，在這種習知手法，由於焊接區26、25 所以若焊接區數增加，則半導體晶片23的 大， ，產生招致成本增高的問題。 3片尺寸會增加 其次，在根據本發明的手法，係圖2所示的接合 ，以半導體晶片3上的焊接墊6、5間隔為14〇 , 接合線8、9對於半導體晶片3垂直引出丨〇 〇众瓜，直將 擴大接合線8、θ間隔，一面在直線距離6〇〇 之點< 面 於接地電極1 0上。在接地電極丨〇上的接合線8、9間隔 2 5 0 y m。 此時的相鄰兩條接地用各接地線8、9間的麵合係數κ如 圖4所示，成為約〇.〇9 [圖4的黑三角（▲)記號]:得知此 不會擴大半導體晶片3的焊接區6、5間隔而可實現和以在 習知技術手法的平行各接合線28、29間隔擴大到約22〇 的封裝等效的隔離，即起因於各接合線8、9的互感成 分減低。 [實施形態2] 茲根據圖3、圖4說明關於本發明半導體裝置的實施形態 2如下。又，由於高頻用半導體晶片3的電路結構或各 區6、5的設定和先前說明的實施形態丨同樣，所以其說明 省略。 本實施形態2係在前述實施形態1 (圖2所載）的各接合線8 、9間的空間和上述各接合線8、9中間位置的半導體晶片3 上的焊接區4、5、6、7、14、16無連接，焊接連接於接地 電極10(接地電位）的產線（dummy wire)(虚設導體）45而封
第19頁 4 5屬 8 3 2 五、發明說明（15) 裝。 虛線45配置於和兩條接地用各接合線8、9離間的位 更佳係上述各接合線8、9略中間的位置（略等間隔的位 ，即沿著離包含半導體晶片3上的各焊接區6、5間的） 點的半導體晶片3長邊方向一端邊的垂直面的位置。、 此外，在本模擬形態，虛線45設定於和接地用各接人 8、9相肖配線高度及料㈣曰曰曰片3到接地電極1〇 口人線 線8、9直線距離相同。 接。 f本實施形態2，兩條接地用各接合線8、9朝接地電極 1上，從运些接合線的基部侧（+ #體晶片3側）向前端部 側（在接地電極10的各焊接位置侧）依次擴大其各接人 、：間隔，所以在上述各接合線8、9之間產生更寬的空' ’而在上述空間内對於接地電極1〇容易封裝虛線45。 ‘將己Ϊ 的效果(模擬結果)以圖4中的黑四角 (^) §己唬顯不於圖4。兩條接地用各接合線8、9的封 疋於和先前的實施形態1相同。 ^述實施形態2 ’藉由設置虛線45，如圖4所示，顯示 J因=接合線8、9的互感成分的輕合係 7 $，得知可使和以習知技術的手 = :大到270，程度的封裳等效的隔 二二間， 線8、9的互感成分減低更加提高並實現/起因於各接。 :上述實施形態2以配置虛線45之例加以說 上述例，取代虛線“，藉由同樣配置其他導體不，特可 付 上述同樣的效果。又’本發明不限於上述實施各形
第20頁 454S83
五、發明說明（16) 態1 來及=ft不脫離要旨的範圍可種種變形實施。 態1及2所示的所單晶片化的放大電路 1和放大電路2的雙方除了接地用各接 路 =接°線），一方為接地用，其他一方為信號線用亦; 線Ξ;)’的不接僅二半導體晶片3的焊接區到封裝體的端子㈠丨 屬線接人蚀接σ線封& ’而且連到電路基板上的端子的金 屬線接“吏用同樣的手法亦可得到同樣的效果是很明顯的 兆in:,如如放大電路1，適用於在高頻區域ο 片3最有效果广〇〇兆赫〜1 〇〇千兆赫)有增益的半導體晶 用半導俨_杜從除去干擾的觀點，不受所封裝的高頻 用牛導體7〇件限制。 ^ 曰Si Λ此的說明係以下述之例進行：·高頻用半導體 ace up)，以各接合線和封裝體11的端 高頻用丰3 基板進行電氣連接；但作為他例，在 :二裝肉載於封裝體時，從高頻用半導體晶片的端二丨出 的^。配線或基板配線後擴大配線間隔，亦可得到同樣 體：夂’二詳細說明’本發明係互相電氣連接高頻用半導 子Him裝體11或基板侧之際，比在半導體晶片3的端 曰a隔寬地設定封裝體11或基板側的端子間間隔，不使
第21頁 4 5 4另 S 3 2-· ^----- 五、發明說明（17) 半導體晶片3的晶片尺寸增加而 構的例如各接合線8、9具有 為相鄰各電氣連接機 禮晶片3動作的高可靠性化，感a成为A減低’可實現半導 高可靠性。 符別疋在馬頻區域的動作的 此外，在本發明藉由在作為上述相鄰各雷资、車搵媸@Μ 例如各接合線8、9的略中間配署=:各電軋連接機構的 J更加霄現互感成分的減低。 ^ 而且，這種各接合線8、9的設 可使用現有的焊接襞置，所w &施匕3虚線45的s又置， ^ ^ 屐置所U廉價辦得到。再者，本發明 亦無需在為了機構上縮短金屬 Γ:ϊΓ之類的特殊加工，可以非常低以：Ϊ 分是不用說的 的刖述方法’可更加減低電感成 ^說在作為放大電路1、2的功率放大器（power Π 6Γ)方面，伴隨近幾年的驅動電壓低電壓化，為了 ，即出電力’需要如降低輸出級電晶體的輪出阻抗 電η變電流振幅般地設計。由於互感成分效果與 办變化大小成比例而變大，所以如上述功率放大器，需 要大量設定電流振幅時，本發明之效果成為特別大。 本發明特別是在關於作為接地線的接地電極丨0的 刀，使放大電路1、2全體性能惡化的重大主要原因之一的 更，頻率（例如1千兆赫〜10千兆赫）電波利用方面，如前述 可減低電感成分會帶給更高頻率電波利用，例如 話等很大的利益。
國 第22頁 4 5 4g B 3 ___________ 五、發明說明（18) 在發明之詳細說明項中所作的具體實施形態或實施例始 終是要闡明本發明技術内容的，不應只限於這種具體例而 作狹義解釋，在本發明之精神和其次所載之申請專利事項 的範圍内可種種變更實施。 [元件編號說明] 1 放 大 電路（ 頻 電 路部件） 2 放 大 電路（ 高 頻 電 路部件） 3 半 導 體晶片 4 焊 接 區（第 —— 連 接 點） 6 焊 接 區（第 «— 連 接 點） 8 接 合 線（電 氣 連接 機構） 9 接 合 線（電 氣 連 接 機構） 10 接 地 電極 11 封 裝 體（電 路 基 板） 45 虛 線 (虚設 導 體）
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Claims (1)

  1. 森54|s3 申請專利範固 ^一種半導體裝置，其特徵在於：具備 導包含多數各高頻電路部件； 冤路基板.裝載半導體晶片；及 各電虱連接機構：分別電氣連接丰暮辦曰^ 路部件和電路基板， 導體晶片之各高頻電 m2電氣連接機構如比在各高頻電路部件的各 構的各第-連接點間隔 =的各電虱連接機 構的各笛一έM _在電路基板的上述各電氣連接機 第一連接點間隔變寬般地設置者。 其中上述各電 其中上述各電 其中對於上述 2. 如申請專利範圍第丨項之導 氣連接機構分別為錢用。 3. 如申請專利範圍第丨項 '連=構為具有電氣導電性的導接體合裝線置 4. 如申請專利範圍第1項 各第一連接點間隔，上述 ，其中對於上述 的範圍内。 各第一連接點間隔為1. 2倍〜3倍 5. ·如申請專利範圍第1 頻電路部件彼此相鄰。 +導體裝置’其中上述各 6. 如申請專利範園第1項之 氣連接機構如從上述各第一 裝置，其中上述各電 這些電氣連接機構間的間==上述各第二連接點 7. 如申請專利範圍第/項&之增半加導般= 設要置。 氣連接機構如從上述各第導體裝置，其中上述各電 依次這歧電氣連接接點向上述各第二連接點： …=1=;的之間一
    構如從上述各第一連接 六、申請專利範圍 二Ϊ以=的間隔直線擴 基板且有成t ΐ 項之半導體裝置，•中上述電路 電極/。、有成為上述各電氣連接機構的各第二連接點的電接路地 其中上述半導 ’其中上述接 其中相鄰的上 體1曰^片Μ範圍第9項之半導體裝置， 日日片裝載於上述接地電極上。 地2極如/:奢專利範圍第1 °項之半導體裳置 比半導體晶片底部面積大。 述各電氣連接機構如在具有上述:第：、中相鄰的上 上具有假想對稱面般地設置。各第一連接點的電路基板 U·如申請專利範圍第12項之半 涊對稱面在上述電路某板点 ^ ，，、中上述假 14 , ^ 义电路暴扳上成為大致垂直。 4.如申請專利範圍第丨項之 電氣連接機構之間，和上述各’其中在上述各 設定於接地電位的虛設導體虱連接機構分別離間配置 15·如申請專利範圍第14項 設二體為具有電氣導電性的金屬 + 線導體裝置，其中上述虛 .如申凊專利範圍第14項之半導俨奘 設導體如對於相鄰的上述各+體裝置，其中上述虛 隔般地配置。 乳連接機構分別成為略等間 17.如申請專利範圍第14 設導體如成為相鄰述 +導體裝置，其中上述虛 、 電氮連接機構的中間位置般地
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TW089109587A 1999-09-20 2000-05-18 Semiconductor device TW454283B (en)

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TWI473182B (zh) * 2007-04-02 2015-02-11 Kulicke & Soffa Ind Inc 在線弧中形成彎曲的方法

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TWI473182B (zh) * 2007-04-02 2015-02-11 Kulicke & Soffa Ind Inc 在線弧中形成彎曲的方法

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